LED data gets transmitted using signal but not stable yet

* Mark interconnect as unstable

* Explicitly set unstable feature in HIL tests

* WIP append feature set name to artifact

* Add name to feature sets, build all combinations

* Fix tests

* Provide a looping executor for stable async tests

* Fix usb serial jtag

* Hide interconnect types

.cargo/config.toml

@@ -0,0 +1,4 @@
+[alias]
+xtask = "run --package xtask --"
+xfmt = "xtask fmt-packages"
+qa = "xtask run-example qa-test"

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,31 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ["bug", "status:needs-attention"]
+assignees: ''
+
+---
+
+## Bug description
+
+<!-- A clear and concise description of what the bug is. -->
+
+## To Reproduce
+
+<!-- Steps to reproduce the behavior. -->
+1. ...
+2. ...
+
+<!-- Please share the minimal repro of the issue where the bug can be reproduced. -->
+
+<!-- Make sure you are able to reproduce the bug in the `main` branch, too. -->
+
+## Expected behavior
+
+<!-- A clear and concise description of what you expected to happen. Attach screenshots if needed. -->
+
+## Environment
+
+- Target device: [e.g. ESP32-S3] <!-- Use `espflash board-info` to get the target device iformation. -->
+- Crate name and version: [e.g. esp-hal 0.20.0]

.github/ISSUE_TEMPLATE/config.yml

@@ -0,0 +1,8 @@
+blank_issues_enabled: true
+contact_links:
+  - name: Ask questions in Matrix channel (Recommended)
+    url: https://matrix.to/#/#esp-rs:matrix.org
+    about: Ask any questions directly in our Matrix channel.
+  - name: Ask questions in GitHub Discussions
+    url: https://github.com/esp-rs/esp-hal/discussions/new
+    about: Post your questions and engage in discussions via GitHub.

.github/ISSUE_TEMPLATE/feature_request.md

@@ -0,0 +1,24 @@
+---
+name: Feature request
+about: Suggest an idea for this project
+title: ''
+labels: ["enhancement", "status:needs-attention"]
+assignees: ''
+
+---
+
+## Motivations
+
+<!-- If your feature request is related to a problem, please describe it. -->
+
+## Solution
+
+<!-- Describe the solution you'd like. -->
+
+## Alternatives
+
+<!-- Describe any alternative solutions or features you've considered. -->
+
+## Additional context
+
+<!-- Add any other context or screenshots about the feature request here. -->

.github/PULL_REQUEST_TEMPLATE.md

@@ -1,18 +1,22 @@
-## Thank you!
+## Thank you for your contribution!
 
-Thank you for your contribution.
-Please make sure that your submission includes the following:
+We appreciate the time and effort you've put into this pull request.
+To help us review it efficiently, please ensure you've gone through the following checklist:
 
-### Must
+### Submission Checklist 📝
+- [ ] I have updated existing examples or added new ones (if applicable).
+- [ ] I have used `cargo xtask fmt-packages` command to ensure that all changed code is formatted correctly.
+- [ ] My changes were added to the [`CHANGELOG.md`](https://github.com/esp-rs/esp-hal/blob/main/esp-hal/CHANGELOG.md) in the **_proper_** section.
+- [ ] I have added necessary changes to user code to the [Migration Guide](https://github.com/esp-rs/esp-hal/blob/main/esp-hal/MIGRATING-0.21.md).
+- [ ] My changes are in accordance to the [esp-rs API guidelines](https://github.com/esp-rs/esp-hal/blob/main/documentation/API-GUIDELINES.md)
 
-- [ ] The code compiles without `errors` or `warnings`.
-- [ ] All examples work.
-- [ ] `cargo fmt` was run.
-- [ ] Your changes were added to the `CHANGELOG.md` in the proper section.
-- [ ] You updated existing examples or added examples (if applicable).
-- [ ] Added examples are checked in CI
+#### Extra:
+- [ ] I have read the [CONTRIBUTING.md guide](https://github.com/esp-rs/esp-hal/blob/main/documentation/CONTRIBUTING.md) and followed its instructions.
 
-### Nice to have
+### Pull Request Details 📖
 
-- [ ] You add a description of your work to this PR.
-- [ ] You added proper docs for your newly added features and code.
+#### Description
+Please provide a clear and concise description of your changes, including the motivation behind these changes. The context is crucial for the reviewers.
+
+#### Testing
+Describe how you tested your changes.

.github/actions/check-esp-hal/action.yml

@@ -0,0 +1,68 @@
+name: Build and Check
+description: Build and check the esp-hal and esp-lp-hal pacakges for a specified device
+inputs:
+  device:
+    description: "Device SOC"
+    required: true
+  target:
+    description: "Target"
+    required: true
+  toolchain:
+    description: "Toolchain channel"
+    required: true
+runs:
+  using: "composite"
+  steps:
+    - name: Set up cargo environment
+      shell: bash
+      run: |
+        # Convert the target triple from kebab-case to SCREAMING_SNAKE_CASE:
+        big_target=$(echo "${{ matrix.device.target }}" | tr [:lower:] [:upper:] | tr '-' '_')
+        # Set the *target specific* RUSTFLAGS for the current device:
+        echo "CARGO_TARGET_${big_target}_RUSTFLAGS=-Dwarnings" >> $GITHUB_ENV
+        # Linting toolchain (stable cant build documentation)
+        if [ "${{ inputs.toolchain }}" == "nightly" ]; then
+          echo "LINTING_TOOLCHAIN=+nightly" >> $GITHUB_ENV
+        else
+          echo "LINTING_TOOLCHAIN=+esp" >> $GITHUB_ENV
+        fi
+    # Clippy and docs checks
+    - name: Clippy
+      shell: bash
+      run: cargo $LINTING_TOOLCHAIN xtask lint-packages --chips ${{ inputs.device }}
+    - name: Check doc-tests
+      shell: bash
+      run: cargo $LINTING_TOOLCHAIN xtask run-doc-test esp-hal ${{ inputs.device }}
+    - name: Check documentation
+      shell: bash
+      run: cargo $LINTING_TOOLCHAIN xtask build-documentation --packages esp-hal --chips ${{ inputs.device }}
+    # Build all supported examples for the low-power core first (if present):
+    - name: Build prerequisite examples (esp-lp-hal)
+      shell: bash
+      if: contains(fromJson('["esp32c6", "esp32s2", "esp32s3"]'), inputs.device)
+      run: cargo +${{ inputs.toolchain }} xtask build-examples esp-lp-hal ${{ inputs.device }}
+    - name: Check esp-lp-hal documentation
+      shell: bash
+      if: contains(fromJson('["esp32c6", "esp32s2", "esp32s3"]'), inputs.device)
+      run: cargo $LINTING_TOOLCHAIN xtask build-documentation --packages esp-lp-hal --chips ${{ inputs.device }}
+    # Make sure we're able to build the HAL without the default features
+    # enabled:
+    - name: Build (no features)
+      shell: bash
+      run: |
+        cargo xtask build-package \
+        	--no-default-features \
+          --toolchain=${{ inputs.toolchain }} \
+        	--features=${{ inputs.device }} \
+        	--target=${{ inputs.target }} \
+        	esp-hal
+    - name: Build (examples)
+      env:
+        CI: 1
+      shell: bash
+      run: cargo +${{ inputs.toolchain }} xtask build-examples esp-hal ${{ inputs.device }} --debug
+    - name: Build (qa-test)
+      env:
+        CI: 1
+      shell: bash
+      run: cargo +${{ inputs.toolchain }} xtask build-examples qa-test ${{ inputs.device }} --debug

.github/workflows/changelog.yml

@@ -1,7 +1,14 @@
-name: Change log check
+name: Changelog check
 
 on:
   pull_request:
+    # We will not track changes for the following packages/directories.
+    paths-ignore:
+      - "/examples/"
+      - "/extras/"
+      - "/hil-tests/"
+      - "/resources/"
+      - "/xtask/"
     # Run on labeled/unlabeled in addition to defaults to detect
     # adding/removing skip-changelog labels.
     types: [opened, reopened, labeled, unlabeled, synchronize]
@@ -12,10 +19,162 @@ jobs:
 
     steps:
       - name: Checkout sources
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
-      - uses: dangoslen/changelog-enforcer@v3
+      - name: Check which package is modified
+        uses: dorny/paths-filter@v3
+        id: changes
         with:
-          changeLogPath: CHANGELOG.md
+          filters: |
+            esp-alloc:
+              - 'esp-alloc/**'
+            esp-backtrace:
+              - 'esp-backtrace/**'
+            esp-build:
+              - 'esp-build/**'
+            esp-config:
+              - 'esp-config/**'
+            esp-hal:
+              - 'esp-hal/**'
+            esp-hal-embassy:
+              - 'esp-hal-embassy/**'
+            esp-hal-procmacros:
+              - 'esp-hal-procmacros/**'
+            esp-ieee802154:
+              - 'esp-ieee802154/**'
+            esp-lp-hal:
+              - 'esp-lp-hal/**'
+            esp-metadata:
+              - 'esp-metadata/**'
+            esp-println:
+              - 'esp-println/**'
+            esp-riscv-rt:
+              - 'esp-riscv-rt/**'
+            esp-storage:
+              - 'esp-storage/**'
+            esp-wifi:
+              - 'esp-wifi/**'
+            xtensa-lx:
+              - 'xtensa-lx/**'
+            xtensa-lx-rt:
+              - 'xtensa-lx-rt/**'
+
+      - name: Check that changelog updated (esp-alloc)
+        if: steps.changes.outputs.esp-alloc == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-alloc/CHANGELOG.md
           skipLabels: "skip-changelog"
-          missingUpdateErrorMessage: "Please add a changelog entry in the CHANGELOG.md file."
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-alloc/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-backtrace)
+        if: steps.changes.outputs.esp-backtrace == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-backtrace/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-backtrace/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-build)
+        if: steps.changes.outputs.esp-build == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-build/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-build/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-config)
+        if: steps.changes.outputs.esp-config == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-config/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-config/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-hal)
+        if: steps.changes.outputs.esp-hal == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-hal/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-hal/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-hal-embassy)
+        if: steps.changes.outputs.esp-hal-embassy == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-hal-embassy/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-hal-embassy/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-hal-procmacros)
+        if: steps.changes.outputs.esp-hal-procmacros == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-hal-procmacros/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-hal-procmacros/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-ieee802154)
+        if: steps.changes.outputs.esp-ieee802154 == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-ieee802154/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-ieee802154/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-lp-hal)
+        if: steps.changes.outputs.esp-lp-hal == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-lp-hal/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-lp-hal/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-println)
+        if: steps.changes.outputs.esp-println == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-println/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-println/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-riscv-rt)
+        if: steps.changes.outputs.esp-riscv-rt == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-riscv-rt/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-riscv-rt/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-storage)
+        if: steps.changes.outputs.esp-storage == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-storage/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-storage/CHANGELOG.md file."
+
+      - name: Check that changelog updated (esp-wifi)
+        if: steps.changes.outputs.esp-wifi == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: esp-wifi/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the esp-wifi/CHANGELOG.md file."
+
+      - name: Check that changelog updated (xtensa-lx)
+        if: steps.changes.outputs.xtensa-lx == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: xtensa-lx/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the xtensa-lx/CHANGELOG.md file."
+
+      - name: Check that changelog updated (xtensa-lx-rt)
+        if: steps.changes.outputs.xtensa-lx-rt == 'true'
+        uses: dangoslen/changelog-enforcer@v3
+        with:
+          changeLogPath: xtensa-lx-rt/CHANGELOG.md
+          skipLabels: "skip-changelog"
+          missingUpdateErrorMessage: "Please add a changelog entry in the xtensa-lx-rt/CHANGELOG.md file."

.github/workflows/ci.yml

@@ -1,21 +1,31 @@
+# NOTE:
+#
+# When adding support for a new chip to `esp-hal`, there are a number of
+# updates which must be made to the CI workflow in order to reflect this; the
+# changes are:
+#
+# 1.) In the 'esp-hal' job, add the name of the chip to the `matrix.soc` array.
+# 1a.) If the device has a low-power core (which is supported in
+#      `esp-lp-hal`), then update the `if` condition to build prerequisites.
+# 2.) In the 'msrv' job, add checks as needed for the new chip.
+
 name: CI
 
 on:
   pull_request:
-    paths-ignore:
-      - "**/README.md"
   push:
     branches-ignore:
       - "gh-readonly-queue/**"
-    paths-ignore:
-      - "**/README.md"
+      - "main"
   merge_group:
   workflow_dispatch:
 
 env:
   CARGO_TERM_COLOR: always
   GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-  MSRV: "1.67.0"
+  MSRV: "1.83.0"
+  RUSTDOCFLAGS: -Dwarnings
+  DEFMT_LOG: trace
 
 # Cancel any currently running workflows from the same PR, branch, or
 # tag when a new workflow is triggered.
@@ -27,543 +37,90 @@ concurrency:
 
 jobs:
   # --------------------------------------------------------------------------
-  # Check Packages
+  # Build Packages
 
-  esp-hal-smartled:
+  esp-hal:
+    name: esp-hal (${{ matrix.device.soc }})
     runs-on: ubuntu-latest
+    env:
+      SSID: SSID
+      PASSWORD: PASSWORD
+      STATIC_IP: 1.1.1.1
+      GATEWAY_IP: 1.1.1.1
+      HOST_IP: 1.1.1.1
 
+    strategy:
+      fail-fast: false
+      matrix:
+        device: [
+            # RISC-V devices:
+            { soc: "esp32c2", target: "riscv32imc-unknown-none-elf", toolchain: "stable" },
+            { soc: "esp32c3", target: "riscv32imc-unknown-none-elf", toolchain: "stable" },
+            { soc: "esp32c6", target: "riscv32imac-unknown-none-elf", toolchain: "stable" },
+            { soc: "esp32h2", target: "riscv32imac-unknown-none-elf", toolchain: "stable" },
+            # Xtensa devices:
+            { soc: "esp32", target: "xtensa-esp32-none-elf", toolchain: "esp" },
+            { soc: "esp32s2", target: "xtensa-esp32s2-none-elf", toolchain: "esp" },
+            { soc: "esp32s3", target: "xtensa-esp32s3-none-elf", toolchain: "esp" },
+          ]
     steps:
       - uses: actions/checkout@v4
+
+      # Install the Rust toolchain for Xtensa devices:
+      - uses: esp-rs/xtensa-toolchain@v1.5
+        with:
+          ldproxy: false
+          version: 1.83.0.1
+      # Install the Rust stable toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
           target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
-          toolchain: nightly
+          toolchain: stable
           components: rust-src
-      - uses: esp-rs/xtensa-toolchain@v1.5
-        with:
-          ldproxy: false
-          override: false
+
       - uses: Swatinem/rust-cache@v2
 
-      # Build all RISC-V targets:
-      - name: build (esp32c3)
-        run: cd esp-hal-smartled/ && cargo +nightly build -Zbuild-std=core --target=riscv32imc-unknown-none-elf --features=esp32c3
-      - name: build (esp32c6)
-        run: cd esp-hal-smartled/ && cargo +nightly build -Zbuild-std=core --target=riscv32imac-unknown-none-elf --features=esp32c6
-      - name: build (esp32h2)
-        run: cd esp-hal-smartled/ && cargo +nightly build -Zbuild-std=core --target=riscv32imac-unknown-none-elf --features=esp32h2
-      # Build all Xtensa targets:
-      - name: build (esp32)
-        run: cd esp-hal-smartled/ && cargo +esp build -Zbuild-std=core --target=xtensa-esp32-none-elf --features=esp32,xtal-40mhz
-      - name: build (esp32s2)
-        run: cd esp-hal-smartled/ && cargo +esp build -Zbuild-std=core --target=xtensa-esp32s2-none-elf --features=esp32s2
-      - name: build (esp32s3)
-        run: cd esp-hal-smartled/ && cargo +esp build -Zbuild-std=core --target=xtensa-esp32s3-none-elf --features=esp32s3
-      # Ensure documentation can be built (requires a chip feature!)
-      - name: rustdoc
-        run: cd esp-hal-smartled/ && cargo doc -Zbuild-std=core --target=riscv32imc-unknown-none-elf --features=esp32c3
+      - name: Build and Check
+        uses: ./.github/actions/check-esp-hal
+        with:
+          device: ${{ matrix.device.soc }}
+          target: ${{ matrix.device.target }}
+          toolchain: ${{ matrix.device.toolchain }}
 
-  esp-riscv-rt:
+  extras:
     runs-on: ubuntu-latest
 
     steps:
       - uses: actions/checkout@v4
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
+          toolchain: stable
       - uses: Swatinem/rust-cache@v2
 
-      - name: Build esp-riscv-rt (riscv32imc, no features)
-        run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf
-      - name: Build esp-riscv-rt (riscv32imac, no features)
-        run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf
-      - name: Build esp-riscv-rt (riscv32imc, all features)
-        run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf --features=ci
-      - name: Build esp-riscv-rt (riscv32imac, all features)
-        run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf --features=ci
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp-riscv-rt/ && cargo doc
-
-  esp-ulp-riscv-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imc-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      - name: build esp-ulp-riscv-hal (esp32s2)
-        run: cd esp-ulp-riscv-hal/ && cargo build --release --features=esp32s2 --examples
-      - name: build esp-ulp-riscv-hal (esp32s3)
-        run: cd esp-ulp-riscv-hal/ && cargo build --release --features=esp32s3 --examples
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp-ulp-riscv-hal/ && cargo doc --features=esp32s3
-
-  esp32-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: esp-rs/xtensa-toolchain@v1.5
-        with:
-          default: true
-          buildtargets: esp32
-          ldproxy: false
-      - uses: Swatinem/rust-cache@v2
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      - name: build esp32-hal (no features)
-        run: cd esp32-hal/ && cargo build --examples
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32-hal (common features)
-        run: |
-          cd esp32-hal/
-          cargo build --examples --features=eh1,ufmt,log
-          cargo build --examples --features=eh1,ufmt,defmt
-      - name: check esp32-hal (embassy)
-        run: |
-          cd esp32-hal/
-          cargo check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-          cargo check --example=embassy_multicore --features=embassy,embassy-time-timg0,embassy-executor-thread
-          cargo check --example=embassy_multicore_interrupt --features=embassy,embassy-time-timg0,embassy-executor-interrupt
-          cargo check --example=embassy_multiprio --features=embassy,embassy-time-timg0,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32-hal (embassy, async)
-        run: |
-          cd esp32-hal/
-          cargo check --example=embassy_wait --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo check --example=embassy_spi --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo check --example=embassy_serial --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo check --example=embassy_i2c --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo check --example=embassy_i2s_read --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo check --example=embassy_i2s_sound --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo check --example=embassy_rmt_rx --features=embassy,embassy-time-timg0,async,embassy-executor-thread --release
-          cargo check --example=embassy_rmt_tx --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-      - name: check esp32-hal (embassy, log/defmt)
-        run: |
-          cd esp32-hal/
-          cargo check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,defmt
-          cargo check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,log
-      - name: check esp32-hal (psram)
-        run: cd esp32-hal/ && cargo check --example=psram --features=psram-2m --release # This example requires release!
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32-hal/ && cargo doc --features=eh1
-
-  esp32c2-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imc-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      # We also use this as an opportunity to verify that the examples link
-      # for each supported image format.
-      - name: build esp32c2-hal (no features)
-        run: cd esp32c2-hal/ && cargo build --examples
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32c2-hal (common features)
-        run: |
-          cd esp32c2-hal/
-          cargo +nightly build --examples --features=eh1,ufmt,log
-          cargo +nightly build --examples --features=eh1,ufmt,defmt
-      - name: check esp32c2-hal (async, systick)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-systick,embassy-executor-thread
-      - name: check esp32c2-hal (async, timg0)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-      - name: check esp32c2-hal (async, gpio)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_wait --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c2-hal (async, multiprio)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_multiprio --features=embassy,embassy-time-systick,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32c2-hal (async, spi)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_spi --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c2-hal (async, serial)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_serial --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c2-hal (async, i2c)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c2-hal (interrupt-preemption)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption
-      - name: check esp32c2-hal (direct-vectoring)
-        run: cd esp32c2-hal/ && cargo +nightly check --example=direct-vectoring --features=direct-vectoring
-      - name: check esp32c2-hal (embassy, log/defmt)
-        run: |
-          cd esp32c2-hal/
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32c2-hal/ && cargo doc --features=eh1
-
-  esp32c3-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imc-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      - name: build esp32c3-hal (no features)
-        run: cd esp32c3-hal/ && cargo +nightly build --examples
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32c3-hal (common features)
-        run: |
-          cd esp32c3-hal/
-          cargo +nightly build --examples --features=eh1,ufmt,log
-          cargo +nightly build --examples --features=eh1,ufmt,defmt
-      - name: check esp32c3-hal (async, systick)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-systick,embassy-executor-thread
-      - name: check esp32c3-hal (async, timg0)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-      - name: check esp32c3-hal (async, gpio)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_wait --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c3-hal (async, multiprio)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_multiprio --features=embassy,embassy-time-systick,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32c3-hal (async, spi)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_spi --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c3-hal (async, serial)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_serial --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c3-hal (async, i2c)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c3-hal (async, usb_serial_jtag)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=embassy_usb_serial_jtag --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c3-hal (interrupt-preemption)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption
-      - name: check esp32c3-hal (direct-vectoring)
-        run: cd esp32c3-hal/ && cargo +nightly check --example=direct-vectoring --features=direct-vectoring
-      - name: check esp32c3-hal (embassy, log/defmt)
-        run: |
-          cd esp32c3-hal/
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32c3-hal/ && cargo doc --features=eh1
-
-  esp32c6-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imac-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # build the lp-hal examples first to make sure the examples which expect
-      # the ELF files to be present will compile
-      - name: build esp32c6-lp-hal prerequisites
-        run: cd esp32c6-lp-hal/ && cargo +nightly build --release --examples
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      # We also use this as an opportunity to verify that the examples link
-      # for each supported image format.
-      - name: build esp32c6-hal (no features)
-        run: cd esp32c6-hal/ && cargo +nightly build --examples
-      - name: build esp32c6-hal (flip-link feature)
-        run: cd esp32c6-hal/ && cargo +nightly build --examples --features=flip-link
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32c6-hal (common features)
-        run: |
-          cd esp32c6-hal/
-          cargo +nightly build --examples --features=eh1,ufmt,log
-          cargo +nightly build --examples --features=eh1,ufmt,defmt
-      - name: check esp32c6-hal (async, systick)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-systick,embassy-executor-thread
-      - name: check esp32c6-hal (async, timg0)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-      - name: check esp32c6-hal (async, gpio)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_wait --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c6-hal (async, multiprio)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_multiprio --features=embassy,embassy-time-systick,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32c6-hal (async, spi)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_spi --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c6-hal (async, serial)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_serial --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c6-hal (async, i2c)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32c6-hal (interrupt-preemption)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption
-      - name: check esp32c6-hal (direct-vectoring)
-        run: cd esp32c6-hal/ && cargo +nightly check --example=direct-vectoring --features=direct-vectoring
-      - name: check esp32c6-hal (embassy, log/defmt)
-        run: |
-          cd esp32c6-hal/
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32c6-hal/ && cargo doc --features=eh1
-
-  esp32c6-lp-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imac-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      - name: build esp32c6-lp-hal (no features)
-        run: cd esp32c6-lp-hal/ && cargo +nightly build --release --examples
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32c6-lp-hal/ && cargo doc
-
-  esp32h2-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imac-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      # We also use this as an opportunity to verify that the examples link
-      # for each supported image format.
-      - name: build esp32h2-hal (no features)
-        run: cd esp32h2-hal/ && cargo +nightly build --examples
-      - name: build esp32h2-hal (flip-link feature)
-        run: cd esp32h2-hal/ && cargo +nightly build --examples --features=flip-link
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32h2-hal (common features)
-        run: |
-          cd esp32h2-hal/
-          cargo +nightly build --examples --features=eh1,ufmt,log
-          cargo +nightly build --examples --features=eh1,ufmt,defmt
-      - name: check esp32h2-hal (async, systick)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-systick,embassy-executor-thread
-      - name: check esp32h2-hal (async, timg0)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-      - name: check esp32h2-hal (async, gpio)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_wait --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32h2-hal (async, multiprio)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_multiprio --features=embassy,embassy-time-systick,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32h2-hal (async, spi)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_spi --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32h2-hal (async, serial)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_serial --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32h2-hal (async, i2c)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=embassy_i2c --features=embassy,embassy-time-systick,embassy-executor-thread,async
-      - name: check esp32h2-hal (interrupt-preemption)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=interrupt_preemption --features=interrupt-preemption
-      - name: check esp32h2-hal (direct-vectoring)
-        run: cd esp32h2-hal/ && cargo +nightly check --example=direct-vectoring --features=direct-vectoring
-      - name: check esp32h2-hal (embassy, log/defmt)
-        run: |
-          cd esp32h2-hal/
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,defmt
-          cargo +nightly check --examples --features=embassy,embassy-time-timg0,embassy-executor-thread,log
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32h2-hal/ && cargo doc --features=eh1
-
-  esp32s2-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: esp-rs/xtensa-toolchain@v1.5
-        with:
-          default: true
-          buildtargets: esp32s2
-          ldproxy: false
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imc-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
-      # the ELF files to be present will compile
-      - name: build esp-ulp-riscv-hal prerequisites
-        run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s2 --examples
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      - name: check esp32s2-hal (no features)
-        run: cd esp32s2-hal/ && cargo +esp build --examples
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32s2-hal (common features)
-        run: |
-          cd esp32s2-hal/
-          cargo +esp build --examples --features=eh1,ufmt,log
-          cargo +esp build --examples --features=eh1,ufmt,defmt
-      # FIXME: `time-systick` feature disabled for now, see 'esp32s2-hal/Cargo.toml'.
-      # - name: check esp32s2-hal (async, systick)
-      #   run: cd esp32s2-hal/ && cargo check --example=embassy_hello_world --features=embassy,embassy-time-systick,executor
-      - name: check esp32s2-hal (embassy, timg0)
-        run: |
-          cd esp32s2-hal/
-          cargo +esp check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-          cargo +esp check --example=embassy_multiprio --features=embassy,embassy-time-timg0,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32s2-hal (embassy, systick)
-        run: |
-          cd esp32s2-hal/
-          cargo +esp check --example=embassy_hello_world --features=embassy,embassy-time-systick,embassy-executor-thread
-          cargo +esp check --example=embassy_multiprio --features=embassy,embassy-time-systick,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32s2-hal (embassy, timg0, async)
-        run: |
-          cd esp32s2-hal/
-          cargo +esp check --example=embassy_wait --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_spi --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_serial --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2c --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2s_read --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2s_sound --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_rmt_rx --features=embassy,embassy-time-timg0,async,embassy-executor-thread --release
-          cargo +esp check --example=embassy_rmt_tx --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-      - name: check esp32s2-hal (embassy, systick, async)
-        run: |
-          cd esp32s2-hal/
-          cargo +esp check --example=embassy_wait --features=embassy,embassy-time-systick,async,embassy-executor-thread
-          cargo +esp check --example=embassy_spi --features=embassy,embassy-time-systick,async,embassy-executor-thread
-          cargo +esp check --example=embassy_serial --features=embassy,embassy-time-systick,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2c --features=embassy,embassy-time-systick,async,embassy-executor-thread
-      - name: check esp32s2-hal (embassy, log/defmt)
-        run: |
-          cd esp32s2-hal/
-          cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,defmt
-          cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,log
-      - name: check esp32s2-hal (psram)
-        run: cd esp32s2-hal/ && cargo +esp check --example=psram --features=psram-2m --release # This example requires release!
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32s2-hal/ && cargo +esp doc --features=eh1
-
-  esp32s3-hal:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: esp-rs/xtensa-toolchain@v1.5
-        with:
-          default: true
-          buildtargets: esp32s3
-          ldproxy: false
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imc-unknown-none-elf
-          toolchain: nightly
-          components: rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # build the esp-ulp-riscv-hal examples first to make sure the examples which expect
-      # the ELF files to be present will compile
-      - name: build esp-ulp-riscv-hal prerequisites
-        run: cd esp-ulp-riscv-hal/ && cargo +nightly build --release --features=esp32s3 --examples
-
-      # Perform a full build initially to verify that the examples not only
-      # build, but also link successfully.
-      # We also use this as an opportunity to verify that the examples link
-      # for each supported image format.
-      - name: build esp32s3-hal (no features)
-        run: cd esp32s3-hal/ && cargo +esp build --examples
-      # Subsequent steps can just check the examples instead, as we're already
-      # confident that they link.
-      - name: check esp32s3-hal (common features)
-        run: |
-          cd esp32s3-hal/
-          cargo +esp build --examples --features=eh1,ufmt,log
-          cargo +esp build --examples --features=eh1,ufmt,defmt
-      - name: check esp32s3-hal (embassy, timg0)
-        run: |
-          cd esp32s3-hal/
-          cargo +esp check --example=embassy_hello_world --features=embassy,embassy-time-timg0,embassy-executor-thread
-          cargo +esp check --example=embassy_multicore --features=embassy,embassy-time-timg0,embassy-executor-thread
-          cargo +esp check --example=embassy_multicore_interrupt --features=embassy,embassy-time-timg0,embassy-executor-interrupt
-          cargo +esp check --example=embassy_multiprio --features=embassy,embassy-time-timg0,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32s3-hal (embassy, systick)
-        run: |
-          cd esp32s3-hal/
-          cargo +esp check --example=embassy_hello_world --features=embassy,embassy-time-systick,embassy-executor-thread
-          cargo +esp check --example=embassy_multicore --features=embassy,embassy-time-systick,embassy-executor-thread
-          cargo +esp check --example=embassy_multicore_interrupt --features=embassy,embassy-time-systick,embassy-executor-interrupt
-          cargo +esp check --example=embassy_multiprio --features=embassy,embassy-time-systick,embassy-executor-thread,embassy-executor-interrupt
-      - name: check esp32s3-hal (embassy, timg0, async)
-        run: |
-          cd esp32s3-hal/
-          cargo +esp check --example=embassy_wait --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_spi --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_serial --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2c --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2s_read --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2s_sound --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_rmt_rx --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-          cargo +esp check --example=embassy_rmt_tx --features=embassy,embassy-time-timg0,async,embassy-executor-thread
-      - name: check esp32s3-hal (embassy, systick, async)
-        run: |
-          cd esp32s3-hal/
-          cargo +esp check --example=embassy_wait --features=embassy,embassy-time-systick,async,embassy-executor-thread
-          cargo +esp check --example=embassy_spi --features=embassy,embassy-time-systick,async,embassy-executor-thread
-          cargo +esp check --example=embassy_serial --features=embassy,embassy-time-systick,async,embassy-executor-thread
-          cargo +esp check --example=embassy_i2c --features=embassy,embassy-time-systick,async,embassy-executor-thread
-      - name: check esp32s3-hal (octal psram and psram)
-        run: | # This examples require release!
-          cd esp32s3-hal/
-          cargo +esp check --example=octal_psram --features=opsram-2m --release
-          cargo +esp check --example=psram --features=psram-2m --release
-      - name: check esp32s3-hal (embassy, log/defmt)
-        run: |
-          cd esp32s3-hal/
-          cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,defmt
-          cargo +esp check --examples --features=embassy,embassy-time-timg0,embassy-executor-interrupt,embassy-executor-thread,log
-      # Ensure documentation can be built
-      - name: rustdoc
-        run: cd esp32s3-hal/ && cargo doc --features=eh1
+      - name: Install dependencies
+        run: sudo apt-get update && sudo apt-get -y install musl-tools libudev-dev pkg-config
+      # Build the extra crates
+      - name: Build the bench-server
+        run: cd extras/bench-server && cargo build
+      - name: Build esp-wifishark
+        run: cd extras/esp-wifishark && cargo build
+      - name: Build ieee802154-sniffer
+        run: cd extras/ieee802154-sniffer && cargo build
 
   # --------------------------------------------------------------------------
   # MSRV
 
-  msrv-riscv:
+  msrv:
     runs-on: ubuntu-latest
     env:
       RUSTC_BOOTSTRAP: 1
 
     steps:
       - uses: actions/checkout@v4
+      - uses: esp-rs/xtensa-toolchain@v1.5
+        with:
+          ldproxy: false
+          version: ${{ env.MSRV }}
       - uses: dtolnay/rust-toolchain@v1
         with:
           target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
@@ -571,127 +128,42 @@ jobs:
           components: rust-src
       - uses: Swatinem/rust-cache@v2
 
-      # Build the esp32c6-lp-hal examples first. This is done to ensure the
-      # examples which expect the ELF files to be present will compile:
-      - name: build esp32c6-lp-hal prerequisites
-        run: cd esp32c6-lp-hal && cargo build --release --examples
-
       # Verify the MSRV for all RISC-V chips.
-      - name: msrv (esp32c2-hal)
+      - name: msrv RISCV (esp-hal)
         run: |
-          cd esp32c2-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
-      - name: msrv (esp32c3-hal)
-        run: |
-          cd esp32c3-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
-      - name: msrv (esp32c6-hal)
-        run: |
-          cd esp32c6-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
-      - name: msrv (esp32c6-lp-hal)
-        run: |
-          cd esp32c6-lp-hal/
-          cargo build
-      - name: msrv (esp32h2-hal)
-        run: |
-          cd esp32h2-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
+          cargo xtask build-package --features=esp32c2,ci --target=riscv32imc-unknown-none-elf   esp-hal
+          cargo xtask build-package --features=esp32c3,ci --target=riscv32imc-unknown-none-elf   esp-hal
+          cargo xtask build-package --features=esp32c6,ci --target=riscv32imac-unknown-none-elf  esp-hal
+          cargo xtask build-package --features=esp32h2,ci --target=riscv32imac-unknown-none-elf  esp-hal
 
-  msrv-xtensa:
-    runs-on: ubuntu-latest
-    env:
-      RUSTC_BOOTSTRAP: 1
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          target: riscv32imc-unknown-none-elf
-          toolchain: ${{ env.MSRV }}
-          components: rust-src
-      - uses: esp-rs/xtensa-toolchain@v1.5
-        with:
-          ldproxy: false
-          version: ${{ env.MSRV }}
-      - uses: Swatinem/rust-cache@v2
-
-      # Build the `esp-ulp-riscv-hal` examples first. This is done to ensure
-      # the examples which expect the ELF files to be present will compile:
-      - name: build esp-ulp-riscv-hal prerequisites
-        run: cd esp-ulp-riscv-hal && cargo build --release --features=esp32s3 --examples
-
-      # Verify the MSRV for all Xtensa chips:
-      - name: msrv (esp32-hal)
+      - name: msrv RISCV (esp-wifi)
         run: |
-          cd esp32-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
-      - name: msrv (esp32s2-hal)
+          cargo xtask build-package --features=esp32c2,wifi,ble,esp-hal/unstable --target=riscv32imc-unknown-none-elf   esp-wifi
+          cargo xtask build-package --features=esp32c3,wifi,ble,esp-hal/unstable --target=riscv32imc-unknown-none-elf   esp-wifi
+          cargo xtask build-package --features=esp32c6,wifi,ble,esp-hal/unstable --target=riscv32imac-unknown-none-elf  esp-wifi
+          cargo xtask build-package --features=esp32h2,ble,esp-hal/unstable --target=riscv32imac-unknown-none-elf  esp-wifi
+
+        # Verify the MSRV for all Xtensa chips:
+      - name: msrv Xtensa (esp-hal)
         run: |
-          cd esp32s2-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
-      - name: msrv (esp32s3-hal)
+          cargo xtask build-package --toolchain=esp --features=esp32,ci   --target=xtensa-esp32-none-elf   esp-hal
+          cargo xtask build-package --toolchain=esp --features=esp32s2,ci --target=xtensa-esp32s2-none-elf esp-hal
+          cargo xtask build-package --toolchain=esp --features=esp32s3,ci --target=xtensa-esp32s3-none-elf esp-hal
+
+      - name: msrv Xtensa (esp-wifi)
         run: |
-          cd esp32s3-hal/
-          cargo build --features=eh1,ufmt,log
-          cargo build --features=defmt
+          cargo xtask build-package --toolchain=esp --features=esp32,wifi,ble,esp-hal/unstable   --target=xtensa-esp32-none-elf   esp-wifi
+          cargo xtask build-package --toolchain=esp --features=esp32s2,wifi,esp-hal/unstable     --target=xtensa-esp32s2-none-elf esp-wifi
+          cargo xtask build-package --toolchain=esp --features=esp32s3,wifi,ble,esp-hal/unstable --target=xtensa-esp32s3-none-elf esp-wifi
+
+      - name: msrv (esp-lp-hal)
+        run: |
+          cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf esp-lp-hal
+          cargo xtask build-package --features=esp32s2 --target=riscv32imc-unknown-none-elf  esp-lp-hal
+          cargo xtask build-package --features=esp32s3 --target=riscv32imc-unknown-none-elf  esp-lp-hal
 
   # --------------------------------------------------------------------------
-  # Lint
-
-  clippy-riscv:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: dtolnay/rust-toolchain@v1
-        with:
-          toolchain: nightly
-          targets: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
-          components: clippy,rust-src
-      - uses: Swatinem/rust-cache@v2
-
-      # Run 'cargo clippy' on all packages targeting RISC-V:
-      - name: clippy (esp-riscv-rt)
-        run: cd esp-riscv-rt && cargo clippy --target=riscv32imc-unknown-none-elf -- -D warnings
-      - name: clippy (esp-ulp-riscv-hal, esp32s2)
-        run: cd esp-ulp-riscv-hal && cargo clippy --features=esp32s2 -- -D warnings
-      - name: clippy (esp-ulp-riscv-hal, esp32s3)
-        run: cd esp-ulp-riscv-hal && cargo clippy --features=esp32s3 -- -D warnings
-      - name: clippy (esp32c2-hal)
-        run: cd esp32c2-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32c3-hal)
-        run: cd esp32c3-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32c6-hal)
-        run: cd esp32c6-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32c6-lp-hal)
-        run: cd esp32c6-lp-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32h2-hal)
-        run: cd esp32h2-hal && cargo clippy -- -D warnings
-
-  clippy-xtensa:
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: esp-rs/xtensa-toolchain@v1.5
-        with:
-          ldproxy: false
-      - uses: Swatinem/rust-cache@v2
-
-      # Run 'cargo clippy' on all packages targeting Xtensa:
-      - name: clippy (esp32-hal)
-        run: cd esp32-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32s2-hal)
-        run: cd esp32s2-hal && cargo clippy -- -D warnings
-      - name: clippy (esp32s3-hal)
-        run: cd esp32s3-hal && cargo clippy -- -D warnings
+  # Format
 
   rustfmt:
     runs-on: ubuntu-latest
@@ -707,29 +179,20 @@ jobs:
       - uses: Swatinem/rust-cache@v2
 
       # Check the formatting of all packages:
-      - name: rustfmt (esp-hal-common)
-        run: cargo fmt --all --manifest-path=esp-hal-common/Cargo.toml -- --check
-      - name: rustfmt (esp-hal-procmacros)
-        run: cargo fmt --all --manifest-path=esp-hal-procmacros/Cargo.toml -- --check
-      - name: rustfmt (esp-hal-smartled)
-        run: cargo fmt --all --manifest-path=esp-hal-smartled/Cargo.toml -- --check
-      - name: rustfmt (esp-riscv-rt)
-        run: cargo fmt --all --manifest-path=esp-riscv-rt/Cargo.toml -- --check
-      - name: rustfmt (esp-ulp-riscv-hal)
-        run: cargo fmt --all --manifest-path=esp-ulp-riscv-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32-hal)
-        run: cargo fmt --all --manifest-path=esp32-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32c2-hal)
-        run: cargo fmt --all --manifest-path=esp32c2-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32c3-hal)
-        run: cargo fmt --all --manifest-path=esp32c3-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32c6-hal)
-        run: cargo fmt --all --manifest-path=esp32c6-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32c6-lp-hal)
-        run: cargo fmt --all --manifest-path=esp32c6-lp-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32h2-hal)
-        run: cargo fmt --all --manifest-path=esp32h2-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32s2-hal)
-        run: cargo fmt --all --manifest-path=esp32s2-hal/Cargo.toml -- --check
-      - name: rustfmt (esp32s3-hal)
-        run: cargo fmt --all --manifest-path=esp32s3-hal/Cargo.toml -- --check
+      - run: cargo xtask fmt-packages --check
+
+  # --------------------------------------------------------------------------
+  # host tests
+
+  host-tests:
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v4
+      - uses: dtolnay/rust-toolchain@v1
+        with:
+          toolchain: stable
+      - uses: Swatinem/rust-cache@v2
+
+      # Check the formatting of all packages:
+      - run: cd esp-config && cargo test --features build

.github/workflows/ci_nightly.yml

@@ -0,0 +1,53 @@
+name: CI - nightly
+
+on:
+  workflow_dispatch:
+  schedule:
+    - cron: "0 0 * * *"
+
+env:
+  CARGO_TERM_COLOR: always
+  GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+  RUSTDOCFLAGS: -Dwarnings
+  DEFMT_LOG: trace
+
+jobs:
+
+  esp-hal-nightly:
+    name: esp-hal | nightly (${{ matrix.device.soc }})
+    runs-on: ubuntu-latest
+    env:
+      SSID: SSID
+      PASSWORD: PASSWORD
+      STATIC_IP: 1.1.1.1
+      GATEWAY_IP: 1.1.1.1
+      HOST_IP: 1.1.1.1
+
+    strategy:
+      fail-fast: false
+      matrix:
+        device: [
+            # RISC-V devices:
+            { soc: "esp32c2", target: "riscv32imc-unknown-none-elf" },
+            { soc: "esp32c3", target: "riscv32imc-unknown-none-elf" },
+            { soc: "esp32c6", target: "riscv32imac-unknown-none-elf" },
+            { soc: "esp32h2", target: "riscv32imac-unknown-none-elf" },
+          ]
+    steps:
+      - uses: actions/checkout@v4
+
+      # Install the Rust nightly toolchain for RISC-V devices:
+      - uses: dtolnay/rust-toolchain@v1
+        with:
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          toolchain: nightly
+          components: rust-src, clippy, rustfmt
+
+      - uses: Swatinem/rust-cache@v2
+
+      - name: Build and Check
+        uses: ./.github/actions/check-esp-hal
+        with:
+          device: ${{ matrix.device.soc }}
+          target: ${{ matrix.device.target }}
+          toolchain: nightly

.github/workflows/documentation.yml

@@ -0,0 +1,99 @@
+name: Documentation
+
+on:
+  workflow_dispatch:
+    inputs:
+      esp-hal:
+        description: "esp-hal tag"
+        required: true
+      esp-wifi:
+        description: "esp-wifi tag"
+        required: true
+
+env:
+  CARGO_TERM_COLOR: always
+
+jobs:
+  setup:
+    runs-on: ubuntu-latest
+    outputs:
+      packages: '[
+            { "name": "esp-hal",  "tag": "${{ github.event.inputs.esp-hal }}" },
+            { "name": "esp-wifi", "tag": "esp-wifi-${{ github.event.inputs.esp-wifi }}" }
+          ]'
+    steps:
+      - run: echo "Setup complete!"
+  build:
+    needs: setup
+    strategy:
+      fail-fast: true
+      matrix:
+        packages: ${{ fromJson(needs.setup.outputs.packages) }}
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - uses: esp-rs/xtensa-toolchain@v1.5
+        with:
+          default: true
+          ldproxy: false
+          version: 1.83.0.1
+
+      - name: Checkout repository
+        uses: actions/checkout@v4
+        with:
+          repository: esp-rs/esp-hal
+          ref: ${{ matrix.packages.tag }}
+
+      - name: Build documentation
+        run: cargo xtask build-documentation --packages=${{ matrix.packages.name }}
+
+      # https://github.com/actions/deploy-pages/issues/303#issuecomment-1951207879
+      - name: Remove problematic '.lock' files
+        run: find docs -name ".lock" -exec rm -f {} \;
+
+      - name: Upload docs for ${{ matrix.packages.name }}
+        uses: actions/upload-artifact@v4
+        with:
+          name: ${{ matrix.packages.name }}
+          path: "docs/${{ matrix.packages.name }}"
+
+  assemble:
+    needs: [setup, build]
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - name: Prepare
+        run: mkdir docs
+      - name: Download all docs
+        uses: actions/download-artifact@v4
+        with:
+          path: "docs/"
+      
+      - name: Create index.html
+        run: "cargo xtask build-documentation-index --packages=$(echo '${{ needs.setup.outputs.packages }}' | jq -r '[.[].name] | join(\",\")')"
+
+      - name: Upload Pages artifact
+        uses: actions/upload-pages-artifact@v3
+        with:
+          path: "docs/"
+
+  deploy:
+    # Add a dependency to the assemble job:
+    needs: assemble
+
+    # Grant GITHUB_TOKEN the permissions required to make a Pages deployment:
+    permissions:
+      pages: write # to deploy to Pages
+      id-token: write # to verify the deployment originates from an appropriate source
+
+    # Deploy to the github-pages environment:
+    environment:
+      name: github-pages
+      url: ${{ steps.deployment.outputs.page_url }}
+
+    # Specify runner + deployment step:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Deploy to GitHub Pages
+        id: deployment
+        uses: actions/deploy-pages@v4

.github/workflows/hil.yml

@@ -0,0 +1,186 @@
+name: HIL
+
+on:
+  pull_request:
+    types: [opened, synchronize, reopened, ready_for_review]
+  merge_group:
+  workflow_dispatch:
+    inputs:
+      repository:
+        description: "Owner and repository to test"
+        required: true
+        default: 'esp-rs/esp-hal'
+      branch:
+        description: "Branch, tag or SHA to checkout."
+        required: true
+        default: "main"
+
+# Cancel any currently running workflows from the same PR, branch, or
+# tag when a new workflow is triggered.
+#
+# https://stackoverflow.com/a/66336834
+concurrency:
+  cancel-in-progress: true
+  group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
+
+env:
+  CARGO_TERM_COLOR: always
+  GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+
+jobs:
+  build-xtasks:
+    name: Build xtasks | ${{ matrix.host.arch }}
+    runs-on: ubuntu-latest
+
+    strategy:
+      fail-fast: false
+      matrix:
+        host:
+          - arch: armv7
+            rust-target: armv7-unknown-linux-gnueabihf
+          - arch: aarch64
+            rust-target: aarch64-unknown-linux-gnu
+
+    steps:
+      - uses: actions/checkout@v4
+        if: github.event_name != 'workflow_dispatch'
+      - uses: actions/checkout@v4
+        if: github.event_name == 'workflow_dispatch'
+        with:
+          repository: ${{ github.event.inputs.repository }}
+          ref: ${{ github.event.inputs.branch }}
+
+      - name: Install Rust toolchain
+        uses: dtolnay/rust-toolchain@v1
+        with:
+          toolchain: stable
+          components: rust-src
+
+      - name: Install cross
+        run: cargo install cross
+
+      - name: Build xtasks
+        run: cross build --release --target ${{ matrix.host.rust-target }} -p xtask
+
+      - name: Upload artifact
+        uses: actions/upload-artifact@v4
+        with:
+          name: xtask-${{ matrix.host.arch }}
+          path: target/${{ matrix.host.rust-target }}/release/xtask
+
+  build-tests:
+    name: Build HIL Tests | ${{ matrix.target.soc }}
+    runs-on: ubuntu-latest
+
+    strategy:
+      fail-fast: false
+      matrix:
+        target:
+          # RISC-V devices:
+          - soc: esp32c2
+            rust-target: riscv32imc-unknown-none-elf
+          - soc: esp32c3
+            rust-target: riscv32imc-unknown-none-elf
+          - soc: esp32c6
+            rust-target: riscv32imac-unknown-none-elf
+          - soc: esp32h2
+            rust-target: riscv32imac-unknown-none-elf
+          # # Xtensa devices:
+          - soc: esp32
+            rust-target: xtensa-esp32-none-elf
+          - soc: esp32s2
+            rust-target: xtensa-esp32s2-none-elf
+          - soc: esp32s3
+            rust-target: xtensa-esp32s3-none-elf
+
+    steps:
+      - uses: actions/checkout@v4
+        if: github.event_name != 'workflow_dispatch'
+      - uses: actions/checkout@v4
+        if: github.event_name == 'workflow_dispatch'
+        with:
+          repository: ${{ github.event.inputs.repository }}
+          ref: ${{ github.event.inputs.branch }}
+
+      # Install the Rust toolchain for RISC-V devices:
+      - if: ${{ !contains(fromJson('["esp32", "esp32s2", "esp32s3"]'), matrix.target.soc) }}
+        uses: dtolnay/rust-toolchain@v1
+        with:
+          target: ${{ matrix.target.rust-target }}
+          toolchain: stable
+          components: rust-src
+      # Install the Rust toolchain for Xtensa devices:
+      - if: contains(fromJson('["esp32", "esp32s2", "esp32s3"]'), matrix.target.soc)
+        uses: esp-rs/xtensa-toolchain@v1.5
+        with:
+          buildtargets: ${{ matrix.target.soc }}
+          default: true
+          ldproxy: false
+          version: 1.83.0.1
+
+      - name: Build tests
+        run: cargo xtask build-tests ${{ matrix.target.soc }}
+
+      - uses: actions/upload-artifact@v4
+        with:
+          name: tests-${{ matrix.target.soc }}
+          path: /home/runner/work/esp-hal/esp-hal/target/tests/${{ matrix.target.soc }}
+          if-no-files-found: error
+          overwrite: true
+
+  hil:
+    name: Run HIL Tests | ${{ matrix.target.soc }}
+    needs: [build-tests, build-xtasks]
+    runs-on:
+      labels: [self-hosted, "${{ matrix.target.runner }}"]
+    strategy:
+      fail-fast: false
+      matrix:
+        target:
+          # RISC-V devices:
+          - soc: esp32c2
+            runner: esp32c2-jtag
+            host: aarch64
+          - soc: esp32c3
+            runner: esp32c3-usb
+            host: armv7
+          - soc: esp32c6
+            runner: esp32c6-usb
+            host: armv7
+          - soc: esp32h2
+            runner: esp32h2-usb
+            host: armv7
+          # Xtensa devices:
+          - soc: esp32
+            runner: esp32-jtag
+            host: aarch64
+          - soc: esp32s2
+            runner: esp32s2-jtag
+            host: armv7
+          - soc: esp32s3
+            runner: esp32s3-usb
+            host: armv7
+    steps:
+      - uses: actions/download-artifact@v4
+        with:
+          name: tests-${{ matrix.target.soc }}
+          path: tests-${{ matrix.target.soc }}
+
+      - uses: actions/download-artifact@v4
+        with:
+          name: xtask-${{ matrix.target.host }}
+
+      - name: Run Tests
+        id: run-tests
+        run: |
+          [ -f ~/setup.sh ] && source ~/setup.sh
+
+          export PATH=$PATH:/home/espressif/.cargo/bin
+          chmod +x xtask
+          ./xtask run-elfs ${{ matrix.target.soc }} tests-${{ matrix.target.soc }}
+
+      - name: Clean up
+        if: always()
+        run: |
+          rm -rf tests-${{ matrix.target.soc }}
+          rm -f xtask

.github/workflows/issue_handler.yml

@@ -13,4 +13,4 @@ jobs:
       - uses: actions/add-to-project@v0.5.0
         with:
           project-url: https://github.com/orgs/esp-rs/projects/2
-          github-token: ${{ secrets.PAT }}
+          github-token: ${{ secrets.PAT }}

.gitignore

@@ -16,3 +16,9 @@ Cargo.lock
 # Wokwi related files
 diagram.json
 wokwi.toml
+
+# We'll ignore VS Code settings (at least for now...)
+**/.vscode/settings.json
+
+# Ignore generated documentation
+docs/

.vscode/extensions.json

@@ -1,3 +0,0 @@
-{
-  "recommendations": ["rust-lang.rust-analyzer", "tamasfe.even-better-toml"]
-}

.vscode/settings.json

@@ -1,34 +0,0 @@
-{
-  "editor.formatOnSave": true,
-
-  "rust-analyzer.cargo.buildScripts.enable": true,
-  "rust-analyzer.check.allTargets": false,
-  "rust-analyzer.imports.granularity.enforce": true,
-  "rust-analyzer.imports.granularity.group": "crate",
-  "rust-analyzer.procMacro.attributes.enable": true,
-  "rust-analyzer.procMacro.enable": true,
-  "rust-analyzer.showUnlinkedFileNotification": false,
-
-  // Uncomment ONE line for the chip you want to work on.
-  // This makes rust-analyzer work on the HAL crate and all its dependencies.
-  "rust-analyzer.linkedProjects": [
-    "esp32-hal/Cargo.toml"
-    // "esp32c2-hal/Cargo.toml",
-    // "esp32c3-hal/Cargo.toml",
-    // "esp32c6-hal/Cargo.toml",
-    // "esp32c6-lp-hal/Cargo.toml",
-    // "esp32h2-hal/Cargo.toml",
-    // "esp32s2-hal/Cargo.toml",
-    // "esp32s3-hal/Cargo.toml",
-  ],
-
-  "[toml]": {
-    "editor.formatOnSave": false,
-  },
-  "[markdown]": {
-    "editor.formatOnSave": false,
-  },
-  "[jsonc]": {
-    "editor.formatOnSave": false,
-  }
-}

CHANGELOG.md

@@ -1,365 +0,0 @@
-# Changelog
-
-All notable changes to this project will be documented in this file.
-
-Please note that only changes to the `esp-hal-common` package are tracked in this CHANGELOG.
-
-The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
-and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
-
-## [0.14.1] - 2023-12-13
-
-### Fixed
-
-- Fix SHA for all targets (#1021)
-
-## [0.14.0] - 2023-12-12
-
-### Added
-
-- ESP32-C6: LP core clock is configurable (#907)
-- Derive `Clone` and `Copy` for `EspTwaiFrame` (#914)
-- A way to configure inverted pins (#912)
-- Added API to check a GPIO-pin's interrupt status bit (#929)
-- A `embedded_io_async::Read` implementation for `UsbSerialJtag` (#889)
-- `RtcClock::get_xtal_freq`, `RtcClock::get_slow_freq` (#957)
-- Added Rx Timeout functionality to async Uart (#911)
-- RISC-V: Thread-mode and interrupt-mode executors, `#[main]` macro (#947)
-- A macro to make it easier to create DMA buffers and descriptors (#935)
-- I2C timeout is configurable (#1011)
-- ESP32-C6/ESP32-H2: `flip-link` feature gives zero-cost stack overflow protection (#1008)
-
-### Changed
-
-- Improve DMA documentation & clean up module (#915)
-- Only allow a single version of `esp-hal-common` to be present in an application (#934)
-- ESP32-C3/C6 and ESP32-H2 can now use the `zero-rtc-bss` feature to enable `esp-hal-common/rv-zero-rtc-bss` (#867)
-- Reuse `ieee802154_clock_enable/disable()` functions for BLE and rename `ble_ieee802154_clock_enable()` (#953)
-- The `embedded-io` trait implementations are now gated behind the `embedded-io` feature (#964)
-- Simplifed RMT channels and channel creators (#958)
-- Reworked construction of I2S driver instances (#983)
-- ESP32-S2/S3: Don't require GPIO 18 to create a USB peripheral driver instance (#990)
-- Updated to latest release candidate (`1.0.0-rc.2`) for `embedded-hal{-async,-nb}` (#994)
-- Explicit panic when hitting the `DefaultHandler` (#1005)
-- Relevant interrupts are now auto enabled in `embassy::init` (#1014).
-
-### Fixed
-
-- ESP32-C2/C3 examples: fix build error (#899)
-- ESP32-S3: Fix GPIO interrupt handler crashing when using GPIO48. (#898)
-- Fixed short wait times in embassy causing hangs (#906)
-- Make sure to clear LP/RTC RAM before loading code (#916)
-- Async RMT channels can be used concurrently (#925)
-- Xtensa: Allow using `embassy-executor`'s thread-mode executor if neither `embassy-executor-thread`, nor `embassy-executor-interrupt` is enabled. (#937)
-- Uart Async: Improve interrupt handling and irq <--> future communication (#977)
-- RISC-V: Fix stack allocation (#988)
-- ESP32-C6: Fix used RAM (#997)
-- ESP32-H2: Fix used RAM (#1003)
-- Fix SPI slave DMA dma\_read and dma\_write (#1013)
-
-### Removed
-
-- Direct boot support has been removed (#903).
-- Removed the `mcu-boot` feature from `esp32c3-hal` (#938)
-- Removed SpiBusController and SpiBusDevice in favour of embedded-hal-bus and embassy-embedded-hal implementataions. (#978)
-
-### Breaking
-
-- `Spi::new`/`Spi::new_half_duplex` takes no gpio pin now, instead you need to call `with_pins` to setup those (#901).
-- ESP32-C2, ESP32-C3, ESP32-S2: atomic emulation trap has been removed. (#904) (#985)
-    - When upgrading you must either remove [these lines](https://github.com/esp-rs/riscv-atomic-emulation-trap#usage) from your `.cargo/config.toml`.
-    - Usage of `core::sync::atomic::*` in dependent crates should be replaced with [portable-atomic](https://github.com/taiki-e/portable-atomic).
-- RSA driver now takes `u32` words instead of `u8` bytes. The expected slice length is now 4 times shorter. (#981)
-
-## [0.13.1] - 2023-11-02
-
-### Fixed
-
-- ESP32-C3: Make sure BLE and WiFi are not powered down when esp-wifi needs them (#891)
-- ESP32-C6/H2: Fix setting UART baud rate (#893)
-
-## [0.13.0] - 2023-10-31
-
-### Added
-
-- Implement SetFrequencyCycle and PwmPin from embedded_hal for PwmPin of MCPWM. (#880)
-- Added `embassy-time-systick` to ESP32-S2 (#827)
-- Implement enabling/disabling BLE clock on ESP32-C6 (#784)
-- Async support for RMT (#787)
-- Implement `defmt::Format` for more types (#786)
-- Add new_no_miso to Spi FullDuplexMode (#794)
-- Add UART support for splitting into TX and RX (#754)
-- Async support for I2S (#801)
-- Async support for PARL_IO (#807)
-- ETM driver, GPIO ETM (#819)
-- (G)DMA AES support (#821)
-- SYSTIMER ETM functionality (#828)
-- Adding async support for RSA peripheral(doesn't work properly for `esp32` chip - issue will be created)(#790)
-- Added sleep support for ESP32-C3 with timer and GPIO wakeups (#795)
-- Support for ULP-RISCV including Delay and GPIO (#840, #845)
-- Add bare-bones SPI slave support, DMA only (#580, #843)
-- Embassy `#[main]` convenience macro (#841)
-- Add a `defmt` feature to the `esp-hal-smartled` package (#846)
-- Support 16MB octal PS-RAM for ESP32-S3 (#858)
-- RISCV TRACE Encoder driver for ESP32-C6 / ESP32-H2 (#864)
-- `embedded_hal` 1 `InputPin` and `embedded_hal_async` `Wait` impls for open drain outputs (#905)
-
-### Changed
-
-- Bumped MSRV to 1.67 (#798)
-- Optimised multi-core critical section implementation (#797)
-- Changed linear- and curve-calibrated ADC to provide readings in mV (#836)
-
-### Fixed
-
-- S3: Allow powering down RC_FAST_CLK (#796)
-- UART/ESP32: fix calculating FIFO counter with `get_rx_fifo_count()` (#804)
-- Xtensa targets: Use ESP32Reset - not Reset (#823)
-- Examples should now work with the `defmt` feature (#810)
-- Fixed a race condition causing SpiDma to stop working unexpectedly (#869)
-- Fixed async uart serial, and updated the embassy_serial examples (#871).
-- Fix ESP32-S3 direct-boot (#873)
-- Fix ESP32-C6 ADC (#876)
-- Fix ADC Calibration not being used on ESP32-S2 and ESP32-S3 (#1000)
-
-### Removed
-
-- `Pin::is_pcore_interrupt_set` (#793)
-- `Pin::is_pcore_non_maskable_interrupt_set` (#793)
-- `Pin::is_acore_interrupt_set` (#793)
-- `Pin::is_acore_non_maskable_interrupt_set` (#793)
-- `Pin::enable_hold` (#793)
-- Removed the generic return type for ADC reads (#792)
-
-### Breaking
-
-- `Uart::new` now takes the `&Clocks` struct to ensure baudrate is correct for CPU/APB speed. (#808)
-- `Uart::new_with_config` takes an `Config` instead of `Option<Config>`. (#808)
-- `Alarm::set_period` takes a period (duration) instead of a frequency (#812)
-- `Alarm::interrupt_clear` is now `Alarm::clear_interrupt` to be consistent (#812)
-- The `PeripheralClockControl` struct is no longer public, drivers no longer take this as a parameter (#817)
-- Unify the system peripheral, `SYSTEM`, `DPORT` and `PCR` are now all exposed as `SYSTEM` (#832).
-- Unified the ESP32's and ESP32-C2's xtal frequency features (#831)
-- Replace any underscores in feature names with dashes (#833)
-- The `spi` and `spi_slave` modules have been refactored into the `spi`, `spi::master`, and `spi::slave` modules (#843)
-- The `WithDmaSpi2`/`WithDmaSpi3` structs are no longer generic around the inner peripheral type (#853)
-- The `SarAdcExt`/`SensExt` traits are now collectively named `AnalogExt` instead (#857)
-- Replace the `radio` module with peripheral singleton structs (#852)
-- The SPI traits are no longer re-exported in the main prelude, but from preludes in `spi::master`/`spi::slave` instead (#860)
-- The `embedded-hal-1` and `embedded-hal-async` traits are no longer re-exported in the prelude (#860)
-
-## [0.12.0] - 2023-09-05
-
-### Added
-
-- Implement RTCIO pullup, pulldown and hold control for Xtensa MCUs (#684)
-- S3: Implement RTCIO wakeup source (#690)
-- Add PARL_IO driver for ESP32-C6 / ESP32-H2 (#733, #760)
-- Implement `ufmt_write::uWrite` trait for USB Serial JTAG (#751)
-- Add HMAC peripheral support (#755)
-- Add multicore-aware embassy executor for Xtensa MCUs (#723, #756).
-- Add interrupt-executor for Xtensa MCUs (#723, #756).
-- Add missing `Into<Gpio<Analog, GPIONUN>>` conversion (#764)
-- Updated `clock` module documentation (#774)
-- Add `log` feature to enable log output (#773)
-- Add `defmt` feature to enable log output (#773)
-- A new macro to load LP core code on ESP32-C6 (#779)
-- Add `ECC`` peripheral driver (#785)
-- Initial LLD support for Xtensa chips (#861).
-
-### Changed
-
-- Update the `embedded-hal-*` packages to `1.0.0-rc.1` and implement traits from `embedded-io` and `embedded-io-async` (#747)
-- Moved AlignmentHelper to its own module (#753)
-- Disable all watchdog timers by default at startup (#763)
-- `log` crate is now opt-in (#773)
-
-### Fixed
-
-- Fix `psram` availability lookup in `esp-hal-common` build script (#718)
-- Fix wrong `dram_seg` length in `esp32s2-hal` linker script (#732)
-- Fix setting alarm when a timer group is used as the alarm source. (#730)
-- Fix `Instant::now()` not counting in some cases when using TIMG0 as the timebase (#737)
-- Fix number of ADC attenuations for ESP32-C6 (#771)
-- Fix SHA registers access (#805)
-
-### Breaking
-
-- `CpuControl::start_app_core()` now takes an `FnOnce` closure (#739)
-
-## [0.11.0] - 2023-08-10
-
-### Added
-
-- Add initial LP-IO support for ESP32-C6 (#639)
-- Implement sleep with some wakeup methods for `esp32` (#574)
-- Add a new RMT driver (#653, #667, #695)
-- Implemented calibrated ADC API for ESP32-S3 (#641)
-- Add MCPWM DeadTime configuration (#406)
-- Implement sleep with some wakeup methods for `esp32-s3` (#660, #689, #696)
-- Add feature enabling directly hooking the interrupt vector table (#621)
-- Add `ClockControl::max` helper for all chips (#701)
-- Added module-level documentation for all peripherals (#680)
-- Implement sleep with some wakeup methods for `esp32-s3` (#660)
-- Add `FlashSafeDma` wrapper for eh traits which ensure correct DMA transfer from source data in flash (ROM) (#678)
-
-### Changed
-
-- Update `embedded-hal-*` alpha packages to their latest versions (#640)
-- Implement the `Clone` and `Copy` traits for the `Rng` driver (#650)
-- Use all remaining memory as core-0's stack (#716)
-
-### Fixed
-
-- Fixed Async Uart `read` when `set_at_cmd` is not used (#652)
-- USB device support is working again (#656)
-- Add missing interrupt status read for esp32s3, which fixes USB-SERIAL-JTAG interrupts (#664)
-- GPIO interrupt status bits are now properly cleared (#670)
-- Increase frequency resolution in `set_periodic` (#686)
-- Fixed ESP32-S2, ESP32-S3, ESP32-C2, ESP32-C3 radio clock gating (#679, #681)
-- Partially fix ESP32 radio clocks (#709)
-- Fixed "ESP32/ESP32-S2 RMT transmission with with data.len() > RMT_CHANNEL_RAM_SIZE results in TransmissionError" #707 (#710)
-
-### Removed
-
-- Remove the `allow-opt-level-z` feature from `esp32c3-hal` (#654)
-- Remove the old `pulse_control` driver (#694)
-
-### Breaking
-
-- `DmaTransfer::wait` and `I2sReadDmaTransfer::wait_receive` now return `Result` (#665)
-- `gpio::Pin` is now object-safe (#687)
-
-## [0.10.0] - 2023-06-04
-
-### Added
-
-- Add `WithDmaSpi3` to prelude for ESP32S3 (#623)
-- Add bare-bones PSRAM support for ESP32 (#506)
-- Add initial support for the ESP32-H2 (#513, #526, #527, #528, #530, #538, #544, #548, #551, #556, #560, #566, #549, #564, #569, #576, #577, #589, #591, #597)
-- Add bare-bones PSRAM support for ESP32-S3 (#517)
-- Add async support to the I2C driver (#519)
-- Implement Copy and Eq for EspTwaiError (#540)
-- Add LEDC hardware fade support (#475)
-- Added support for multicore async GPIO (#542)
-- Add a fn to poll DMA transfers (#559)
-- Add unified field-based efuse access (#567)
-- Move `esp-riscv-rt` into esp-hal (#578)
-- Add CRC functions from ESP ROM (#587)
-- Add a `debug` feature to enable the PACs' `impl-register-debug` feature (#596)
-- Add initial support for `I2S` in ESP32-H2 (#597)
-- Add octal PSRAM support for ESP32-S3 (#610)
-- Add MD5 functions from ESP ROM (#618)
-- Add embassy async `read` support for `uart` (#620)
-- Add bare-bones support to run code on ULP-RISCV / LP core (#631)
-- Add ADC calibration implementation for a riscv chips (#555)
-- Add `async` implementation for `USB Serial/JTAG`(#632)
-
-### Changed
-
-- Simplify the `Delay` driver, derive `Clone` and `Copy` (#568)
-- DMA types can no longer be constructed by the user (#625)
-- Move core interrupt handling from Flash to RAM for RISC-V chips (ESP32-H2, ESP32-C2, ESP32-C3, ESP32-C6) (#541)
-- Change LED pin to GPIO2 in ESP32 blinky example (#581)
-- Update ESP32-H2 and ESP32-C6 clocks and remove `i2c_clock` for all chips but ESP32 (#592)
-- Use both timers in `TIMG0` for embassy time driver when able (#609)
-- Re-work `RadioExt` implementations, add support for ESP32-H2 (#627)
-- Improve examples documentation (#533)
-- esp32h2-hal: added README (#585)
-- Update `esp-hal-procmacros` package dependencies and features (#628)
-
-### Fixed
-
-- Corrected the expected DMA descriptor counts (#622, #625)
-- DMA is supported for SPI3 on ESP32-S3 (#507)
-- `change_bus_frequency` is now available on `SpiDma` (#529)
-- Fixed a bug where a GPIO interrupt could erroneously fire again causing the next `await` on that pin to instantly return `Poll::Ok` (#537)
-- Set `vecbase` on core 1 (ESP32, ESP32-S3) (#536)
-- ESP32-S3: Move PSRAM related function to RAM (#546)
-- ADC driver will now apply attenuation values to the correct ADC's channels. (#554)
-- Sometimes half-duplex non-DMA SPI reads were reading garbage in non-release mode (#552)
-- ESP32-C3: Fix GPIO5 ADC channel id (#562)
-- ESP32-H2: Fix direct-boot feature (#570)
-- Fix Async GPIO not disabling interupts on chips with multiple banks (#572)
-- ESP32-C6: Support FOSC CLK calibration for ECO1+ chip revisions (#593)
-- Fixed CI by pinning the log crate to 0.4.18 (#600)
-- ESP32-S3: Fix calculation of PSRAM start address (#601)
-- Fixed wrong variable access (FOSC CLK calibration for ESP32-C6 #593)
-- Fixed [trap location in ram](https://github.com/esp-rs/esp-hal/pull/605#issuecomment-1604039683) (#605)
-- Fix rom::crc docs (#611)
-- Fixed a possible overlap of `.data` and `.rwtext` (#616)
-- Avoid SDA/SCL being low while configuring pins for I2C (#619)
-
-### Breaking
-
-- Simplified user-facing SpiDma and I2s types (#626)
-- Significantly simplified user-facing GPIO pin types. (#553)
-- No longer re-export the `soc` module and the contents of the `interrupt` module at the package level (#607)
-
-## [0.9.0] - 2023-05-02
-
-### Added
-
-- Add bare-bones PSRAM support for ESP32-S2 (#493)
-- Add `DEBUG_ASSIST` functionality (#484)
-- Add RSA peripheral support (#467)
-- Add PeripheralClockControl argument to `timg`, `wdt`, `sha`, `usb-serial-jtag` and `uart` constructors (#463)
-- Added API to raise and reset software interrupts (#426)
-- Implement `embedded_hal_nb::serial::*` traits for `UsbSerialJtag` (#498)
-
-### Fixed
-
-- Fix `get_wakeup_cause` comparison error (#472)
-- Use 192 as mclk_multiple for 24-bit I2S (#471)
-- Fix `CpuControl::start_app_core` signature (#466)
-- Move `rwtext` after other RAM data sections (#464)
-- ESP32-C3: Disable `usb_pad_enable` when setting GPIO18/19 to input/output (#461)
-- Fix 802.15.4 clock enabling (ESP32-C6) (#458)
-- ESP32-S3: Disable usb_pad_enable when setting GPIO19/20 to input/output (#645)
-
-### Changed
-
-- Update `embedded-hal-async` and `embassy-*` dependencies (#488)
-- Update to `embedded-hal@1.0.0-alpha.10` and `embedded-hal-nb@1.0.0-alpha.2` (#487)
-- Let users configure the LEDC output pin as open-drain (#474)
-- Use bitflags to decode wakeup cause (#473)
-- Minor linker script additions (#470)
-- Minor documentation improvements (#460)
-
-### Removed
-
-- Remove unnecessary generic from `UsbSerialJtag` driver (#492)
-- Remove `#[doc(inline)]` from esp-hal-common re-exports (#490)
-
-## [0.8.0] - 2023-03-27
-
-## [0.7.1] - 2023-02-22
-
-## [0.7.0] - 2023-02-21
-
-## [0.5.0] - 2023-01-26
-
-## [0.4.0] - 2022-12-12
-
-## [0.3.0] - 2022-11-17
-
-## [0.2.0] - 2022-09-13
-
-## [0.1.0] - 2022-08-05
-
-[0.14.1]: https://github.com/esp-rs/esp-hal/compare/v0.14.0...v0.14.1
-[0.14.0]: https://github.com/esp-rs/esp-hal/compare/v0.13.1...v0.14.0
-[0.13.1]: https://github.com/esp-rs/esp-hal/compare/v0.13.0...v0.13.1
-[0.13.0]: https://github.com/esp-rs/esp-hal/compare/v0.12.0...v0.13.0
-[0.12.0]: https://github.com/esp-rs/esp-hal/compare/v0.11.0...v0.12.0
-[0.11.0]: https://github.com/esp-rs/esp-hal/compare/v0.10.0...v0.11.0
-[0.10.0]: https://github.com/esp-rs/esp-hal/compare/v0.9.0...v0.10.0
-[0.9.0]: https://github.com/esp-rs/esp-hal/compare/v0.8.0...v0.9.0
-[0.8.0]: https://github.com/esp-rs/esp-hal/compare/v0.7.1...v0.8.0
-[0.7.1]: https://github.com/esp-rs/esp-hal/compare/v0.7.0...v0.7.1
-[0.7.0]: https://github.com/esp-rs/esp-hal/compare/v0.5.0...v0.7.0
-[0.5.0]: https://github.com/esp-rs/esp-hal/compare/v0.4.0...v0.5.0
-[0.4.0]: https://github.com/esp-rs/esp-hal/compare/v0.3.0...v0.4.0
-[0.3.0]: https://github.com/esp-rs/esp-hal/compare/v0.2.0...v0.3.0
-[0.2.0]: https://github.com/esp-rs/esp-hal/compare/v0.1.0...v0.2.0
-[0.1.0]: https://github.com/esp-rs/esp-hal/releases/tag/v0.1.0

CONTRIBUTING.md

@@ -1,101 +0,0 @@
-# Welcome to the `esp-hal` contributing guide
-
-Thank you for investing your time in contributing to our project!
-
-In this guide you will get an overview of the contribution workflow from opening an issue, creating a PR, reviewing, and merging the PR.
-
-Use the table of contents icon (<img src="resources/table-of-contents.png" width="24" height="24" />) in the top right corner of this document to get to a specific section of this guide quickly.
-
-## New Contributor Guide
-
-To get an overview of the project, please read the [README]. Here are some resources to help you get started with open source contributions:
-
-- [Finding ways to contribute to open source on GitHub]
-- [Set up Git]
-- [GitHub flow]
-- [Collaborating with pull requests]
-
-[README]: README.md
-[Finding ways to contribute to open source on GitHub]: https://docs.github.com/en/get-started/exploring-projects-on-github/finding-ways-to-contribute-to-open-source-on-github
-[Set up Git]: https://docs.github.com/en/get-started/quickstart/set-up-git
-[GitHub flow]: https://docs.github.com/en/get-started/quickstart/github-flow
-[Collaborating with pull requests]: https://docs.github.com/en/github/collaborating-with-pull-requests
-
-## Getting Started
-
-### Issues
-
-#### Create a New Issue
-
-If you spot a problem with the docs, [search if an issue already exists]. If a related issue doesn't exist, you can open a new issue using the [issue form].
-
-[search if an issue already exists]: https://docs.github.com/en/github/searching-for-information-on-github/searching-on-github/searching-issues-and-pull-requests#search-by-the-title-body-or-comments
-[issue form]: https://github.com/esp-rs/esp-hal/issues/new/
-
-#### Solve an Issue
-
-Scan through our [existing issues] to find one that interests you. You can narrow down the search using labels as filters. If you find an issue to work on, you are welcome to open a PR with a fix.
-
-It's recommended that you comment in the relevant issue, mentioning that you are actively working on it, however this is not a requirement.
-
-If somebody is already assigned to an issue, this does not necessarily mean they are actively working on it; don't be afraid to comment in these issues asking if you can take over the work if you're interested.
-
-[existing issues]: https://github.com/esp-rs/esp-hal/issues
-
-### Make Changes
-
-1. Fork the repository.
-   - Using GitHub Desktop:
-     - [Getting started with GitHub Desktop] will guide you through setting up Desktop.
-     - Once Desktop is set up, you can use it to [fork the repo!]
-   - Using the command line:
-     - [Fork the repo] so that you can make your changes without affecting the original project until you're ready to merge them.
-2. Install or update to the latest version of Rust. See [rustup.rs] for more information.
-3. Create a working branch and start with your changes!
-
-[Getting started with GitHub Desktop]: https://docs.github.com/en/desktop/installing-and-configuring-github-desktop/getting-started-with-github-desktop
-[fork the repo!]: https://docs.github.com/en/desktop/contributing-and-collaborating-using-github-desktop/cloning-and-forking-repositories-from-github-desktop
-[Fork the repo]: https://docs.github.com/en/github/getting-started-with-github/fork-a-repo#fork-an-example-repository
-[rustup.rs]: https://rustup.rs/
-
-### Commit Your Update
-
-Commit the changes once you are happy with them. Don't forget to self-review to speed up the review process.
-
-We ask that you ensure all source code files has been properly formatted with `rustfmt`, and that you have linted your changes by running `cargo clippy`. These tools can be installed by running the following commands:
-
-```shell
-rustup component add rustfmt
-rustup component add clippy
-```
-
-We _strongly_ recommend that you use the supplied `pre-commit` Git hook, which will ensure that all source code has been formatted correctly prior to committing. See the [Git documentation] for more information on hooks.
-
-The `pre-commit` hook can be installed by running the following command in a terminal, from the root of the repository:
-
-```shell
-cp pre-commit .git/hooks/pre-commit
-```
-
-[Git documentation]: https://git-scm.com/book/en/v2/Customizing-Git-Git-Hooks
-
-### Pull Request
-
-When you're finished with the changes, create a pull request, also known as a PR.
-
-- Fill the pull request template so that we can review your PR. This template helps reviewers understand your changes as well as the purpose of your pull request.
-- Don't forget to [link PR to issue] if you are solving one.
-- Enable the checkbox to [allow maintainer edits] so the branch can be updated for a merge. Once you submit your PR, a Docs team member will review your proposal. We may ask questions or request additional information.
-- We may ask for changes to be made before a PR can be merged, either using [suggested changes] or pull request comments. You can apply suggested changes directly through the UI. You can make any other changes in your fork, then commit them to your branch.
-- As you update your PR and apply changes, mark each conversation as [resolved].
-- If you run into any merge issues, checkout this [git tutorial] to help you resolve merge conflicts and other issues.
-
-[link PR to issue]: https://docs.github.com/en/issues/tracking-your-work-with-issues/linking-a-pull-request-to-an-issue
-[allow maintainer edits]: https://docs.github.com/en/github/collaborating-with-issues-and-pull-requests/allowing-changes-to-a-pull-request-branch-created-from-a-fork
-[suggested changes]: https://docs.github.com/en/github/collaborating-with-issues-and-pull-requests/incorporating-feedback-in-your-pull-request
-[resolved]: https://docs.github.com/en/github/collaborating-with-issues-and-pull-requests/commenting-on-a-pull-request#resolving-conversations
-[git tutorial]: https://github.com/skills/resolve-merge-conflicts
-
-### Your PR is Merged!
-
-Congratulations! The esp-rs team thanks you for your contributions!

Cargo.toml

@@ -0,0 +1,28 @@
+[workspace]
+resolver = "2"
+members  = ["xtask"]
+exclude  = [
+    "esp-alloc",
+    "esp-backtrace",
+    "esp-build",
+    "esp-config",
+    "esp-hal",
+    "esp-hal-embassy",
+    "esp-hal-procmacros",
+    "esp-ieee802154",
+    "esp-lp-hal",
+    "esp-metadata",
+    "esp-println",
+    "esp-riscv-rt",
+    "esp-wifi",
+    "esp-storage",
+    "examples",
+    "extras/bench-server",
+    "extras/esp-wifishark",
+    "extras/ieee802154-sniffer",
+    "hil-test",
+    "qa-test",
+    "xtensa-lx",
+    "xtensa-lx-rt",
+    "xtensa-lx-rt/procmacros",
+]

README.md

@@ -1,20 +1,29 @@
 # esp-hal
 
-![GitHub Workflow Status](https://img.shields.io/github/actions/workflow/status/esp-rs/esp-hal/ci.yml?label=CI&logo=github&style=flat-square)
-![MIT/Apache-2.0 licensed](https://img.shields.io/badge/license-MIT%2FApache--2.0-blue?style=flat-square)
-[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
+![GitHub Actions Workflow Status](https://img.shields.io/github/actions/workflow/status/esp-rs/esp-hal/ci.yml?labelColor=1C2C2E&label=CI&logo=github&style=flat-square)
+![GitHub Actions Workflow Status](https://img.shields.io/github/actions/workflow/status/esp-rs/esp-hal/hil.yml?labelColor=1C2C2E&label=HIL&logo=github&style=flat-square&event=merge_group)
+![MIT/Apache-2.0 licensed](https://img.shields.io/badge/license-MIT%2FApache--2.0-blue?labelColor=1C2C2E&style=flat-square)
+[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?labelColor=1C2C2E&label=join%20matrix&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
 
-**H**ardware **A**bstraction **L**ayer crates for the **ESP32**, **ESP32-C2/C3/C6**, **ESP32-H2**, and **ESP32-S2/S3** from Espressif. Additionally provides support for programming the low-power RISC-V cores found on the **ESP32-C6** and **ESP32-S2/S3**.
+Bare-metal (`no_std`) hardware abstraction layer for Espressif devices. Currently supports, to varying degrees, the following devices:
 
-These HALs are `no_std`; if you are looking for `std` support, please use [esp-idf-hal] instead.
+- ESP32 Series: _ESP32_
+- ESP32-C Series: _ESP32-C2, ESP32-C3, ESP32-C6_
+- ESP32-H Series: _ESP32-H2_
+- ESP32-S Series: _ESP32-S2, ESP32-S3_
+
+Additionally provides limited support for programming the low-power RISC-V cores found on the _ESP32-C6_, _ESP32-S2_, and _ESP32-S3_ via the [esp-lp-hal] package.
+
+These packages are all `no_std`; if you are looking for `std` support, please use [esp-idf-svc] instead.
 
 If you have any questions, comments, or concerns, please [open an issue], [start a new discussion], or join us on [Matrix]. For additional information regarding any of the crates in this repository, please refer to the relevant crate's README.
 
 > [!NOTE]
 >
-> This project is still in the relatively early stages of development, and as such there should be no expectation of API stability. A significant number of peripherals currently have drivers implemented but have varying levels of functionality. For most basic tasks, this should be usable already, however some more advanced or uncommon features may not yet be implemented.
+> This repository includes crates that are at various stages of maturity and stability. While many functionalities have already been implemented and are usable for most tasks, certain advanced or less common features may still be under development. Each crate may offer different levels of functionality and guarantees.
 
-[esp-idf-hal]: https://github.com/esp-rs/esp-idf-hal
+[esp-lp-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp-lp-hal
+[esp-idf-svc]: https://github.com/esp-rs/esp-idf-svc
 [open an issue]: https://github.com/esp-rs/esp-hal/issues/new
 [start a new discussion]: https://github.com/esp-rs/esp-hal/discussions/new
 [matrix]: https://matrix.to/#/#esp-rs:matrix.org
@@ -23,10 +32,10 @@ If you have any questions, comments, or concerns, please [open an issue], [start
 
 For information relating to the development of Rust applications on ESP devices, please first read [The Rust on ESP Book].
 
-For information about the HAL and how to use it in your own projects, please refer to the documentation on [docs.rs] for the relevant chip.
+For information about the HAL and how to use it in your own projects, please refer to the [documentation].
 
 [The Rust on ESP Book]: https://esp-rs.github.io/book/
-[docs.rs]: https://docs.rs
+[documentation]: https://docs.esp-rs.org/esp-hal/
 
 ## Resources
 
@@ -36,98 +45,16 @@ For information about the HAL and how to use it in your own projects, please ref
 - [The Rust on ESP Book](https://esp-rs.github.io/book/)
 - [Embedded Rust (no_std) on Espressif](https://esp-rs.github.io/no_std-training/)
 
-## HAL Crates
+## Crates
 
-### High-Power Cores
+This repository is home to a number of different packages; for more information regarding a particular package, please refer to its `README.md` and/or documentation.
 
-|     Crate     |                   Documentation                    | Technical Reference Manual |             Target             |
-| :-----------: | :------------------------------------------------: | :------------------------: | :----------------------------: |
-|  [esp32-hal]  |   [![esp32-hal-docs]](https://docs.rs/esp32-hal)   |          [ESP32]           |    `xtensa-esp32-none-elf`     |
-| [esp32c2-hal] | [![esp32c2-hal-docs]](https://docs.rs/esp32c2-hal) |         [ESP32-C2]         | `riscv32imc-unknown-none-elf`  |
-| [esp32c3-hal] | [![esp32c3-hal-docs]](https://docs.rs/esp32c3-hal) |         [ESP32-C3]         | `riscv32imc-unknown-none-elf`  |
-| [esp32c6-hal] | [![esp32c6-hal-docs]](https://docs.rs/esp32c6-hal) |         [ESP32-C6]         | `riscv32imac-unknown-none-elf` |
-| [esp32h2-hal] | [![esp32h2-hal-docs]](https://docs.rs/esp32h2-hal) |         [ESP32-H2]         | `riscv32imac-unknown-none-elf` |
-| [esp32s2-hal] | [![esp32s2-hal-docs]](https://docs.rs/esp32s2-hal) |         [ESP32-S2]         |   `xtensa-esp32s2-none-elf`    |
-| [esp32s3-hal] | [![esp32s3-hal-docs]](https://docs.rs/esp32s3-hal) |         [ESP32-S3]         |   `xtensa-esp32s3-none-elf`    |
+## Contributing
 
-[esp32-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32-hal
-[esp32c2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c2-hal
-[esp32c3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c3-hal
-[esp32c6-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c6-hal
-[esp32h2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32h2-hal
-[esp32s2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s2-hal
-[esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal
-[esp32-hal-docs]: https://img.shields.io/docsrs/esp32-hal?color=C96329&logo=rust&style=flat-square
-[esp32c2-hal-docs]: https://img.shields.io/docsrs/esp32c2-hal?color=C96329&logo=rust&style=flat-square
-[esp32c3-hal-docs]: https://img.shields.io/docsrs/esp32c3-hal?color=C96329&logo=rust&style=flat-square
-[esp32c6-hal-docs]: https://img.shields.io/docsrs/esp32c6-hal?color=C96329&logo=rust&style=flat-square
-[esp32h2-hal-docs]: https://img.shields.io/docsrs/esp32h2-hal?color=C96329&logo=rust&style=flat-square
-[esp32s2-hal-docs]: https://img.shields.io/docsrs/esp32s2-hal?color=C96329&logo=rust&style=flat-square
-[esp32s3-hal-docs]: https://img.shields.io/docsrs/esp32s3-hal?color=C96329&logo=rust&style=flat-square
-[esp32]: https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf
-[esp32-c2]: https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf
-[esp32-c3]: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
-[esp32-c6]: https://www.espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf
-[esp32-h2]: https://www.espressif.com/sites/default/files/documentation/esp32-h2_technical_reference_manual_en.pdf
-[esp32-s2]: https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf
-[esp32-s3]: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
+We have a number of living documents to aid contributing to the project, please give these a read before modifying code:
 
-### Low-Power Cores
-
-|        Crate        |       Documentation        |             Target             |
-| :-----------------: | :------------------------: | :----------------------------: |
-| [esp-ulp-riscv-hal] | N/A (_Not yet published_) | `riscv32imc-unknown-none-elf`  |
-|  [esp32c6-lp-hal]   | N/A (_Not yet published_) | `riscv32imac-unknown-none-elf` |
-
-[esp-ulp-riscv-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp-ulp-riscv-hal
-[esp32c6-lp-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c6-lp-hal
-
-## Ancillary Crates
-
-There are a number of other crates within the [esp-rs organization] which can be used in conjunction with `esp-hal`:
-
-|      Crate       |                                  Description                                   |
-| :--------------: | :----------------------------------------------------------------------------: |
-|   [esp-alloc]    |                        A simple `no_std` heap allocator                        |
-| [esp-backtrace]  |                 Backtrace support for bare-metal applications                  |
-| [esp-ieee802154] |          Low-level IEEE802.15.4 driver for the ESP32-C6 and ESP32-H2           |
-| [esp-openthread] |           A bare-metal Thread implementation using `esp-ieee802154`            |
-|  [esp-println]   |                Provides `print!` and `println!` implementations                |
-|  [esp-storage]   | Implementation of [embedded-storage] traits to access unencrypted flash memory |
-|    [esp-wifi]    |                       `no_std` Wi-Fi/BLE/ESP-NOW support                       |
-
-[esp-rs organization]: https://github.com/esp-rs
-[esp-alloc]: https://github.com/esp-rs/esp-alloc
-[esp-backtrace]: https://github.com/esp-rs/esp-backtrace
-[esp-ieee802154]: https://github.com/esp-rs/esp-ieee802154
-[esp-openthread]: https://github.com/esp-rs/esp-openthread
-[esp-println]: https://github.com/esp-rs/esp-println
-[esp-storage]: https://github.com/esp-rs/esp-storage
-[embedded-storage]: https://github.com/rust-embedded-community/embedded-storage
-[esp-wifi]: https://github.com/esp-rs/esp-wifi
-
-## Git Hooks
-
-We provide a simple `pre-commit` hook to verify the formatting of each package prior to committing changes. We _strongly_ encourage use of this git hook.
-
-The hook can be enabled by copying it in to the `.git/hooks/` directory:
-
-```bash
-cp pre-commit .git/hooks/pre-commit
-```
-
-When using this hook, you can choose to ignore its failure on a per-commit basis by committing with the `--no-verify` flag; however, you will need to be sure that all packages are formatted when submitting a pull request.
-
-## MSRV
-
-The **M**inimum **S**upported **R**ust **V**ersion is `1.67.0` for all packages.
-
-RISC-V is officially supported by the official Rust compiler, however, it should be noted that targeting the Xtensa ISA currently requires the use of the [esp-rs/rust] compiler fork. Our recommend method of installation is [espup].
-
-When targetting the RISC-V architecture _and_ using a `stable` Rust release, it is necessary to set `RUSTC_BOOTSTRAP=1` in order to build successfully; this is not required when using a `nightly` release or when targeting Xtensa.
-
-[esp-rs/rust]: https://github.com/esp-rs/rust
-[espup]: https://github.com/esp-rs/espup
+- [API-GUIDELINES](https://github.com/esp-rs/esp-hal/blob/main/documentation/API-GUIDELINES.md)
+- [CONTRIBUTING-GUIDE](https://github.com/esp-rs/esp-hal/blob/main/documentation/CONTRIBUTING.md)
 
 ## License
 
@@ -138,7 +65,7 @@ Licensed under either of:
 
 at your option.
 
-### Contribution
+### Contribution notice
 
 Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
 the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without

documentation/API-GUIDELINES.md

@@ -0,0 +1,144 @@
+# `esp-rs` API Guidelines
+
+## About
+
+This is a living document - make sure to check the latest version of this document.
+
+> [!NOTE]
+> Not all of the currently existing code follows this guideline, yet.
+
+In general, the [Rust API Guidelines](https://rust-lang.github.io/api-guidelines) apply to all projects in the ESP-RS GitHub organization where possible.
+  - Especially for public API but if possible also for internal APIs.
+
+## Amendments to the Rust API Guidelines
+
+- `C-RW-VALUE` and `C-SERDE` do not apply.
+- `C-COMMON-TRAITS`:
+  The set of traits to implement depend on the type and use case. In esp-hal, we can highlight a few such use cases and provide recommendations what should be implemented. If nothing here applies, use your best judgement.
+  - Driver structures: `Debug`
+  - Driver configuration: `Default`, `Debug`, `PartialEq/Eq`, `Clone/Copy`, `Hash`
+    - `Clone/Copy` depends on the size and contents of the structure. They should generally be implemented, unless there is a good reason not to.
+    - The `Default` configuration needs to make sense for a particular driver, and applying the default configuration must not fail.
+  - Error types: `Debug`, `PartialEq/Eq`, `Clone/Copy`, `Hash`, `Error`, `Display`
+
+## Construction and Destruction of Drivers
+
+- Drivers must take peripherals via the `PeripheralRef` pattern - they don't consume peripherals directly.
+- If a driver requires pins, those pins should be configured using `fn with_signal_name(self, pin: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self` or `fn with_signal_name(self, pin: impl Peripheral<P = impl PeripheralOutput> + 'd) -> Self`
+- If a driver supports multiple peripheral instances (for example, I2C0 is one such instance):
+  - The driver should not be generic over the peripheral instance.
+  - The author must to use `crate::any_peripheral` to define the "any" peripheral instance type.
+  - The driver must implement a `new` constructor that automatically converts the peripheral instance into the any type.
+- If a driver is configurable, configuration options should be implemented as a `Config` struct in the same module where the driver is located.
+  - The driver's constructor should take the config struct by value, and it should return `Result<Self, ConfigError>`.
+  - The `ConfigError` enum should be separate from other `Error` enums used by the driver.
+  - The driver should implement `fn apply_config(&mut self, config: &Config) -> Result<(), ConfigError>`.
+  - In case the driver's configuration is infallible (all possible combinations of options are supported by the hardware), the `ConfigError` should be implemented as an empty `enum`.
+  - Configuration structs should derive `procmacros::BuilderLite` in order to automatically implement the Builder Lite pattern for them.
+- If a driver implements both blocking and async operations, or only implements blocking operations, but may support asynchronous ones in the future, the driver's type signature must include a `crate::Mode` type parameter.
+- By default, constructors must configure the driver for blocking mode. The driver must implement `into_async` (and a matching `into_blocking`) function that reconfigures the driver.
+  - `into_async` must configure the driver and/or the associated DMA channels. This most often means enabling an interrupt handler.
+  - `into_blocking` must undo the configuration done by `into_async`.
+- The asynchronous driver implementation must also expose the blocking methods (except for interrupt related functions).
+- Drivers must have a `Drop` implementation resetting the peripheral to idle state. There are some exceptions to this:
+  - GPIO where common usage is to "set and drop" so they can't be changed
+  - Where we don't want to disable the peripheral as it's used internally, for example SYSTIMER is used by `time::now()` API. See `KEEP_ENABLED` in src/system.rs
+  - A driver doesn't need to do anything special for deinitialization and has a `PeripheralGuard` field which implements the disabling and resetting of the peripheral.
+- Consider using a builder-like pattern for driver construction.
+
+## Interoperability
+
+- Don't use `log::XXX!` macros directly - use the wrappers in `fmt.rs` (e.g. just `info!` instead of `log::info!` or importing `log::*`)!
+- Consider implementing common ecosystem traits, like the ones in `embedded-hal` or `embassy-embedded-hal`.
+  - Where the guidelines suggest implementing `Debug`, `defmt::Format` should also be implemented.
+    - The `defmt::Format` implementation needs to be gated behind the `defmt` feature.
+    - see [this example](https://github.com/esp-rs/esp-hal/blob/df2b7bd8472cc1d18db0d9441156575570f59bb3/esp-hal/src/spi/mod.rs#L15)
+    - e.g. `#[cfg_attr(feature = "defmt", derive(defmt::Format))]`
+  - Implementations of common, but unstable traits (e.g. `embassy_embedded_hal::SetConfig`) need to be gated with the `unstable` feature.
+
+## API Surface
+
+- API documentation must be provided for every new driver and API.
+- Private details should not leak into the public API, and should be made private where technically possible.
+  - Implementation details that _need_ to be public should be marked with `#[doc(hidden)]` and a comment as to why it needs to be public.
+    - For the time being, this includes any `Instance` traits, and `State` or `Info` structs as well.
+  - Functions which technically need to be public but shouldn't be callable by the user need to be sealed.
+    - see [this example in Rust's core library](https://github.com/rust-lang/rust/blob/044a28a4091f2e1a5883f7fa990223f8b200a2cd/library/core/src/error.rs#L89-L100)
+- Any public traits, that **must not** be implemented downstream need to be `Sealed`.
+- Prefer compile-time checks over runtime checks where possible, prefer a fallible API over panics.
+- Follow naming conventions in order to be consistent across drivers - take inspiration from existing drivers.
+- Design APIs in a way that they are easy to use.
+- Driver API decisions should be assessed individually, don't _not_ just follow embedded-hal or other ecosystem trait crates. Expose the capabilities of the hardware. (Ecosystem traits are implemented on top of the inherent API)
+- Avoid type states and extraneous generics whenever possible
+  - These often lead to usability problems, and tend to just complicate things needlessly - sometimes it can be a good tradeoff to make a type not ZST
+  - Common cases of useless type info is storing pin information - this is usually not required after configuring the pins and will bloat the complexity of the type massively. When following the `PeripheralRef` pattern it's not needed in order to keep users from re-using the pin while in use
+- Avoiding `&mut self` when `&self` is safe to use. `&self` is generally easier to use as an API. Typical applications of this are where the methods just do writes to registers which don't have side effects.
+- Maintain order consistency in the API, such as in the case of pairs like RX/TX.
+- If your driver provides a way to listen for interrupts, the interrupts should be listed in a `derive(EnumSetType)` enum as opposed to one function per interrupt flag.
+- If a driver only implements a subset of a peripheral's capabilities, it should be placed in the `peripheral::subcategory` module.
+  - For example, if a driver implements the slave-mode I2C driver, it should be placed into `i2c::slave`.
+  - This helps us reducing the need of introducing breaking changes if we implement additional functionalities.
+- Avoid abbreviations and contractions in the API, where possible.
+  - Saving a few characters may introduce ambiguity, e.g `SpiTransDone`, is it `Transmit` or `Transfer`?
+  - Common abbreviations, that are well understood such as `Dma` are perfectly fine.
+
+## Maintainability
+
+- Avoid excessive use of macros unless there is no other option; modification of the PAC crates should be considered before resorting to macros.
+- Every line of code is a liability. Take some time to see if your implementation can be simplified before opening a PR.
+- If you are porting code from ESP-IDF (or anything else), please include a link WITH the commit hash in it, and please highlight the relevant line(s) of code
+- If necessary provide further context as comments (consider linking to code, PRs, TRM - make sure to use permanent links, e.g. include the hash when linking to a Git repository, include the revision, page number etc. when linking to TRMs)
+- Prefer line comments (//) to block comments (/* ... */)
+- Generally, follow common "good practices" and idiomatic Rust style
+- All `Future` objects (public or private) must be marked with ``#[must_use = "futures do nothing unless you `.await` or poll them"]``.
+- Prefer `cfg_if!` (or, if the branches just pick between separate values of the same variable, `cfg!()`) over multiple exclusive `#[cfg]` attributes. `cfg_if!`/`cfg!()` visually divide the options, often results in simpler conditions and simplifies adding new branches in the future.
+
+## Driver implementation
+
+- If a common `Instance` trait is used for multiple peripherals, those traits should not have any logic implemented in them.
+- The `Instance` traits should only be used to access information about a peripheral instance.
+- The internal implementation of the driver should be non-generic over the peripheral instance. This helps the compiler produce smaller code.
+- The author is encouraged to return a static shared reference to an `Info` and a `State` structure from the `Instance` trait.
+  - The `Info` struct should describe the peripheral. Do not use any interior mutability.
+  - The `State` struct should contain counters, wakers and other, mutable state. As this is accessed via a shared reference, interior mutability and atomic variables are preferred.
+
+## Modules Documentation
+
+Modules should have the following documentation format:
+```rust
+//! # Peripheral Name (Peripheral Acronym)
+//!
+//! ## Overview
+//! Small description of the peripheral, see ESP-IDF docs or TRM
+//!
+//! ## Configuration
+//! Explain how can the peripheral be configured, and which parameters can be configured
+//!
+//! ## Usage
+//! Explain if we implement any external traits
+//!
+//! ## Examples
+//!
+//! ### Name of the Example
+//! Small description of the example if needed
+//! ```rust, no_run
+//! ...
+//! ```
+//!
+//! ## Implementation State
+//! List unsupported features
+```
+- If any of the headers is empty, remove it
+- When possible, use ESP-IDF docs and TRM as references and include links if possible.
+  - In case of referencing an ESP-IDF link make it chip-specific, for example:
+    ```
+    #![doc = concat!("[ESP-IDF documentation](https://docs.espressif.com/projects/esp-idf/en/latest/", crate::soc::chip!(), "/api-reference/peripherals/etm.html)")]
+    ```
+  - In case of referencing a TRM chapter, use the `crate::trm_markdown_link!()` macro. If you are referring to a particular chapter, you may use `crate::trm_markdown_link!("#chapter_anchor")`.
+- Documentation examples must be short
+  - But must also provide value beyond what the rustdoc generated docs show
+    - Showing a snippet of a slightly more complex interaction, for example inverting the signals for a driver
+    - Showing construction if it is more complex, or requires some non-obvious precursor steps. Think about this for drivers that take a generic instance to construct, rustdoc doesn't do a good job of showing what concrete things can be passed into a constructor.
+  - For more complex scenarios, create an example.
+- Use rustdoc syntax for linking to other documentation items instead of markdown links where possible
+  - https://doc.rust-lang.org/rustdoc/write-documentation/linking-to-items-by-name.html

documentation/CONTRIBUTING.md

@@ -0,0 +1,143 @@
+
+# Welcome to the `esp-hal` Contributing Guide
+
+Thank you for considering contributing to our project! Your efforts help make `esp-hal` a better ecosystem for everyone.
+
+This guide outlines the contribution workflow, from reporting issues and submitting pull requests, to the review process and eventual merger of contributions.
+
+## Quick Navigation
+*   [New Contributor Guide]
+*   [Getting Started]
+    *   [Issues: Reporting and Resolving]
+    *   [Making Changes: Fork, Edit, and Pull Request]
+    *   [Testing Your Contributions]
+    *   [Commit Your Updates]
+*   [Pull Request: From Submission to Merge]
+*   [Your PR is merged!]
+
+[New Contributor Guide]: #new-contributor-guide
+[Getting Started]: #getting-started
+[Issues: Reporting and Resolving]: #issues-reporting-and-resolving
+[Making Changes: Fork, Edit, and Pull Request]: #making-changes-fork-edit-and-pull-request
+[Testing Your Contributions]: #testing-your-contributions
+[Commit your updates]: #commit-your-updates
+[Pull Request: From Submission to Merge]: #pull-request-from-submission-to-merge
+[Your PR is merged!]: #your-pr-is-merged
+
+## New Contributor Guide
+
+Welcome aboard! If you're new to `esp-hal` or open-source contribution, here are some resources to get you started:
+
+*   [Understanding the Project]: A high-level overview of `esp-hal`.
+*   Intro to Open Source Contribution: [GitHub's Guide]
+*   [Setting Up Git]
+*   Workflow Insights: [GitHub Flow]
+*   Collaborating via [Pull Requests]
+
+Before adding or changing code, review the [esp-rs API guidelines].
+
+[Understanding the Project]: README.md
+[GitHub's Guide]: https://docs.github.com/en/get-started/exploring-projects-on-github/finding-ways-to-contribute-to-open-source-on-github
+[Setting Up Git]: https://docs.github.com/en/get-started/quickstart/set-up-git
+[GitHub Flow]: https://docs.github.com/en/get-started/quickstart/github-flow
+[Pull Requests]: https://docs.github.com/en/github/collaborating-with-pull-requests
+[esp-rs API guidelines]: ./documentation/API-GUIDELINES.md
+
+## Getting Started
+
+### Issues: Reporting and Resolving
+
+#### Reporting a New Issue
+
+Encountered a problem or have an idea? First, [check existing issues] to avoid duplicates. If your concern is new, use our [issue form] to submit it.
+
+[check existing issues]: https://github.com/esp-rs/esp-hal/issues
+[issue form]: https://github.com/esp-rs/esp-hal/issues/new/
+
+#### Working on an Issue
+
+Browse [existing issues] to find one that resonates with you. Use labels for easier filtering. If you decide to tackle an issue, it's courteous (but not mandatory) to let others know by commenting.
+
+[existing issues]: https://github.com/esp-rs/esp-hal/issues
+
+#### Making Changes: Fork, Edit, and Pull Request
+
+1. **Fork**: Start by [forking the repository]. This keeps the main project safe while you make your changes.
+2. **Setup**: Ensure you have the latest Rust toolchain via [rustup.rs].
+3. **Branch**: Create a branch in your fork for your changes. Keep your changes focused and limited to a single issue or feature.
+
+[forking the repository]: https://docs.github.com/en/github/getting-started-with-github/fork-a-repo
+[rustup.rs]: https://rustup.rs/
+
+#### What You Should Do:
+
+* **API changes**: If your contribution changes the API, please adapt the driver (including module level documentation) and examples accordingly and update the [HIL] (Hardware-in-the-Loop) tests.
+* **Run Related Examples**: After making changes, run any affected examples to ensure they build successfully and perform as expected.
+* **Manual Testing**: For hardware-related changes, manually test your changes on the actual devices when possible. If not, please note it in the corresponding issue, and someone from our team will assist with testing. This is crucial because hardware behavior can sometimes differ from what's simulated or expected.
+* **HIL Tests**: Ensure that any changes to the API or hardware interaction logic are reflected in the HIL tests located in the `hil-test` directory. This helps verify the real-world applicability of your changes.
+
+By taking these extra steps to test your contributions, you help maintain the high quality and reliability of `esp-hal`, ensuring it remains a robust platform for everyone.
+
+[HIL]: https://github.com/esp-rs/esp-hal/tree/main/hil-test
+
+### Testing Your Contributions
+
+Ensuring the quality and reliability of `esp-hal` is a shared responsibility, and testing plays a critical role in this process. Our GitHub CI automatically checks the buildability of all examples and drivers within the project. However, automated tests can't catch everything, especially when it comes to the nuanced behavior of hardware interactions. So make sure that the example affected by your change works as expected. 
+
+Further steps that can (or should) be taken in testing:
+
+* Using [xtask], build examples for the specified chip.
+* Build the documentation and run the doctests if they have been modified using the `build-documentation` and  `run-doc-test` commands in [xtask].
+* Run the [HIL] tests locally if changes have been made to them.
+
+[xtask]: https://github.com/esp-rs/esp-hal/tree/main/xtask
+
+### Commit Your Updates
+
+Commit your changes once you're satisfied. Review your own work to streamline the review process later. Use `rustfmt` and `cargo clippy` to ensure your code adheres to Rust's conventions.
+
+```shell
+rustup component add rustfmt
+rustup component add clippy
+```
+
+We _strongly_ recommend that you format your code before committing to ensure consistency throughout the project.
+To format all packages in the workspace, run the following command in a terminal from the root of the repository:
+
+```shell
+cargo xtask fmt-packages
+```
+
+We also recommend using the `lint-packages` subcommand, which uses `cargo clippy` and will lint the entire driver in order to catch common mistakes in the code.
+
+```shell
+cargo xtask lint-packages
+```
+
+This will use `rustfmt` to ensure that all source code is formatted correctly prior to committing.
+
+## Pull Request: From Submission to Merge
+
+*   Fill the pull request template so that we can review your PR. This template helps reviewers understand your changes as well as the purpose of your pull request.
+*   [Link your PR] to any relevant issues it addresses.
+*   [Allow edits from maintainers] so the branch can be updated for a merge. Once you submit your PR, a Docs team member will review your proposal. We may ask questions or request additional information.
+*   Make sure you add an entry with your changes to the [Changelog]. Also make sure that it is in the appropriate section of the document.
+*   Make sure you add your changes to the current [migration guide].
+*   We may ask for changes to be made before a PR can be merged, either using [suggested changes] or pull request comments. You can apply suggested changes directly through the UI. You can make any other changes in your fork, then commit them to your branch.
+*   As you update your PR and apply changes, mark each conversation as [resolved].
+*   Resolve merge conflicts if they arise, using resources like [this git tutorial] for help.
+
+[Link your PR]: https://docs.github.com/en/issues/tracking-your-work-with-issues/linking-a-pull-request-to-an-issue
+[Allow edits from maintainers]: https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/allowing-changes-to-a-pull-request-branch-created-from-a-forkmember
+[Changelog]: esp-hal/CHANGELOG.md
+[migration guide]: esp-hal/MIGRATING-0.20.md
+[suggested changes]: https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/incorporating-feedback-in-your-pull-request
+[resolved]: https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/reviewing-changes-in-pull-requests/commenting-on-a-pull-request#resolving-conversations
+[this git tutorial]: https://github.com/skills/resolve-merge-conflicts
+
+
+## Your PR is Merged!
+
+Congratulations! The `esp-rs` team thanks you for your contributions!
+
+Contributing to open source extends beyond just code! Each contribution, regardless of size, plays a significant role. We appreciate your involvement in this collective endeavor.

esp-alloc/.clippy.toml

@@ -0,0 +1 @@
+avoid-breaking-exported-api = false

esp-alloc/CHANGELOG.md

@@ -0,0 +1,36 @@
+# Changelog
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
+and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+
+## [Unreleased]
+
+### Added
+
+- `esp_alloc::HEAP.stats()` can now be used to get heap usage informations (#2137)
+
+### Changed
+
+### Fixed
+
+### Removed
+
+## 0.5.0 - 2024-10-10
+
+### Changed
+
+- a global allocator is created in esp-alloc, now you need to add individual memory regions (up to 3) to the allocator (#2099)
+
+## 0.4.0 - 2024-06-04
+
+## 0.3.0 - 2023-04-25
+
+## 0.2.1 - 2023-04-21
+
+## 0.2.0 - 2023-02-22
+
+## 0.1.0 - 2022-07-25
+
+[Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp-alloc?since=2024-10-10

esp-alloc/Cargo.toml

@@ -0,0 +1,37 @@
+[package]
+name         = "esp-alloc"
+version      = "0.5.0"
+edition      = "2021"
+rust-version = "1.68"
+description  = "A heap allocator for Espressif devices"
+keywords     = ["allocator", "embedded", "embedded-hal", "esp32", "espressif", "memory"]
+categories   = ["embedded", "memory-management", "no-std"]
+repository   = "https://github.com/esp-rs/esp-hal"
+license      = "MIT OR Apache-2.0"
+
+[package.metadata.docs.rs]
+default-target = "riscv32imc-unknown-none-elf"
+features       = ["nightly"]
+
+[dependencies]
+defmt                 = { version = "0.3.8", optional = true }
+cfg-if                = "1.0.0"
+critical-section      = "1.1.3"
+enumset               = "1.1.5"
+linked_list_allocator = { version = "0.10.5", default-features = false, features = ["const_mut_refs"] }
+document-features     = "0.2.10"
+
+[features]
+default = []
+nightly = []
+
+## Implement `defmt::Format` on certain types.
+defmt = ["dep:defmt"]
+
+## Enable this feature if you want to keep stats about the internal heap usage such as:
+## - Max memory usage since initialization of the heap
+## - Total allocated memory since initialization of the heap
+## - Total freed memory since initialization of the heap
+##
+## ⚠️ Note: Enabling this feature will require extra computation every time alloc/dealloc is called.
+internal-heap-stats = []

esp-alloc/README.md

@@ -0,0 +1,26 @@
+# esp-alloc
+
+[![Crates.io](https://img.shields.io/crates/v/esp-alloc?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-alloc)
+[![docs.rs](https://img.shields.io/docsrs/esp-alloc?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-alloc)
+![MSRV](https://img.shields.io/badge/MSRV-1.68-blue?labelColor=1C2C2E&style=flat-square)
+![Crates.io](https://img.shields.io/crates/l/esp-alloc?labelColor=1C2C2E&style=flat-square)
+[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
+
+A simple `no_std` heap allocator for RISC-V and Xtensa processors from Espressif. Supports all currently available ESP32 devices.
+
+**NOTE:** using this as your global allocator requires using Rust 1.68 or greater, or the `nightly` release channel.
+
+## License
+
+Licensed under either of:
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
+the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
+any additional terms or conditions.

esp-alloc/src/lib.rs

@@ -0,0 +1,589 @@
+//! A `no_std` heap allocator for RISC-V and Xtensa processors from
+//! Espressif. Supports all currently available ESP32 devices.
+//!
+//! **NOTE:** using this as your global allocator requires using Rust 1.68 or
+//! greater, or the `nightly` release channel.
+//!
+//! # Using this as your Global Allocator
+//!
+//! ```rust
+//! use esp_alloc as _;
+//!
+//! fn init_heap() {
+//!     const HEAP_SIZE: usize = 32 * 1024;
+//!     static mut HEAP: MaybeUninit<[u8; HEAP_SIZE]> = MaybeUninit::uninit();
+//!
+//!     unsafe {
+//!         esp_alloc::HEAP.add_region(esp_alloc::HeapRegion::new(
+//!             HEAP.as_mut_ptr() as *mut u8,
+//!             HEAP_SIZE,
+//!             esp_alloc::MemoryCapability::Internal.into(),
+//!         ));
+//!     }
+//! }
+//! ```
+//!
+//! # Using this with the nightly `allocator_api`-feature
+//! Sometimes you want to have more control over allocations.
+//!
+//! For that, it's convenient to use the nightly `allocator_api`-feature,
+//! which allows you to specify an allocator for single allocations.
+//!
+//! **NOTE:** To use this, you have to enable the crate's `nightly` feature
+//! flag.
+//!
+//! Create and initialize an allocator to use in single allocations:
+//! ```rust
+//! static PSRAM_ALLOCATOR: esp_alloc::EspHeap = esp_alloc::EspHeap::empty();
+//!
+//! fn init_psram_heap() {
+//!     unsafe {
+//!         PSRAM_ALLOCATOR.add_region(esp_alloc::HeapRegion::new(
+//!             psram::psram_vaddr_start() as *mut u8,
+//!             psram::PSRAM_BYTES,
+//!             esp_alloc::MemoryCapability::Internal.into(),
+//!         ));
+//!     }
+//! }
+//! ```
+//!
+//! And then use it in an allocation:
+//! ```rust
+//! let large_buffer: Vec<u8, _> = Vec::with_capacity_in(1048576, &PSRAM_ALLOCATOR);
+//! ```
+//!
+//! You can also get stats about the heap usage at anytime with:
+//! ```rust
+//! let stats: HeapStats = esp_alloc::HEAP.stats();
+//! // HeapStats implements the Display and defmt::Format traits, so you can pretty-print the heap stats.
+//! println!("{}", stats);
+//! ```
+//!
+//! ```txt
+//! HEAP INFO
+//! Size: 131068
+//! Current usage: 46148
+//! Max usage: 46148
+//! Total freed: 0
+//! Total allocated: 46148
+//! Memory Layout:
+//! Internal | ████████████░░░░░░░░░░░░░░░░░░░░░░░ | Used: 35% (Used 46148 of 131068, free: 84920)
+//! Unused   | ░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░ |
+//! Unused   | ░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░░ |
+//! ```
+//! ## Feature Flags
+#![doc = document_features::document_features!()]
+#![no_std]
+#![cfg_attr(feature = "nightly", feature(allocator_api))]
+#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
+
+mod macros;
+
+#[cfg(feature = "nightly")]
+use core::alloc::{AllocError, Allocator};
+use core::{
+    alloc::{GlobalAlloc, Layout},
+    cell::RefCell,
+    fmt::Display,
+    ptr::{self, NonNull},
+};
+
+use critical_section::Mutex;
+use enumset::{EnumSet, EnumSetType};
+use linked_list_allocator::Heap;
+
+/// The global allocator instance
+#[global_allocator]
+pub static HEAP: EspHeap = EspHeap::empty();
+
+const NON_REGION: Option<HeapRegion> = None;
+
+const BAR_WIDTH: usize = 35;
+
+fn write_bar(f: &mut core::fmt::Formatter<'_>, usage_percent: usize) -> core::fmt::Result {
+    let used_blocks = BAR_WIDTH * usage_percent / 100;
+    (0..used_blocks).try_for_each(|_| write!(f, "█"))?;
+    (used_blocks..BAR_WIDTH).try_for_each(|_| write!(f, "░"))
+}
+
+#[cfg(feature = "defmt")]
+fn write_bar_defmt(fmt: defmt::Formatter, usage_percent: usize) {
+    let used_blocks = BAR_WIDTH * usage_percent / 100;
+    (0..used_blocks).for_each(|_| defmt::write!(fmt, "█"));
+    (used_blocks..BAR_WIDTH).for_each(|_| defmt::write!(fmt, "░"));
+}
+
+#[derive(EnumSetType, Debug)]
+/// Describes the properties of a memory region
+pub enum MemoryCapability {
+    /// Memory must be internal; specifically it should not disappear when
+    /// flash/spiram cache is switched off
+    Internal,
+    /// Memory must be in SPI RAM
+    External,
+}
+
+/// Stats for a heap region
+#[derive(Debug)]
+pub struct RegionStats {
+    /// Total usable size of the heap region in bytes.
+    size: usize,
+
+    /// Currently used size of the heap region in bytes.
+    used: usize,
+
+    /// Free size of the heap region in bytes.
+    free: usize,
+
+    /// Capabilities of the memory region.
+    capabilities: EnumSet<MemoryCapability>,
+}
+
+impl Display for RegionStats {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let usage_percent = self.used * 100 / self.size;
+
+        // Display Memory type
+        if self.capabilities.contains(MemoryCapability::Internal) {
+            write!(f, "Internal")?;
+        } else if self.capabilities.contains(MemoryCapability::External) {
+            write!(f, "External")?;
+        } else {
+            write!(f, "Unknown")?;
+        }
+
+        write!(f, " | ")?;
+
+        write_bar(f, usage_percent)?;
+
+        write!(
+            f,
+            " | Used: {}% (Used {} of {}, free: {})",
+            usage_percent, self.used, self.size, self.free
+        )
+    }
+}
+
+#[cfg(feature = "defmt")]
+impl defmt::Format for RegionStats {
+    fn format(&self, fmt: defmt::Formatter) {
+        let usage_percent = self.used * 100 / self.size;
+
+        if self.capabilities.contains(MemoryCapability::Internal) {
+            defmt::write!(fmt, "Internal");
+        } else if self.capabilities.contains(MemoryCapability::External) {
+            defmt::write!(fmt, "External");
+        } else {
+            defmt::write!(fmt, "Unknown");
+        }
+
+        defmt::write!(fmt, " | ");
+
+        write_bar_defmt(fmt, usage_percent);
+
+        defmt::write!(
+            fmt,
+            " | Used: {}% (Used {} of {}, free: {})",
+            usage_percent,
+            self.used,
+            self.size,
+            self.free
+        );
+    }
+}
+
+/// A memory region to be used as heap memory
+pub struct HeapRegion {
+    heap: Heap,
+    capabilities: EnumSet<MemoryCapability>,
+}
+
+impl HeapRegion {
+    /// Create a new [HeapRegion] with the given capabilities
+    ///
+    /// # Safety
+    ///
+    /// - The supplied memory region must be available for the entire program
+    ///   (`'static`).
+    /// - The supplied memory region must be exclusively available to the heap
+    ///   only, no aliasing.
+    /// - `size > 0`.
+    pub unsafe fn new(
+        heap_bottom: *mut u8,
+        size: usize,
+        capabilities: EnumSet<MemoryCapability>,
+    ) -> Self {
+        let mut heap = Heap::empty();
+        heap.init(heap_bottom, size);
+
+        Self { heap, capabilities }
+    }
+
+    /// Return stats for the current memory region
+    pub fn stats(&self) -> RegionStats {
+        RegionStats {
+            size: self.heap.size(),
+            used: self.heap.used(),
+            free: self.heap.free(),
+            capabilities: self.capabilities,
+        }
+    }
+}
+
+/// Stats for a heap allocator
+///
+/// Enable the "internal-heap-stats" feature if you want collect additional heap
+/// informations at the cost of extra cpu time during every alloc/dealloc.
+#[derive(Debug)]
+pub struct HeapStats {
+    /// Granular stats for all the configured memory regions.
+    region_stats: [Option<RegionStats>; 3],
+
+    /// Total size of all combined heap regions in bytes.
+    size: usize,
+
+    /// Current usage of the heap across all configured regions in bytes.
+    current_usage: usize,
+
+    /// Estimation of the max used heap in bytes.
+    #[cfg(feature = "internal-heap-stats")]
+    max_usage: usize,
+
+    /// Estimation of the total allocated bytes since initialization.
+    #[cfg(feature = "internal-heap-stats")]
+    total_allocated: usize,
+
+    /// Estimation of the total freed bytes since initialization.
+    #[cfg(feature = "internal-heap-stats")]
+    total_freed: usize,
+}
+
+impl Display for HeapStats {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        writeln!(f, "HEAP INFO")?;
+        writeln!(f, "Size: {}", self.size)?;
+        writeln!(f, "Current usage: {}", self.current_usage)?;
+        #[cfg(feature = "internal-heap-stats")]
+        {
+            writeln!(f, "Max usage: {}", self.max_usage)?;
+            writeln!(f, "Total freed: {}", self.total_freed)?;
+            writeln!(f, "Total allocated: {}", self.total_allocated)?;
+        }
+        writeln!(f, "Memory Layout: ")?;
+        for region in self.region_stats.iter() {
+            if let Some(region) = region.as_ref() {
+                region.fmt(f)?;
+                writeln!(f)?;
+            } else {
+                // Display unused memory regions
+                write!(f, "Unused   | ")?;
+                write_bar(f, 0)?;
+                writeln!(f, " |")?;
+            }
+        }
+        Ok(())
+    }
+}
+
+#[cfg(feature = "defmt")]
+impl defmt::Format for HeapStats {
+    fn format(&self, fmt: defmt::Formatter) {
+        defmt::write!(fmt, "HEAP INFO\n");
+        defmt::write!(fmt, "Size: {}\n", self.size);
+        defmt::write!(fmt, "Current usage: {}\n", self.current_usage);
+        #[cfg(feature = "internal-heap-stats")]
+        {
+            defmt::write!(fmt, "Max usage: {}\n", self.max_usage);
+            defmt::write!(fmt, "Total freed: {}\n", self.total_freed);
+            defmt::write!(fmt, "Total allocated: {}\n", self.total_allocated);
+        }
+        defmt::write!(fmt, "Memory Layout:\n");
+        for region in self.region_stats.iter() {
+            if let Some(region) = region.as_ref() {
+                defmt::write!(fmt, "{}\n", region);
+            } else {
+                defmt::write!(fmt, "Unused   | ");
+                write_bar_defmt(fmt, 0);
+                defmt::write!(fmt, " |\n");
+            }
+        }
+    }
+}
+
+/// Internal stats to keep track across multiple regions.
+#[cfg(feature = "internal-heap-stats")]
+struct InternalHeapStats {
+    max_usage: usize,
+    total_allocated: usize,
+    total_freed: usize,
+}
+
+/// A memory allocator
+///
+/// In addition to what Rust's memory allocator can do it allows to allocate
+/// memory in regions satisfying specific needs.
+pub struct EspHeap {
+    heap: Mutex<RefCell<[Option<HeapRegion>; 3]>>,
+    #[cfg(feature = "internal-heap-stats")]
+    internal_heap_stats: Mutex<RefCell<InternalHeapStats>>,
+}
+
+impl EspHeap {
+    /// Crate a new UNINITIALIZED heap allocator
+    pub const fn empty() -> Self {
+        EspHeap {
+            heap: Mutex::new(RefCell::new([NON_REGION; 3])),
+            #[cfg(feature = "internal-heap-stats")]
+            internal_heap_stats: Mutex::new(RefCell::new(InternalHeapStats {
+                max_usage: 0,
+                total_allocated: 0,
+                total_freed: 0,
+            })),
+        }
+    }
+
+    /// Add a memory region to the heap
+    ///
+    /// `heap_bottom` is a pointer to the location of the bottom of the heap.
+    ///
+    /// `size` is the size of the heap in bytes.
+    ///
+    /// You can add up to three regions per allocator.
+    ///
+    /// Note that:
+    ///
+    /// - Memory is allocated from the first suitable memory region first
+    ///
+    /// - The heap grows "upwards", towards larger addresses. Thus `end_addr`
+    ///   must be larger than `start_addr`
+    ///
+    /// - The size of the heap is `(end_addr as usize) - (start_addr as usize)`.
+    ///   The allocator won't use the byte at `end_addr`.
+    ///
+    /// # Safety
+    ///
+    /// - The supplied memory region must be available for the entire program (a
+    ///   `'static` lifetime).
+    /// - The supplied memory region must be exclusively available to the heap
+    ///   only, no aliasing.
+    /// - `size > 0`.
+    pub unsafe fn add_region(&self, region: HeapRegion) {
+        critical_section::with(|cs| {
+            let mut regions = self.heap.borrow_ref_mut(cs);
+            let free = regions
+                .iter()
+                .enumerate()
+                .find(|v| v.1.is_none())
+                .map(|v| v.0);
+
+            if let Some(free) = free {
+                regions[free] = Some(region);
+            } else {
+                panic!(
+                    "Exceeded the maximum of {} heap memory regions",
+                    regions.len()
+                );
+            }
+        });
+    }
+
+    /// Returns an estimate of the amount of bytes in use in all memory regions.
+    pub fn used(&self) -> usize {
+        critical_section::with(|cs| {
+            let regions = self.heap.borrow_ref(cs);
+            let mut used = 0;
+            for region in regions.iter() {
+                if let Some(region) = region.as_ref() {
+                    used += region.heap.used();
+                }
+            }
+            used
+        })
+    }
+
+    /// Return usage stats for the [Heap].
+    ///
+    /// Note:
+    /// [HeapStats] directly implements [Display], so this function can be
+    /// called from within `println!()` to pretty-print the usage of the
+    /// heap.
+    pub fn stats(&self) -> HeapStats {
+        const EMPTY_REGION_STAT: Option<RegionStats> = None;
+        let mut region_stats: [Option<RegionStats>; 3] = [EMPTY_REGION_STAT; 3];
+
+        critical_section::with(|cs| {
+            let mut used = 0;
+            let mut free = 0;
+            let regions = self.heap.borrow_ref(cs);
+            for (id, region) in regions.iter().enumerate() {
+                if let Some(region) = region.as_ref() {
+                    let stats = region.stats();
+                    free += stats.free;
+                    used += stats.used;
+                    region_stats[id] = Some(region.stats());
+                }
+            }
+
+            cfg_if::cfg_if! {
+                if #[cfg(feature = "internal-heap-stats")] {
+                    let internal_heap_stats = self.internal_heap_stats.borrow_ref(cs);
+                    HeapStats {
+                        region_stats,
+                        size: free + used,
+                        current_usage: used,
+                        max_usage: internal_heap_stats.max_usage,
+                        total_allocated: internal_heap_stats.total_allocated,
+                        total_freed: internal_heap_stats.total_freed,
+                    }
+                } else {
+                    HeapStats {
+                        region_stats,
+                        size: free + used,
+                        current_usage: used,
+                    }
+                }
+            }
+        })
+    }
+
+    /// Returns an estimate of the amount of bytes available.
+    pub fn free(&self) -> usize {
+        self.free_caps(EnumSet::empty())
+    }
+
+    /// The free heap satisfying the given requirements
+    pub fn free_caps(&self, capabilities: EnumSet<MemoryCapability>) -> usize {
+        critical_section::with(|cs| {
+            let regions = self.heap.borrow_ref(cs);
+            let mut free = 0;
+            for region in regions.iter().filter(|region| {
+                if region.is_some() {
+                    region
+                        .as_ref()
+                        .unwrap()
+                        .capabilities
+                        .is_superset(capabilities)
+                } else {
+                    false
+                }
+            }) {
+                if let Some(region) = region.as_ref() {
+                    free += region.heap.free();
+                }
+            }
+            free
+        })
+    }
+
+    /// Allocate memory in a region satisfying the given requirements.
+    ///
+    /// # Safety
+    ///
+    /// This function is unsafe because undefined behavior can result
+    /// if the caller does not ensure that `layout` has non-zero size.
+    ///
+    /// The allocated block of memory may or may not be initialized.
+    pub unsafe fn alloc_caps(
+        &self,
+        capabilities: EnumSet<MemoryCapability>,
+        layout: Layout,
+    ) -> *mut u8 {
+        critical_section::with(|cs| {
+            #[cfg(feature = "internal-heap-stats")]
+            let before = self.used();
+            let mut regions = self.heap.borrow_ref_mut(cs);
+            let mut iter = (*regions).iter_mut().filter(|region| {
+                if region.is_some() {
+                    region
+                        .as_ref()
+                        .unwrap()
+                        .capabilities
+                        .is_superset(capabilities)
+                } else {
+                    false
+                }
+            });
+
+            let res = loop {
+                if let Some(Some(region)) = iter.next() {
+                    let res = region.heap.allocate_first_fit(layout);
+                    if let Ok(res) = res {
+                        break Some(res);
+                    }
+                } else {
+                    break None;
+                }
+            };
+
+            res.map_or(ptr::null_mut(), |allocation| {
+                #[cfg(feature = "internal-heap-stats")]
+                {
+                    let mut internal_heap_stats = self.internal_heap_stats.borrow_ref_mut(cs);
+                    drop(regions);
+                    // We need to call used because [linked_list_allocator::Heap] does internal size
+                    // alignment so we cannot use the size provided by the layout.
+                    let used = self.used();
+
+                    internal_heap_stats.total_allocated += used - before;
+                    internal_heap_stats.max_usage =
+                        core::cmp::max(internal_heap_stats.max_usage, used);
+                }
+
+                allocation.as_ptr()
+            })
+        })
+    }
+}
+
+unsafe impl GlobalAlloc for EspHeap {
+    unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
+        self.alloc_caps(EnumSet::empty(), layout)
+    }
+
+    unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
+        if ptr.is_null() {
+            return;
+        }
+
+        critical_section::with(|cs| {
+            #[cfg(feature = "internal-heap-stats")]
+            let before = self.used();
+            let mut regions = self.heap.borrow_ref_mut(cs);
+            let mut iter = (*regions).iter_mut();
+
+            while let Some(Some(region)) = iter.next() {
+                if region.heap.bottom() <= ptr && region.heap.top() >= ptr {
+                    region.heap.deallocate(NonNull::new_unchecked(ptr), layout);
+                }
+            }
+
+            #[cfg(feature = "internal-heap-stats")]
+            {
+                let mut internal_heap_stats = self.internal_heap_stats.borrow_ref_mut(cs);
+                drop(regions);
+                // We need to call `used()` because [linked_list_allocator::Heap] does internal
+                // size alignment so we cannot use the size provided by the
+                // layout.
+                internal_heap_stats.total_freed += before - self.used();
+            }
+        })
+    }
+}
+
+#[cfg(feature = "nightly")]
+unsafe impl Allocator for EspHeap {
+    fn allocate(&self, layout: Layout) -> Result<NonNull<[u8]>, AllocError> {
+        let raw_ptr = unsafe { self.alloc(layout) };
+
+        if raw_ptr.is_null() {
+            return Err(AllocError);
+        }
+
+        let ptr = NonNull::new(raw_ptr).ok_or(AllocError)?;
+        Ok(NonNull::slice_from_raw_parts(ptr, layout.size()))
+    }
+
+    unsafe fn deallocate(&self, ptr: NonNull<u8>, layout: Layout) {
+        self.dealloc(ptr.as_ptr(), layout);
+    }
+}

esp-alloc/src/macros.rs

@@ -0,0 +1,43 @@
+//! Macros provided for convenience
+
+/// Initialize a global heap allocator providing a heap of the given size in
+/// bytes
+#[macro_export]
+macro_rules! heap_allocator {
+    ($size:expr) => {{
+        static mut HEAP: core::mem::MaybeUninit<[u8; $size]> = core::mem::MaybeUninit::uninit();
+
+        unsafe {
+            $crate::HEAP.add_region($crate::HeapRegion::new(
+                HEAP.as_mut_ptr() as *mut u8,
+                $size,
+                $crate::MemoryCapability::Internal.into(),
+            ));
+        }
+    }};
+}
+
+/// Initialize a global heap allocator backed by PSRAM
+///
+/// You need a SoC which supports PSRAM
+/// and activate the feature to enable it. You need to pass the PSRAM peripheral
+/// and the psram module path.
+///
+/// # Usage
+/// ```rust, no_run
+/// esp_alloc::psram_allocator!(peripherals.PSRAM, hal::psram);
+/// ```
+#[macro_export]
+macro_rules! psram_allocator {
+    ($peripheral:expr, $psram_module:path) => {{
+        use $psram_module as _psram;
+        let (start, size) = _psram::psram_raw_parts(&$peripheral);
+        unsafe {
+            $crate::HEAP.add_region($crate::HeapRegion::new(
+                start,
+                size,
+                $crate::MemoryCapability::External.into(),
+            ));
+        }
+    }};
+}

esp-backtrace/CHANGELOG.md

@@ -0,0 +1,63 @@
+# Changelog
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
+and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+
+## [Unreleased]
+
+### Added
+
+### Changed
+
+### Fixed
+
+### Removed
+
+## 0.14.2 - 2024-10-10
+
+### Fixed
+
+- Fix build when not using `panic-handler` (#2257)
+
+## 0.14.1 - 2024-09-06
+
+### Added
+
+### Changed
+
+- Print a more helpful message in case of a `Cp0Disabled` exception (#2061)
+
+### Fixed
+
+### Removed
+
+## 0.14.0 - 2024-08-29
+
+### Added
+
+- Add custom-pre-backtrace feature (#1822)
+
+### Changed
+
+- Improve panic message printing (#1823)
+
+## 0.13.0 - 2024-07-16
+
+No changes - published to avoid conflicts with `esp-println`
+
+## 0.12.2 - 2024-07-15
+
+### Changed
+
+- Remove build script check for `nightly-2024-06-12` (#1788)
+
+## 0.12.1 - 2024-06-19
+
+### Fixed
+
+- Fix compilation for nightly after 2024-06-12. (#1681)
+- Only prints float registers on targets which have them. (#1690)
+
+[Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp-backtrace?since=2024-10-10

esp-backtrace/Cargo.toml

@@ -0,0 +1,55 @@
+[package]
+name         = "esp-backtrace"
+version      = "0.14.2"
+edition      = "2021"
+rust-version = "1.76.0"
+description  = "Bare-metal backtrace support for Espressif devices"
+keywords     = ["backtrace", "embedded", "esp32", "espressif"]
+categories   = ["embedded", "hardware-support", "no-std"]
+repository   = "https://github.com/esp-rs/esp-hal"
+license      = "MIT OR Apache-2.0"
+
+[package.metadata.docs.rs]
+default-target = "riscv32imc-unknown-none-elf"
+features       = ["esp32c3", "panic-handler", "exception-handler", "println", "esp-println/uart"]
+
+[dependencies]
+defmt       = { version = "0.3.8",  optional = true }
+esp-println = { version = "0.12.0", optional = true, default-features = false, path = "../esp-println" }
+semihosting = { version = "0.1.15", optional = true }
+
+[build-dependencies]
+esp-build = { version = "0.1.0", path = "../esp-build" }
+
+[features]
+default = ["colors"]
+
+# You must enable exactly one of the below features to support the correct chip:
+esp32   = ["esp-println?/esp32", "semihosting?/openocd-semihosting", "print-float-registers"]
+esp32c2 = ["esp-println?/esp32c2"]
+esp32c3 = ["esp-println?/esp32c3"]
+esp32c6 = ["esp-println?/esp32c6"]
+esp32h2 = ["esp-println?/esp32h2"]
+esp32p4 = ["esp-println?/esp32p4"]
+esp32s2 = ["esp-println?/esp32s2", "semihosting?/openocd-semihosting"]
+esp32s3 = ["esp-println?/esp32s3", "semihosting?/openocd-semihosting", "print-float-registers"]
+
+# Use esp-println
+println = ["dep:esp-println"]
+
+# Use defmt
+defmt = ["dep:defmt"]
+
+print-float-registers = [] # TODO support esp32p4
+
+# You may optionally enable one or more of the below features to provide
+# additional functionality:
+colors               = []
+custom-halt          = []
+custom-pre-backtrace = []
+exception-handler    = []
+halt-cores           = []
+panic-handler        = []
+
+[lints.rust]
+unexpected_cfgs = "allow"

esp-backtrace/README.md

@@ -0,0 +1,60 @@
+# esp-backtrace - backtrace for ESP32 bare-metal
+
+[![Crates.io](https://img.shields.io/crates/v/esp-backtrace?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-backtrace)
+[![docs.rs](https://img.shields.io/docsrs/esp-backtrace?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-backtrace)
+![MSRV](https://img.shields.io/badge/MSRV-1.76-blue?labelColor=1C2C2E&style=flat-square)
+![Crates.io](https://img.shields.io/crates/l/esp-backtrace?labelColor=1C2C2E&style=flat-square)
+[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
+
+Supports the ESP32, ESP32-C2/C3/C6, ESP32-H2, ESP32-P4, and ESP32-S2/S3. Optional exception and panic handlers are included, both of which can be enabled via their respective features.
+
+Please note that when targeting a RISC-V device, you **need** to force frame pointers (i.e. `"-C", "force-frame-pointers",` in your `.cargo/config.toml`); this is **not** required for Xtensa.
+
+You can get an array of backtrace addresses (currently limited to 10) via `arch::backtrace()` if
+you want to create a backtrace yourself (i.e. not using the panic or exception handler).
+
+When using the panic and/or exception handler make sure to include `use esp_backtrace as _;`.
+
+## Features
+
+| Feature              | Description                                                                                                        |
+|----------------------|--------------------------------------------------------------------------------------------------------------------|
+| esp32                | Target ESP32                                                                                                       |
+| esp32c2              | Target ESP32-C2                                                                                                    |
+| esp32c3              | Target ESP32-C3                                                                                                    |
+| esp32c6              | Target ESP32-C6                                                                                                    |
+| esp32h2              | Target ESP32-H2                                                                                                    |
+| esp32p4              | Target ESP32-P4                                                                                                    |
+| esp32s2              | Target ESP32-S2                                                                                                    |
+| esp32s3              | Target ESP32-S3                                                                                                    |
+| panic-handler        | Include a panic handler, will add `esp-println` as a dependency                                                    |
+| exception-handler    | Include an exception handler, will add `esp-println` as a dependency                                               |
+| println              | Use `esp-println` to print messages                                                                                |
+| defmt                | Use `defmt` logging to print messages\* (check [example](https://github.com/playfulFence/backtrace-defmt-example)) |
+| colors               | Print messages in red\*                                                                                            |
+| halt-cores           | Halt both CPUs on ESP32 / ESP32-S3 instead of doing a `loop {}` in case of a panic or exception                    |
+| semihosting          | Call `semihosting::process::abort()` on panic.                                                                     |
+| custom-halt          | Invoke the extern function `custom_halt()` instead of doing a `loop {}` in case of a panic or exception            |
+| custom-pre-backtrace | Invoke the extern function `custom_pre_backtrace()` before handling a panic or exception                           |
+
+\* _only used for panic and exception handlers_
+
+### `defmt` Feature
+
+Please note that `defmt` does _not_ provide MSRV guarantees with releases, and as such we are not able to make any MSRV guarantees when this feature is enabled. For more information refer to the MSRV section of `defmt`'s README:
+https://github.com/knurling-rs/defmt?tab=readme-ov-file#msrv
+
+## License
+
+Licensed under either of:
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
+the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
+any additional terms or conditions.

esp-backtrace/build.rs

@@ -0,0 +1,15 @@
+use esp_build::assert_unique_used_features;
+
+fn main() {
+    // Ensure that only a single chip is specified:
+    assert_unique_used_features!(
+        "esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32p4", "esp32s2", "esp32s3"
+    );
+
+    // Ensure that exactly a backend is selected:
+    assert_unique_used_features!("defmt", "println");
+
+    if cfg!(feature = "custom-halt") && cfg!(feature = "halt-cores") {
+        panic!("Only one of `custom-halt` and `halt-cores` can be enabled");
+    }
+}

esp-backtrace/src/lib.rs

@@ -0,0 +1,341 @@
+#![allow(rustdoc::bare_urls, unused_macros)]
+#![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))]
+#![doc = include_str!("../README.md")]
+#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
+#![no_std]
+
+#[cfg(feature = "defmt")]
+use defmt as _;
+#[cfg(feature = "println")]
+use esp_println as _;
+
+const MAX_BACKTRACE_ADDRESSES: usize = 10;
+
+#[cfg(feature = "colors")]
+const RESET: &str = "\u{001B}[0m";
+#[cfg(feature = "colors")]
+const RED: &str = "\u{001B}[31m";
+
+#[cfg(feature = "defmt")]
+macro_rules! println {
+    ("") => {
+        // Do nothing if the string is just a space
+    };
+    ($($arg:tt)*) => {
+        defmt::error!($($arg)*);
+    };
+}
+
+#[cfg(all(feature = "println", not(feature = "defmt")))]
+macro_rules! println {
+    ($($arg:tt)*) => {
+        esp_println::println!($($arg)*);
+    };
+}
+
+#[allow(unused, unused_variables)]
+fn set_color_code(code: &str) {
+    #[cfg(feature = "println")]
+    {
+        println!("{}", code);
+    }
+}
+
+#[cfg_attr(target_arch = "riscv32", path = "riscv.rs")]
+#[cfg_attr(target_arch = "xtensa", path = "xtensa.rs")]
+pub mod arch;
+
+#[cfg(feature = "panic-handler")]
+#[panic_handler]
+fn panic_handler(info: &core::panic::PanicInfo) -> ! {
+    pre_backtrace();
+
+    #[cfg(feature = "colors")]
+    set_color_code(RED);
+
+    println!("");
+    println!("====================== PANIC ======================");
+
+    #[cfg(not(feature = "defmt"))]
+    println!("{}", info);
+
+    #[cfg(feature = "defmt")]
+    println!("{}", defmt::Display2Format(info));
+
+    println!("");
+    println!("Backtrace:");
+    println!("");
+
+    let backtrace = crate::arch::backtrace();
+    #[cfg(target_arch = "riscv32")]
+    if backtrace.iter().filter(|e| e.is_some()).count() == 0 {
+        println!("No backtrace available - make sure to force frame-pointers. (see https://crates.io/crates/esp-backtrace)");
+    }
+    for addr in backtrace.into_iter().flatten() {
+        #[cfg(all(feature = "colors", feature = "println"))]
+        println!("{}0x{:x}", RED, addr - crate::arch::RA_OFFSET);
+
+        #[cfg(not(all(feature = "colors", feature = "println")))]
+        println!("0x{:x}", addr - crate::arch::RA_OFFSET);
+    }
+
+    #[cfg(feature = "colors")]
+    set_color_code(RESET);
+
+    #[cfg(feature = "semihosting")]
+    semihosting::process::abort();
+
+    #[cfg(not(feature = "semihosting"))]
+    halt();
+}
+
+#[cfg(all(feature = "exception-handler", target_arch = "xtensa"))]
+#[no_mangle]
+#[link_section = ".rwtext"]
+unsafe fn __user_exception(cause: arch::ExceptionCause, context: arch::Context) {
+    pre_backtrace();
+
+    #[cfg(feature = "colors")]
+    set_color_code(RED);
+
+    // Unfortunately, a different formatter string is used
+    #[cfg(not(feature = "defmt"))]
+    esp_println::println!("\n\nException occurred '{}'", cause);
+
+    #[cfg(feature = "defmt")]
+    defmt::error!("\n\nException occurred '{}'", cause);
+
+    println!("{:?}", context);
+
+    let backtrace = crate::arch::backtrace_internal(context.A1, 0);
+    for e in backtrace {
+        if let Some(addr) = e {
+            println!("0x{:x}", addr);
+        }
+    }
+    println!("");
+    println!("");
+    println!("");
+
+    #[cfg(feature = "colors")]
+    set_color_code(RESET);
+
+    #[cfg(feature = "semihosting")]
+    semihosting::process::abort();
+
+    #[cfg(not(feature = "semihosting"))]
+    halt();
+}
+
+#[cfg(all(feature = "exception-handler", target_arch = "riscv32"))]
+#[export_name = "ExceptionHandler"]
+fn exception_handler(context: &arch::TrapFrame) -> ! {
+    pre_backtrace();
+
+    let mepc = context.pc;
+    let code = context.mcause & 0xff;
+    let mtval = context.mtval;
+
+    #[cfg(feature = "colors")]
+    set_color_code(RED);
+
+    if code == 14 {
+        println!("");
+        println!(
+            "Stack overflow detected at 0x{:x} called by 0x{:x}",
+            mepc, context.ra
+        );
+        println!("");
+    } else {
+        let code = match code {
+            0 => "Instruction address misaligned",
+            1 => "Instruction access fault",
+            2 => "Illegal instruction",
+            3 => "Breakpoint",
+            4 => "Load address misaligned",
+            5 => "Load access fault",
+            6 => "Store/AMO address misaligned",
+            7 => "Store/AMO access fault",
+            8 => "Environment call from U-mode",
+            9 => "Environment call from S-mode",
+            10 => "Reserved",
+            11 => "Environment call from M-mode",
+            12 => "Instruction page fault",
+            13 => "Load page fault",
+            14 => "Reserved",
+            15 => "Store/AMO page fault",
+            _ => "UNKNOWN",
+        };
+
+        println!(
+            "Exception '{}' mepc=0x{:08x}, mtval=0x{:08x}",
+            code, mepc, mtval
+        );
+        #[cfg(not(feature = "defmt"))]
+        println!("{:x?}", context);
+
+        #[cfg(feature = "defmt")]
+        println!("{:?}", context);
+
+        let backtrace = crate::arch::backtrace_internal(context.s0 as u32, 0);
+        if backtrace.iter().filter(|e| e.is_some()).count() == 0 {
+            println!("No backtrace available - make sure to force frame-pointers. (see https://crates.io/crates/esp-backtrace)");
+        }
+        for addr in backtrace.into_iter().flatten() {
+            #[cfg(all(feature = "colors", feature = "println"))]
+            println!("{}0x{:x}", RED, addr - crate::arch::RA_OFFSET);
+
+            #[cfg(not(all(feature = "colors", feature = "println")))]
+            println!("0x{:x}", addr - crate::arch::RA_OFFSET);
+        }
+    }
+
+    println!("");
+    println!("");
+    println!("");
+
+    #[cfg(feature = "colors")]
+    set_color_code(RESET);
+
+    #[cfg(feature = "semihosting")]
+    semihosting::process::abort();
+
+    #[cfg(not(feature = "semihosting"))]
+    halt();
+}
+
+// Ensure that the address is in DRAM and that it is 16-byte aligned.
+//
+// Based loosely on the `esp_stack_ptr_in_dram` function from
+// `components/esp_hw_support/include/esp_memory_utils.h` in ESP-IDF.
+//
+// Address ranges can be found in `components/soc/$CHIP/include/soc/soc.h` as
+// `SOC_DRAM_LOW` and `SOC_DRAM_HIGH`.
+fn is_valid_ram_address(address: u32) -> bool {
+    if (address & 0xF) != 0 {
+        return false;
+    }
+
+    #[cfg(feature = "esp32")]
+    if !(0x3FFA_E000..=0x4000_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32c2")]
+    if !(0x3FCA_0000..=0x3FCE_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32c3")]
+    if !(0x3FC8_0000..=0x3FCE_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32c6")]
+    if !(0x4080_0000..=0x4088_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32h2")]
+    if !(0x4080_0000..=0x4085_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32p4")]
+    if !(0x4FF0_0000..=0x4FFC_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32s2")]
+    if !(0x3FFB_0000..=0x4000_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32s3")]
+    if !(0x3FC8_8000..=0x3FD0_0000).contains(&address) {
+        return false;
+    }
+
+    true
+}
+
+#[cfg(all(
+    any(
+        not(any(feature = "esp32", feature = "esp32p4", feature = "esp32s3")),
+        not(feature = "halt-cores")
+    ),
+    not(feature = "custom-halt")
+))]
+#[allow(unused)]
+fn halt() -> ! {
+    loop {
+        continue;
+    }
+}
+
+#[cfg(feature = "custom-halt")]
+fn halt() -> ! {
+    extern "Rust" {
+        fn custom_halt() -> !;
+    }
+    unsafe { custom_halt() }
+}
+
+// TODO: Enable `halt` function for `esp32p4` feature once implemented
+#[cfg(all(any(feature = "esp32", feature = "esp32s3"), feature = "halt-cores"))]
+#[allow(unused)]
+fn halt() -> ! {
+    #[cfg(feature = "esp32")]
+    mod registers {
+        pub(crate) const OPTIONS0: u32 = 0x3ff48000;
+        pub(crate) const SW_CPU_STALL: u32 = 0x3ff480ac;
+    }
+
+    #[cfg(feature = "esp32p4")]
+    mod registers {
+        pub(crate) const SW_CPU_STALL: u32 = 0x50115200;
+    }
+
+    #[cfg(feature = "esp32s3")]
+    mod registers {
+        pub(crate) const OPTIONS0: u32 = 0x60008000;
+        pub(crate) const SW_CPU_STALL: u32 = 0x600080bc;
+    }
+
+    let sw_cpu_stall = registers::SW_CPU_STALL as *mut u32;
+
+    #[cfg(feature = "esp32p4")]
+    unsafe {}
+
+    #[cfg(not(feature = "esp32p4"))]
+    unsafe {
+        // We need to write the value "0x86" to stall a particular core. The write
+        // location is split into two separate bit fields named "c0" and "c1", and the
+        // two fields are located in different registers. Each core has its own pair of
+        // "c0" and "c1" bit fields.
+
+        let options0 = registers::OPTIONS0 as *mut u32;
+
+        options0.write_volatile(options0.read_volatile() & !(0b1111) | 0b1010);
+
+        sw_cpu_stall.write_volatile(
+            sw_cpu_stall.read_volatile() & !(0b111111 << 20) & !(0b111111 << 26)
+                | (0x21 << 20)
+                | (0x21 << 26),
+        );
+    }
+
+    loop {}
+}
+
+#[cfg(not(feature = "custom-pre-backtrace"))]
+#[allow(unused)]
+fn pre_backtrace() {}
+
+#[cfg(feature = "custom-pre-backtrace")]
+fn pre_backtrace() {
+    extern "Rust" {
+        fn custom_pre_backtrace();
+    }
+    unsafe { custom_pre_backtrace() }
+}

esp-backtrace/src/riscv.rs

@@ -0,0 +1,219 @@
+use core::arch::asm;
+
+use crate::MAX_BACKTRACE_ADDRESSES;
+
+// subtract 4 from the return address
+// the return address is the address following the JALR
+// we get better results (especially if the caller was the last instruction in
+// the calling function) if we report the address of the JALR itself
+// even if it was a C.JALR we should get good results using RA - 4
+#[allow(unused)]
+pub(super) const RA_OFFSET: usize = 4;
+
+/// Registers saved in trap handler
+#[doc(hidden)]
+#[derive(Default, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(C)]
+#[cfg(feature = "exception-handler")]
+pub(crate) struct TrapFrame {
+    /// Return address, stores the address to return to after a function call or
+    /// interrupt.
+    pub ra: usize,
+    /// Temporary register t0, used for intermediate values.
+    pub t0: usize,
+    /// Temporary register t1, used for intermediate values.
+    pub t1: usize,
+    /// Temporary register t2, used for intermediate values.
+    pub t2: usize,
+    /// Temporary register t3, used for intermediate values.
+    pub t3: usize,
+    /// Temporary register t4, used for intermediate values.
+    pub t4: usize,
+    /// Temporary register t5, used for intermediate values.
+    pub t5: usize,
+    /// Temporary register t6, used for intermediate values.
+    pub t6: usize,
+    /// Argument register a0, typically used to pass the first argument to a
+    /// function.
+    pub a0: usize,
+    /// Argument register a1, typically used to pass the second argument to a
+    /// function.
+    pub a1: usize,
+    /// Argument register a2, typically used to pass the third argument to a
+    /// function.
+    pub a2: usize,
+    /// Argument register a3, typically used to pass the fourth argument to a
+    /// function.
+    pub a3: usize,
+    /// Argument register a4, typically used to pass the fifth argument to a
+    /// function.
+    pub a4: usize,
+    /// Argument register a5, typically used to pass the sixth argument to a
+    /// function.
+    pub a5: usize,
+    /// Argument register a6, typically used to pass the seventh argument to a
+    /// function.
+    pub a6: usize,
+    /// Argument register a7, typically used to pass the eighth argument to a
+    /// function.
+    pub a7: usize,
+    /// Saved register s0, used to hold values across function calls.
+    pub s0: usize,
+    /// Saved register s1, used to hold values across function calls.
+    pub s1: usize,
+    /// Saved register s2, used to hold values across function calls.
+    pub s2: usize,
+    /// Saved register s3, used to hold values across function calls.
+    pub s3: usize,
+    /// Saved register s4, used to hold values across function calls.
+    pub s4: usize,
+    /// Saved register s5, used to hold values across function calls.
+    pub s5: usize,
+    /// Saved register s6, used to hold values across function calls.
+    pub s6: usize,
+    /// Saved register s7, used to hold values across function calls.
+    pub s7: usize,
+    /// Saved register s8, used to hold values across function calls.
+    pub s8: usize,
+    /// Saved register s9, used to hold values across function calls.
+    pub s9: usize,
+    /// Saved register s10, used to hold values across function calls.
+    pub s10: usize,
+    /// Saved register s11, used to hold values across function calls.
+    pub s11: usize,
+    /// Global pointer register, holds the address of the global data area.
+    pub gp: usize,
+    /// Thread pointer register, holds the address of the thread-local storage
+    /// area.
+    pub tp: usize,
+    /// Stack pointer register, holds the address of the top of the stack.
+    pub sp: usize,
+    /// Program counter, stores the address of the next instruction to be
+    /// executed.
+    pub pc: usize,
+    /// Machine status register, holds the current status of the processor,
+    /// including interrupt enable bits and privilege mode.
+    pub mstatus: usize,
+    /// Machine cause register, contains the reason for the trap (e.g.,
+    /// exception or interrupt number).
+    pub mcause: usize,
+    /// Machine trap value register, contains additional information about the
+    /// trap (e.g., faulting address).
+    pub mtval: usize,
+}
+
+#[cfg(feature = "exception-handler")]
+impl core::fmt::Debug for TrapFrame {
+    fn fmt(&self, fmt: &mut core::fmt::Formatter<'_>) -> Result<(), core::fmt::Error> {
+        write!(
+            fmt,
+            "TrapFrame
+PC=0x{:08x}         RA/x1=0x{:08x}      SP/x2=0x{:08x}      GP/x3=0x{:08x}      TP/x4=0x{:08x}
+T0/x5=0x{:08x}      T1/x6=0x{:08x}      T2/x7=0x{:08x}      S0/FP/x8=0x{:08x}   S1/x9=0x{:08x}
+A0/x10=0x{:08x}     A1/x11=0x{:08x}     A2/x12=0x{:08x}     A3/x13=0x{:08x}     A4/x14=0x{:08x}
+A5/x15=0x{:08x}     A6/x16=0x{:08x}     A7/x17=0x{:08x}     S2/x18=0x{:08x}     S3/x19=0x{:08x}
+S4/x20=0x{:08x}     S5/x21=0x{:08x}     S6/x22=0x{:08x}     S7/x23=0x{:08x}     S8/x24=0x{:08x}
+S9/x25=0x{:08x}     S10/x26=0x{:08x}    S11/x27=0x{:08x}    T3/x28=0x{:08x}     T4/x29=0x{:08x}
+T5/x30=0x{:08x}     T6/x31=0x{:08x}
+
+MSTATUS=0x{:08x}
+MCAUSE=0x{:08x}
+MTVAL=0x{:08x}
+        ",
+            self.pc,
+            self.ra,
+            self.gp,
+            self.sp,
+            self.tp,
+            self.t0,
+            self.t1,
+            self.t2,
+            self.s0,
+            self.s1,
+            self.a0,
+            self.a1,
+            self.a2,
+            self.a3,
+            self.a4,
+            self.a5,
+            self.a6,
+            self.a7,
+            self.s2,
+            self.s3,
+            self.s4,
+            self.s5,
+            self.s6,
+            self.s7,
+            self.s8,
+            self.s9,
+            self.s10,
+            self.s11,
+            self.t3,
+            self.t4,
+            self.t5,
+            self.t6,
+            self.mstatus,
+            self.mcause,
+            self.mtval,
+        )
+    }
+}
+
+/// Get an array of backtrace addresses.
+///
+/// This needs `force-frame-pointers` enabled.
+pub fn backtrace() -> [Option<usize>; MAX_BACKTRACE_ADDRESSES] {
+    let fp = unsafe {
+        let mut _tmp: u32;
+        asm!("mv {0}, x8", out(reg) _tmp);
+        _tmp
+    };
+
+    backtrace_internal(fp, 2)
+}
+
+pub(crate) fn backtrace_internal(
+    fp: u32,
+    suppress: i32,
+) -> [Option<usize>; MAX_BACKTRACE_ADDRESSES] {
+    let mut result = [None; 10];
+    let mut index = 0;
+
+    let mut fp = fp;
+    let mut suppress = suppress;
+    let mut old_address = 0;
+    loop {
+        unsafe {
+            let address = (fp as *const u32).offset(-1).read_volatile(); // RA/PC
+            fp = (fp as *const u32).offset(-2).read_volatile(); // next FP
+
+            if old_address == address {
+                break;
+            }
+
+            old_address = address;
+
+            if address == 0 {
+                break;
+            }
+
+            if !crate::is_valid_ram_address(fp) {
+                break;
+            }
+
+            if suppress == 0 {
+                result[index] = Some(address as usize);
+                index += 1;
+
+                if index >= MAX_BACKTRACE_ADDRESSES {
+                    break;
+                }
+            } else {
+                suppress -= 1;
+            }
+        }
+    }
+
+    result
+}

esp-backtrace/src/xtensa.rs

@@ -0,0 +1,424 @@
+use core::{arch::asm, fmt::Display};
+
+use crate::MAX_BACKTRACE_ADDRESSES;
+
+// subtract 3 from the return address
+// the return address is the address following the callxN
+// we get better results (especially if the caller was the last function in the
+// calling function) if we report the address of callxN itself
+#[allow(unused)]
+pub(super) const RA_OFFSET: usize = 3;
+
+/// Exception Cause
+#[doc(hidden)]
+#[derive(Debug, Clone, Copy, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(C)]
+pub enum ExceptionCause {
+    /// Illegal Instruction
+    IllegalInstruction             = 0,
+    /// System Call (Syscall Instruction)
+    Syscall                        = 1,
+    /// Instruction Fetch Error
+    InstrFetchError                = 2,
+    /// Load Store Error
+    LoadStoreError                 = 3,
+    /// Level 1 Interrupt
+    LevelOneInterrupt              = 4,
+    /// Stack Extension Assist (movsp Instruction) For Alloca
+    Alloca                         = 5,
+    /// Integer Divide By Zero
+    DivideByZero                   = 6,
+    /// Use Of Failed Speculative Access (Not Implemented)
+    NextPCValueIllegal             = 7,
+    /// Privileged Instruction
+    PrivilegedInstruction          = 8,
+    /// Unaligned Load Or Store
+    UnalignedLoadOrStore           = 9,
+    /// Reserved
+    ExternalRegisterPrivilegeError = 10,
+    /// Reserved
+    ExclusiveError                 = 11,
+    /// Pif Data Error On Instruction Fetch (Rb-200x And Later)
+    InstrDataError                 = 12,
+    /// Pif Data Error On Load Or Store (Rb-200x And Later)
+    LoadStoreDataError             = 13,
+    /// Pif Address Error On Instruction Fetch (Rb-200x And Later)
+    InstrAddrError                 = 14,
+    /// Pif Address Error On Load Or Store (Rb-200x And Later)
+    LoadStoreAddrError             = 15,
+    /// Itlb Miss (No Itlb Entry Matches, Hw Refill Also Missed)
+    ItlbMiss                       = 16,
+    /// Itlb Multihit (Multiple Itlb Entries Match)
+    ItlbMultiHit                   = 17,
+    /// Ring Privilege Violation On Instruction Fetch
+    InstrRing                      = 18,
+    /// Size Restriction On Ifetch (Not Implemented)
+    Reserved19                     = 19,
+    /// Cache Attribute Does Not Allow Instruction Fetch
+    InstrProhibited                = 20,
+    /// Reserved
+    Reserved21                     = 21,
+    /// Reserved
+    Reserved22                     = 22,
+    /// Reserved
+    Reserved23                     = 23,
+    /// Dtlb Miss (No Dtlb Entry Matches, Hw Refill Also Missed)
+    DtlbMiss                       = 24,
+    /// Dtlb Multihit (Multiple Dtlb Entries Match)
+    DtlbMultiHit                   = 25,
+    /// Ring Privilege Violation On Load Or Store
+    LoadStoreRing                  = 26,
+    /// Size Restriction On Load/Store (Not Implemented)
+    Reserved27                     = 27,
+    /// Cache Attribute Does Not Allow Load
+    LoadProhibited                 = 28,
+    /// Cache Attribute Does Not Allow Store
+    StoreProhibited                = 29,
+    /// Reserved
+    Reserved30                     = 30,
+    /// Reserved
+    Reserved31                     = 31,
+    /// Access To Coprocessor 0 When Disabled
+    Cp0Disabled                    = 32,
+    /// Access To Coprocessor 1 When Disabled
+    Cp1Disabled                    = 33,
+    /// Access To Coprocessor 2 When Disabled
+    Cp2Disabled                    = 34,
+    /// Access To Coprocessor 3 When Disabled
+    Cp3Disabled                    = 35,
+    /// Access To Coprocessor 4 When Disabled
+    Cp4Disabled                    = 36,
+    /// Access To Coprocessor 5 When Disabled
+    Cp5Disabled                    = 37,
+    /// Access To Coprocessor 6 When Disabled
+    Cp6Disabled                    = 38,
+    /// Access To Coprocessor 7 When Disabled
+    Cp7Disabled                    = 39,
+    /// None
+    None                           = 255,
+}
+
+impl Display for ExceptionCause {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        if *self == Self::Cp0Disabled {
+            write!(f, "Cp0Disabled (Access to the floating point coprocessor is not allowed. You may want to enable the `float-save-restore` feature of the `xtensa-lx-rt` crate.)")
+        } else {
+            write!(f, "{:?}", self)
+        }
+    }
+}
+
+#[doc(hidden)]
+#[allow(non_snake_case)]
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(C)]
+pub struct Context {
+    /// Program counter, stores the address of the next instruction to be
+    /// executed.
+    pub PC: u32,
+    /// Processor status, holds various status flags for the CPU.
+    pub PS: u32,
+    /// General-purpose register A0 used for data storage and manipulation.
+    pub A0: u32,
+    /// General-purpose register A1 used for data storage and manipulation.
+    pub A1: u32,
+    /// General-purpose register A2 used for data storage and manipulation.
+    pub A2: u32,
+    /// General-purpose register A3 used for data storage and manipulation.
+    pub A3: u32,
+    /// General-purpose register A4 used for data storage and manipulation.
+    pub A4: u32,
+    /// General-purpose register A5 used for data storage and manipulation.
+    pub A5: u32,
+    /// General-purpose register A6 used for data storage and manipulation.
+    pub A6: u32,
+    /// General-purpose register A7 used for data storage and manipulation.
+    pub A7: u32,
+    /// General-purpose register A8 used for data storage and manipulation.
+    pub A8: u32,
+    /// General-purpose register A9 used for data storage and manipulation.
+    pub A9: u32,
+    /// General-purpose register A10 used for data storage and manipulation.
+    pub A10: u32,
+    /// General-purpose register A11 used for data storage and manipulation.
+    pub A11: u32,
+    /// General-purpose register A12 used for data storage and manipulation.
+    pub A12: u32,
+    /// General-purpose register A13 used for data storage and manipulation.
+    pub A13: u32,
+    /// General-purpose register A14 used for data storage and manipulation.
+    pub A14: u32,
+    /// General-purpose register A15 used for data storage and manipulation.
+    pub A15: u32,
+    /// Shift amount register, used for shift and rotate instructions.
+    pub SAR: u32,
+    /// Exception cause, indicates the reason for the last exception.
+    pub EXCCAUSE: u32,
+    /// Exception address, holds the address related to the exception.
+    pub EXCVADDR: u32,
+    /// Loop start address, used in loop instructions.
+    pub LBEG: u32,
+    /// Loop end address, used in loop instructions.
+    pub LEND: u32,
+    /// Loop counter, used to count iterations in loop instructions.
+    pub LCOUNT: u32,
+    /// Thread pointer, used for thread-local storage.
+    pub THREADPTR: u32,
+    /// Compare register, used for certain compare instructions.
+    pub SCOMPARE1: u32,
+    /// Break register, used for breakpoint-related operations.
+    pub BR: u32,
+    /// Accumulator low register, used for extended arithmetic operations.
+    pub ACCLO: u32,
+    /// Accumulator high register, used for extended arithmetic operations.
+    pub ACCHI: u32,
+    /// Additional register M0 used for special operations.
+    pub M0: u32,
+    /// Additional register M1 used for special operations.
+    pub M1: u32,
+    /// Additional register M2 used for special operations.
+    pub M2: u32,
+    /// Additional register M3 used for special operations.
+    pub M3: u32,
+    /// 64-bit floating-point register (low part), available if the
+    /// `print-float-registers` feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F64R_LO: u32,
+    /// 64-bit floating-point register (high part), available if the
+    /// `print-float-registers` feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F64R_HI: u32,
+    /// Floating-point status register, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F64S: u32,
+    /// Floating-point control register, available if the
+    /// `print-float-registers` feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub FCR: u32,
+    /// Floating-point status register, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub FSR: u32,
+    /// Floating-point register F0, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F0: u32,
+    /// Floating-point register F1, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F1: u32,
+    /// Floating-point register F2, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F2: u32,
+    /// Floating-point register F3, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F3: u32,
+    /// Floating-point register F4, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F4: u32,
+    /// Floating-point register F5, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F5: u32,
+    /// Floating-point register F6, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F6: u32,
+    /// Floating-point register F7, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F7: u32,
+    /// Floating-point register F8, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F8: u32,
+    /// Floating-point register F9, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F9: u32,
+    /// Floating-point register F10, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F10: u32,
+    /// Floating-point register F11, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F11: u32,
+    /// Floating-point register F12, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F12: u32,
+    /// Floating-point register F13, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F13: u32,
+    /// Floating-point register F14, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F14: u32,
+    /// Floating-point register F15, available if the `print-float-registers`
+    /// feature is enabled.
+    #[cfg(feature = "print-float-registers")]
+    pub F15: u32,
+}
+
+impl core::fmt::Debug for Context {
+    fn fmt(&self, fmt: &mut core::fmt::Formatter<'_>) -> Result<(), core::fmt::Error> {
+        write!(
+            fmt,
+            "Context
+PC=0x{:08x}       PS=0x{:08x}
+A0=0x{:08x}       A1=0x{:08x}       A2=0x{:08x}       A3=0x{:08x}       A4=0x{:08x}
+A5=0x{:08x}       A6=0x{:08x}       A7=0x{:08x}       A8=0x{:08x}       A9=0x{:08x}
+A10=0x{:08x}      A11=0x{:08x}      A12=0x{:08x}      A13=0x{:08x}      A14=0x{:08x}
+A15=0x{:08x}
+SAR={:08x}
+EXCCAUSE=0x{:08x} EXCVADDR=0x{:08x}
+LBEG=0x{:08x}     LEND=0x{:08x}     LCOUNT=0x{:08x}
+THREADPTR=0x{:08x}
+SCOMPARE1=0x{:08x}
+BR=0x{:08x}
+ACCLO=0x{:08x}    ACCHI=0x{:08x}
+M0=0x{:08x}       M1=0x{:08x}       M2=0x{:08x}       M3=0x{:08x}
+",
+            self.PC,
+            self.PS,
+            self.A0,
+            self.A1,
+            self.A2,
+            self.A3,
+            self.A4,
+            self.A5,
+            self.A6,
+            self.A7,
+            self.A8,
+            self.A9,
+            self.A10,
+            self.A11,
+            self.A12,
+            self.A13,
+            self.A14,
+            self.A15,
+            self.SAR,
+            self.EXCCAUSE,
+            self.EXCVADDR,
+            self.LBEG,
+            self.LEND,
+            self.LCOUNT,
+            self.THREADPTR,
+            self.SCOMPARE1,
+            self.BR,
+            self.ACCLO,
+            self.ACCHI,
+            self.M0,
+            self.M1,
+            self.M2,
+            self.M3,
+        )?;
+        #[cfg(feature = "print-float-registers")]
+        write!(
+            fmt,
+            "F64R_LO=0x{:08x}  F64R_HI=0x{:08x}  F64S=0x{:08x}
+FCR=0x{:08x}      FSR=0x{:08x}
+F0=0x{:08x}       F1=0x{:08x}       F2=0x{:08x}       F3=0x{:08x}       F4=0x{:08x}
+F5=0x{:08x}       F6=0x{:08x}       F7=0x{:08x}       F8=0x{:08x}       F9=0x{:08x}
+F10=0x{:08x}      F11=0x{:08x}      F12=0x{:08x}      F13=0x{:08x}      F14=0x{:08x}
+F15=0x{:08x}",
+            self.F64R_LO,
+            self.F64R_HI,
+            self.F64S,
+            self.FCR,
+            self.FSR,
+            self.F0,
+            self.F1,
+            self.F2,
+            self.F3,
+            self.F4,
+            self.F5,
+            self.F6,
+            self.F7,
+            self.F8,
+            self.F9,
+            self.F10,
+            self.F11,
+            self.F12,
+            self.F13,
+            self.F14,
+            self.F15,
+        )?;
+
+        Ok(())
+    }
+}
+
+/// Get an array of backtrace addresses.
+pub fn backtrace() -> [Option<usize>; MAX_BACKTRACE_ADDRESSES] {
+    let sp = unsafe {
+        let mut _tmp: u32;
+        asm!("mov {0}, a1", out(reg) _tmp);
+        _tmp
+    };
+
+    backtrace_internal(sp, 1)
+}
+
+pub(crate) fn sanitize_address(address: u32) -> u32 {
+    (address & 0x3fff_ffff) | 0x4000_0000
+}
+
+pub(crate) fn backtrace_internal(
+    sp: u32,
+    suppress: i32,
+) -> [Option<usize>; MAX_BACKTRACE_ADDRESSES] {
+    let mut result = [None; 10];
+    let mut index = 0;
+
+    let mut fp = sp;
+    let mut suppress = suppress;
+    let mut old_address = 0;
+
+    loop {
+        unsafe {
+            let address = sanitize_address((fp as *const u32).offset(-4).read_volatile()); // RA/PC
+            fp = (fp as *const u32).offset(-3).read_volatile(); // next FP
+
+            if old_address == address {
+                break;
+            }
+
+            old_address = address;
+
+            // the address is 0 but we sanitized the address - then 0 becomes 0x40000000
+            if address == 0x40000000 {
+                break;
+            }
+
+            if !crate::is_valid_ram_address(fp) {
+                break;
+            }
+
+            if fp == 0 {
+                break;
+            }
+
+            if suppress == 0 {
+                result[index] = Some(address as usize);
+                index += 1;
+
+                if index >= MAX_BACKTRACE_ADDRESSES {
+                    break;
+                }
+            } else {
+                suppress -= 1;
+            }
+        }
+    }
+
+    result
+}

esp-build/CHANGELOG.md

@@ -2,21 +2,23 @@
 
 All notable changes to this project will be documented in this file.
 
-The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
 
 ### Added
 
-- Add the `ulp-riscv-hal` package (#840)
+### Fixed
 
 ### Changed
 
-- Renamed to `esp-ulp-riscv-hal` (#916)
-
-### Fixed
+- Use `panic` instead of `process::exit` in esp-build (#2402 )
 
 ### Removed
 
-[Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp-ulp-riscv-hal
+## [0.1.0] - 2024-04-17
+
+- Initial release
+
+[Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp-build?since=2024-04-17

esp-build/Cargo.toml

@@ -0,0 +1,16 @@
+[package]
+name         = "esp-build"
+version      = "0.1.0"
+edition      = "2021"
+rust-version = "1.60.0"
+description  = "Build utilities for esp-hal"
+repository   = "https://github.com/esp-rs/esp-hal"
+license      = "MIT OR Apache-2.0"
+
+[lib]
+proc-macro = true
+
+[dependencies]
+quote     = "1.0.37"
+syn       = { version = "2.0.79", features = ["fold", "full"] }
+termcolor = "1.4.1"

esp-build/README.md

@@ -0,0 +1,33 @@
+# esp-build
+
+[![Crates.io](https://img.shields.io/crates/v/esp-build?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-build)
+[![docs.rs](https://img.shields.io/docsrs/esp-build?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-build)
+![MSRV](https://img.shields.io/badge/MSRV-1.60-blue?labelColor=1C2C2E&style=flat-square)
+![Crates.io](https://img.shields.io/crates/l/esp-build?labelColor=1C2C2E&style=flat-square)
+[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
+
+Build utilities for use with `esp-hal` and other related packages, intended for use in [build scripts]. This package is still quite minimal, but provides:
+
+[build scripts]: https://doc.rust-lang.org/cargo/reference/build-scripts.html
+
+## [Documentation](https://docs.rs/crate/esp-build)
+
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.60 and up. It _might_
+compile with older versions but that may change in any new patch release.
+
+## License
+
+Licensed under either of:
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
+the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
+any additional terms or conditions.

esp-build/src/lib.rs

@@ -0,0 +1,229 @@
+//! Build utilities for esp-hal.
+
+#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
+
+use std::io::Write as _;
+
+use proc_macro::TokenStream;
+use quote::ToTokens;
+use syn::{parse_macro_input, punctuated::Punctuated, LitStr, Token};
+use termcolor::{Color, ColorChoice, ColorSpec, StandardStream, WriteColor};
+
+/// Print a build error and terminate the process.
+///
+/// It should be noted that the error will be printed BEFORE the main function
+/// is called, and as such this should NOT be thought analogous to `println!` or
+/// similar utilities.
+///
+/// ## Example
+///
+/// ```rust
+/// esp_build::error! {"
+/// ERROR: something really bad has happened!
+/// "}
+/// // Process exits with exit code 1
+/// ```
+#[proc_macro]
+pub fn error(input: TokenStream) -> TokenStream {
+    do_alert(Color::Red, input);
+    panic!("Build failed");
+}
+
+/// Print a build warning.
+///
+/// It should be noted that the warning will be printed BEFORE the main function
+/// is called, and as such this should NOT be thought analogous to `println!` or
+/// similar utilities.
+///
+/// ## Example
+///
+/// ```rust
+/// esp_build::warning! {"
+/// WARNING: something unpleasant has happened!
+/// "};
+/// ```
+#[proc_macro]
+pub fn warning(input: TokenStream) -> TokenStream {
+    do_alert(Color::Yellow, input)
+}
+
+/// Given some features, assert that **at most** one of the features is enabled.
+///
+/// ## Example
+/// ```rust
+/// assert_unique_features!("foo", "bar", "baz");
+/// ```
+#[proc_macro]
+pub fn assert_unique_features(input: TokenStream) -> TokenStream {
+    let features = parse_macro_input!(input with Punctuated<LitStr, Token![,]>::parse_terminated)
+        .into_iter()
+        .collect::<Vec<_>>();
+
+    let unique = impl_unique_features(&features, "exactly zero or one");
+
+    quote::quote! {
+        #unique
+    }
+    .into()
+}
+
+/// Given some features, assert that **at least** one of the features is
+/// enabled.
+///
+/// ## Example
+/// ```rust
+/// assert_used_features!("foo", "bar", "baz");
+/// ```
+#[proc_macro]
+pub fn assert_used_features(input: TokenStream) -> TokenStream {
+    let features = parse_macro_input!(input with Punctuated<LitStr, Token![,]>::parse_terminated)
+        .into_iter()
+        .collect::<Vec<_>>();
+
+    let used = impl_used_features(&features, "at least one");
+
+    quote::quote! {
+        #used
+    }
+    .into()
+}
+
+/// Given some features, assert that **exactly** one of the features is enabled.
+///
+/// ## Example
+/// ```rust
+/// assert_unique_used_features!("foo", "bar", "baz");
+/// ```
+#[proc_macro]
+pub fn assert_unique_used_features(input: TokenStream) -> TokenStream {
+    let features = parse_macro_input!(input with Punctuated<LitStr, Token![,]>::parse_terminated)
+        .into_iter()
+        .collect::<Vec<_>>();
+
+    let unique = impl_unique_features(&features, "exactly one");
+    let used = impl_used_features(&features, "exactly one");
+
+    quote::quote! {
+        #unique
+        #used
+    }
+    .into()
+}
+
+// ----------------------------------------------------------------------------
+// Helper Functions
+
+fn impl_unique_features(features: &[LitStr], expectation: &str) -> impl ToTokens {
+    let pairs = unique_pairs(features);
+    let unique_cfgs = pairs
+        .iter()
+        .map(|(a, b)| quote::quote! { all(feature = #a, feature = #b) });
+
+    let message = format!(
+        r#"
+ERROR: expected {expectation} enabled feature from feature group:
+  {:?}
+"#,
+        features.iter().map(|lit| lit.value()).collect::<Vec<_>>(),
+    );
+
+    quote::quote! {
+        #[cfg(any(#(#unique_cfgs),*))]
+        ::esp_build::error! { #message }
+    }
+}
+
+fn impl_used_features(features: &[LitStr], expectation: &str) -> impl ToTokens {
+    let message = format!(
+        r#"
+ERROR: expected {expectation} enabled feature from feature group:
+  {:?}
+    "#,
+        features.iter().map(|lit| lit.value()).collect::<Vec<_>>()
+    );
+
+    quote::quote! {
+        #[cfg(not(any(#(feature = #features),*)))]
+        ::esp_build::error! { #message }
+    }
+}
+
+// Adapted from:
+// https://github.com/dtolnay/build-alert/blob/49d060e/src/lib.rs#L54-L93
+fn do_alert(color: Color, input: TokenStream) -> TokenStream {
+    let message = parse_macro_input!(input as LitStr).value();
+
+    let stderr = &mut StandardStream::stderr(ColorChoice::Auto);
+    let color_spec = ColorSpec::new().set_fg(Some(color)).clone();
+
+    let mut has_nonspace = false;
+
+    for mut line in message.lines() {
+        if !has_nonspace {
+            let (maybe_heading, rest) = split_heading(line);
+
+            if let Some(heading) = maybe_heading {
+                stderr.set_color(color_spec.clone().set_bold(true)).ok();
+                write!(stderr, "\n{}", heading).ok();
+                has_nonspace = true;
+            }
+
+            line = rest;
+        }
+
+        if line.is_empty() {
+            writeln!(stderr).ok();
+        } else {
+            stderr.set_color(&color_spec).ok();
+            writeln!(stderr, "{}", line).ok();
+
+            has_nonspace = has_nonspace || line.contains(|ch: char| ch != ' ');
+        }
+    }
+
+    stderr.reset().ok();
+    writeln!(stderr).ok();
+
+    TokenStream::new()
+}
+
+// Adapted from:
+// https://github.com/dtolnay/build-alert/blob/49d060e/src/lib.rs#L95-L114
+fn split_heading(s: &str) -> (Option<&str>, &str) {
+    let mut end = 0;
+    while end < s.len() && s[end..].starts_with(|ch: char| ch.is_ascii_uppercase()) {
+        end += 1;
+    }
+
+    if end >= 3 && (end == s.len() || s[end..].starts_with(':')) {
+        let (heading, rest) = s.split_at(end);
+        (Some(heading), rest)
+    } else {
+        (None, s)
+    }
+}
+
+fn unique_pairs(features: &[LitStr]) -> Vec<(&LitStr, &LitStr)> {
+    let mut pairs = Vec::new();
+
+    let mut i = 0;
+    let mut j = 0;
+
+    while i < features.len() {
+        let a = &features[i];
+        let b = &features[j];
+
+        if a.value() != b.value() {
+            pairs.push((a, b));
+        }
+
+        j += 1;
+
+        if j >= features.len() {
+            i += 1;
+            j = i;
+        }
+    }
+
+    pairs
+}

esp-config/CHANGELOG.md

@@ -0,0 +1,32 @@
+# Changelog
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/),
+and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+
+## [Unreleased]
+
+### Added
+
+### Fixed
+
+- Users no longer have to manually import `esp_config_int_parse`. (#2630)
+
+### Changed
+
+- Crate prefixes and configuration keys are now separated by `_CONFIG_` (#2848)
+
+### Removed
+
+## 0.2.0 - 2024-11-20
+
+### Added
+
+- Add configuration validation (#2475)
+
+## 0.1.0 - 2024-10-10
+
+- Initial release
+
+[Unreleased]: https://github.com/esp-rs/esp-hal/commits/main/esp-config?since=2024-11-20

esp-config/Cargo.toml

@@ -0,0 +1,18 @@
+[package]
+name         = "esp-config"
+version      = "0.2.0"
+edition      = "2021"
+rust-version = "1.79.0"
+description  = "Configure projects using esp-hal and related packages"
+repository   = "https://github.com/esp-rs/esp-hal"
+license      = "MIT OR Apache-2.0"
+
+[dependencies]
+document-features = "0.2.10"
+
+[dev-dependencies]
+temp-env = "0.3.6"
+
+[features]
+## Enable the generation and parsing of a config
+build = []

esp-config/README.md

@@ -0,0 +1,65 @@
+# esp-config
+
+[![Crates.io](https://img.shields.io/crates/v/esp-config?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-config)
+[![docs.rs](https://img.shields.io/docsrs/esp-config?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-config)
+![MSRV](https://img.shields.io/badge/MSRV-1.79-blue?labelColor=1C2C2E&style=flat-square)
+![Crates.io](https://img.shields.io/crates/l/esp-config?labelColor=1C2C2E&style=flat-square)
+[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
+
+## [Documentation](https://docs.rs/crate/esp-config)
+
+## Usage
+
+`esp-config` takes a prefix (usually the crate name) and a set of configuration keys and default values to produce a configuration system that supports:
+
+- Emitting rustc cfg's for boolean keys
+- Emitting environment variables for numbers
+  - Along with decimal parsing, it supports Hex, Octal and Binary with the respective `0x`, `0o` and `0b` prefixes.
+- Emitting environment variables string values
+
+### Viewing the configuration
+
+The possible configuration values are output as a markdown table in the crates `OUT_DIR` with the format `{prefix}_config_table.md`, this can then be included into the crates top level documentation. Here is an example of the output:
+
+
+| Name | Description | Default value |
+|------|-------------|---------------|
+|**ESP_HAL_PLACE_SPI_DRIVER_IN_RAM**|Places the SPI driver in RAM for better performance|false|
+
+### Setting configuration options
+
+For any available configuration option, the environment variable or cfg is _always_ set based on the default value specified in the table. Users can override this by setting environment variables locally in their shell _or_ the preferred option is to utilize cargo's [`env` section](https://doc.rust-lang.org/cargo/reference/config.html#env).
+
+It's important to note that due to a [bug in cargo](https://github.com/rust-lang/cargo/issues/10358), any modifications to the environment, local or otherwise will only get picked up on a full clean build of the project.
+
+To see the final selected configuration another table is output to the `OUT_DIR` with the format `{prefix}_selected_config.md`.
+
+### Capturing configuration values in the downstream crate
+
+For all supported data types, there are helper macros that emit `const` code for parsing the configuration values.
+
+- Numbers - `esp_config_int!(integer_type, "ENV")`
+- Strings - `esp_config_str!("ENV")`
+- Bool - `esp_config_bool!("ENV")`
+
+In addition to environment variables, for boolean types rust `cfg`'s are emitted in snake case _without_ the prefix.
+
+## Minimum Supported Rust Version (MSRV)
+
+This crate is guaranteed to compile on stable Rust 1.79 and up. It _might_
+compile with older versions but that may change in any new patch release.
+
+## License
+
+Licensed under either of:
+
+- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+### Contribution
+
+Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
+the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
+any additional terms or conditions.

esp-config/src/generate.rs

@@ -0,0 +1,699 @@
+use std::{
+    collections::HashMap,
+    env,
+    fmt::{self, Write as _},
+    fs,
+    ops::Range,
+    path::PathBuf,
+};
+
+const DOC_TABLE_HEADER: &str = r#"
+| Name | Description | Default value |
+|------|-------------|---------------|
+"#;
+
+const SELECTED_TABLE_HEADER: &str = r#"
+| Name | Selected value |
+|------|----------------|
+"#;
+
+/// Configuration errors.
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum Error {
+    /// Parse errors.
+    Parse(String),
+    /// Validation errors.
+    Validation(String),
+}
+
+impl Error {
+    /// Convenience function for creating parse errors.
+    pub fn parse<S>(message: S) -> Self
+    where
+        S: Into<String>,
+    {
+        Self::Parse(message.into())
+    }
+
+    /// Convenience function for creating validation errors.
+    pub fn validation<S>(message: S) -> Self
+    where
+        S: Into<String>,
+    {
+        Self::Validation(message.into())
+    }
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Error::Parse(message) => write!(f, "{message}"),
+            Error::Validation(message) => write!(f, "{message}"),
+        }
+    }
+}
+
+/// Supported configuration value types.
+#[derive(Debug, Clone, PartialEq, Eq)]
+pub enum Value {
+    /// Booleans.
+    Bool(bool),
+    /// Integers.
+    Integer(i128),
+    /// Strings.
+    String(String),
+}
+
+// TODO: Do we want to handle negative values for non-decimal values?
+impl Value {
+    fn parse_in_place(&mut self, s: &str) -> Result<(), Error> {
+        *self = match self {
+            Value::Bool(_) => match s {
+                "true" => Value::Bool(true),
+                "false" => Value::Bool(false),
+                _ => {
+                    return Err(Error::parse(format!(
+                        "Expected 'true' or 'false', found: '{s}'"
+                    )))
+                }
+            },
+            Value::Integer(_) => {
+                let inner = match s.as_bytes() {
+                    [b'0', b'x', ..] => i128::from_str_radix(&s[2..], 16),
+                    [b'0', b'o', ..] => i128::from_str_radix(&s[2..], 8),
+                    [b'0', b'b', ..] => i128::from_str_radix(&s[2..], 2),
+                    _ => i128::from_str_radix(&s, 10),
+                }
+                .map_err(|_| Error::parse(format!("Expected valid intger value, found: '{s}'")))?;
+
+                Value::Integer(inner)
+            }
+            Value::String(_) => Value::String(s.into()),
+        };
+
+        Ok(())
+    }
+
+    /// Convert the value to a [bool].
+    pub fn as_bool(&self) -> bool {
+        match self {
+            Value::Bool(value) => *value,
+            _ => panic!("attempted to convert non-bool value to a bool"),
+        }
+    }
+
+    /// Convert the value to an [i128].
+    pub fn as_integer(&self) -> i128 {
+        match self {
+            Value::Integer(value) => *value,
+            _ => panic!("attempted to convert non-integer value to an integer"),
+        }
+    }
+
+    /// Convert the value to a [String].
+    pub fn as_string(&self) -> String {
+        match self {
+            Value::String(value) => value.to_owned(),
+            _ => panic!("attempted to convert non-string value to a string"),
+        }
+    }
+
+    /// Is the value a bool?
+    pub fn is_bool(&self) -> bool {
+        matches!(self, Value::Bool(_))
+    }
+
+    /// Is the value an integer?
+    pub fn is_integer(&self) -> bool {
+        matches!(self, Value::Integer(_))
+    }
+
+    /// Is the value a string?
+    pub fn is_string(&self) -> bool {
+        matches!(self, Value::String(_))
+    }
+}
+
+impl fmt::Display for Value {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Value::Bool(b) => write!(f, "{b}"),
+            Value::Integer(i) => write!(f, "{i}"),
+            Value::String(s) => write!(f, "{s}"),
+        }
+    }
+}
+
+/// Configuration value validation functions.
+pub enum Validator {
+    /// Only allow negative integers, i.e. any values less than 0.
+    NegativeInteger,
+    /// Only allow non-negative integers, i.e. any values greater than or equal
+    /// to 0.
+    NonNegativeInteger,
+    /// Only allow positive integers, i.e. any values greater than to 0.
+    PositiveInteger,
+    /// Ensure that an integer value falls within the specified range.
+    IntegerInRange(Range<i128>),
+    /// A custom validation function to run against any supported value type.
+    Custom(Box<dyn Fn(&Value) -> Result<(), Error>>),
+}
+
+impl Validator {
+    fn validate(&self, value: &Value) -> Result<(), Error> {
+        match self {
+            Validator::NegativeInteger => negative_integer(value)?,
+            Validator::NonNegativeInteger => non_negative_integer(value)?,
+            Validator::PositiveInteger => positive_integer(value)?,
+            Validator::IntegerInRange(range) => integer_in_range(range, value)?,
+            Validator::Custom(validator_fn) => validator_fn(value)?,
+        }
+
+        Ok(())
+    }
+}
+
+fn negative_integer(value: &Value) -> Result<(), Error> {
+    if !value.is_integer() {
+        return Err(Error::validation(
+            "Validator::NegativeInteger can only be used with integer values",
+        ));
+    } else if value.as_integer() >= 0 {
+        return Err(Error::validation(format!(
+            "Expected negative integer, found '{}'",
+            value.as_integer()
+        )));
+    }
+
+    Ok(())
+}
+
+fn non_negative_integer(value: &Value) -> Result<(), Error> {
+    if !value.is_integer() {
+        return Err(Error::validation(
+            "Validator::NonNegativeInteger can only be used with integer values",
+        ));
+    } else if value.as_integer() < 0 {
+        return Err(Error::validation(format!(
+            "Expected non-negative integer, found '{}'",
+            value.as_integer()
+        )));
+    }
+
+    Ok(())
+}
+
+fn positive_integer(value: &Value) -> Result<(), Error> {
+    if !value.is_integer() {
+        return Err(Error::validation(
+            "Validator::PositiveInteger can only be used with integer values",
+        ));
+    } else if value.as_integer() <= 0 {
+        return Err(Error::validation(format!(
+            "Expected positive integer, found '{}'",
+            value.as_integer()
+        )));
+    }
+
+    Ok(())
+}
+
+fn integer_in_range(range: &Range<i128>, value: &Value) -> Result<(), Error> {
+    if !value.is_integer() || !range.contains(&value.as_integer()) {
+        Err(Error::validation(format!(
+            "Value '{}' does not fall within range '{:?}'",
+            value, range
+        )))
+    } else {
+        Ok(())
+    }
+}
+
+/// Generate and parse config from a prefix, and an array tuples containing the
+/// name, description, default value, and an optional validator.
+///
+/// This function will parse any `SCREAMING_SNAKE_CASE` environment variables
+/// that match the given prefix. It will then attempt to parse the [`Value`] and
+/// run any validators which have been specified.
+///
+/// Once the config has been parsed, this function will emit `snake_case` cfg's
+/// _without_ the prefix which can be used in the dependant crate. After that,
+/// it will create a markdown table in the `OUT_DIR` under the name
+/// `{prefix}_config_table.md` where prefix has also been converted to
+/// `snake_case`. This can be included in crate documentation to outline the
+/// available configuration options for the crate.
+///
+/// Passing a value of true for the `emit_md_tables` argument will create and
+/// write markdown files of the available configuration and selected
+/// configuration which can be included in documentation.
+///
+/// Unknown keys with the supplied prefix will cause this function to panic.
+pub fn generate_config(
+    crate_name: &str,
+    config: &[(&str, &str, Value, Option<Validator>)],
+    emit_md_tables: bool,
+) -> HashMap<String, Value> {
+    // Only rebuild if `build.rs` changed. Otherwise, Cargo will rebuild if any
+    // other file changed.
+    println!("cargo:rerun-if-changed=build.rs");
+
+    #[cfg(not(test))]
+    env_change_work_around();
+
+    let mut doc_table = String::from(DOC_TABLE_HEADER);
+    let mut selected_config = String::from(SELECTED_TABLE_HEADER);
+
+    // Ensure that the prefix is `SCREAMING_SNAKE_CASE`:
+    let prefix = format!("{}_CONFIG_", screaming_snake_case(crate_name));
+
+    // Build a lookup table for any provided validators; we must prefix the
+    // name of the config and transform it to SCREAMING_SNAKE_CASE so that
+    // it matches the keys in the hash table produced by `create_config`.
+    let config_validators = config
+        .iter()
+        .flat_map(|(name, _description, _default, validator)| {
+            if let Some(validator) = validator {
+                let name = format!("{prefix}{}", screaming_snake_case(name));
+                Some((name, validator))
+            } else {
+                None
+            }
+        })
+        .collect::<HashMap<_, _>>();
+
+    let mut configs = create_config(&prefix, config, &mut doc_table);
+    capture_from_env(&prefix, &mut configs);
+
+    for (name, value) in configs.iter() {
+        if let Some(validator) = config_validators.get(name) {
+            validator.validate(value).unwrap();
+        }
+    }
+
+    emit_configuration(&prefix, &configs, &mut selected_config);
+
+    if emit_md_tables {
+        let file_name = snake_case(crate_name);
+        write_config_tables(&file_name, doc_table, selected_config);
+    }
+
+    configs
+}
+
+// A work-around for https://github.com/rust-lang/cargo/issues/10358
+// This can be removed when https://github.com/rust-lang/cargo/pull/14058 is merged.
+// Unlikely to work on projects in workspaces
+#[cfg(not(test))]
+fn env_change_work_around() {
+    let mut out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
+
+    // We clean out_dir by removing all trailing directories, until it ends with
+    // target
+    while !out_dir.ends_with("target") {
+        if !out_dir.pop() {
+            return; // We ran out of directories...
+        }
+    }
+    out_dir.pop();
+
+    let dotcargo = out_dir.join(".cargo/");
+    if dotcargo.exists() {
+        if dotcargo.join("config.toml").exists() {
+            println!(
+                "cargo:rerun-if-changed={}",
+                dotcargo.join("config.toml").display()
+            );
+        }
+        if dotcargo.join("config").exists() {
+            println!(
+                "cargo:rerun-if-changed={}",
+                dotcargo.join("config").display()
+            );
+        }
+    }
+}
+
+fn create_config(
+    prefix: &str,
+    config: &[(&str, &str, Value, Option<Validator>)],
+    doc_table: &mut String,
+) -> HashMap<String, Value> {
+    let mut configs = HashMap::new();
+
+    for (name, description, default, _validator) in config {
+        let name = format!("{prefix}{}", screaming_snake_case(name));
+        configs.insert(name.clone(), default.clone());
+
+        // Write documentation table line:
+        let default = default.to_string();
+        writeln!(doc_table, "|**{name}**|{description}|{default}|").unwrap();
+
+        // Rebuild if config environment variable changed:
+        println!("cargo:rerun-if-env-changed={name}");
+    }
+
+    configs
+}
+
+fn capture_from_env(prefix: &str, configs: &mut HashMap<String, Value>) {
+    let mut unknown = Vec::new();
+    let mut failed = Vec::new();
+
+    // Try and capture input from the environment:
+    for (var, value) in env::vars() {
+        if var.starts_with(prefix) {
+            let Some(cfg) = configs.get_mut(&var) else {
+                unknown.push(var);
+                continue;
+            };
+
+            if let Err(e) = cfg.parse_in_place(&value) {
+                failed.push(format!("{var}: {e}"));
+            }
+        }
+    }
+
+    if !failed.is_empty() {
+        panic!("Invalid configuration options detected: {:?}", failed);
+    }
+
+    if !unknown.is_empty() {
+        panic!("Unknown configuration options detected: {:?}", unknown);
+    }
+}
+
+fn emit_configuration(
+    prefix: &str,
+    configs: &HashMap<String, Value>,
+    selected_config: &mut String,
+) {
+    for (name, value) in configs.iter() {
+        let cfg_name = snake_case(name.trim_start_matches(prefix));
+        println!("cargo:rustc-check-cfg=cfg({cfg_name})");
+
+        if let Value::Bool(true) = value {
+            println!("cargo:rustc-cfg={cfg_name}");
+        }
+
+        let value = value.to_string();
+
+        // Values that haven't been seen will be output here with the default value:
+        println!("cargo:rustc-env={}={}", name, value);
+        writeln!(selected_config, "|**{name}**|{value}|").unwrap();
+    }
+}
+
+fn write_config_tables(prefix: &str, doc_table: String, selected_config: String) {
+    let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
+
+    let out_file = out_dir
+        .join(format!("{prefix}_config_table.md"))
+        .display()
+        .to_string();
+    fs::write(out_file, doc_table).unwrap();
+
+    let out_file = out_dir
+        .join(format!("{prefix}_selected_config.md"))
+        .display()
+        .to_string();
+    fs::write(out_file, selected_config).unwrap();
+}
+
+fn snake_case(name: &str) -> String {
+    let mut name = name.replace("-", "_");
+    name.make_ascii_lowercase();
+
+    name
+}
+
+fn screaming_snake_case(name: &str) -> String {
+    let mut name = name.replace("-", "_");
+    name.make_ascii_uppercase();
+
+    name
+}
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn value_number_formats() {
+        const INPUTS: &[&str] = &["0xAA", "0o252", "0b0000000010101010", "170"];
+        let mut v = Value::Integer(0);
+
+        for input in INPUTS {
+            v.parse_in_place(input).unwrap();
+            // no matter the input format, the output format should be decimal
+            assert_eq!(format!("{v}"), "170");
+        }
+    }
+
+    #[test]
+    fn value_bool_inputs() {
+        let mut v = Value::Bool(false);
+
+        v.parse_in_place("true").unwrap();
+        assert_eq!(format!("{v}"), "true");
+
+        v.parse_in_place("false").unwrap();
+        assert_eq!(format!("{v}"), "false");
+    }
+
+    #[test]
+    fn env_override() {
+        temp_env::with_vars(
+            [
+                ("ESP_TEST_CONFIG_NUMBER", Some("0xaa")),
+                ("ESP_TEST_CONFIG_NUMBER_SIGNED", Some("-999")),
+                ("ESP_TEST_CONFIG_STRING", Some("Hello world!")),
+                ("ESP_TEST_CONFIG_BOOL", Some("true")),
+            ],
+            || {
+                let configs = generate_config(
+                    "esp-test",
+                    &[
+                        ("number", "NA", Value::Integer(999), None),
+                        ("number_signed", "NA", Value::Integer(-777), None),
+                        ("string", "NA", Value::String("Demo".to_owned()), None),
+                        ("bool", "NA", Value::Bool(false), None),
+                        ("number_default", "NA", Value::Integer(999), None),
+                        (
+                            "string_default",
+                            "NA",
+                            Value::String("Demo".to_owned()),
+                            None,
+                        ),
+                        ("bool_default", "NA", Value::Bool(false), None),
+                    ],
+                    false,
+                );
+
+                // some values have changed
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_NUMBER").unwrap() {
+                        Value::Integer(num) => *num,
+                        _ => unreachable!(),
+                    },
+                    0xaa
+                );
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_NUMBER_SIGNED").unwrap() {
+                        Value::Integer(num) => *num,
+                        _ => unreachable!(),
+                    },
+                    -999
+                );
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_STRING").unwrap() {
+                        Value::String(val) => val,
+                        _ => unreachable!(),
+                    },
+                    "Hello world!"
+                );
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_BOOL").unwrap() {
+                        Value::Bool(val) => *val,
+                        _ => unreachable!(),
+                    },
+                    true
+                );
+
+                // the rest are the defaults
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_NUMBER_DEFAULT").unwrap() {
+                        Value::Integer(num) => *num,
+                        _ => unreachable!(),
+                    },
+                    999
+                );
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_STRING_DEFAULT").unwrap() {
+                        Value::String(val) => val,
+                        _ => unreachable!(),
+                    },
+                    "Demo"
+                );
+                assert_eq!(
+                    match configs.get("ESP_TEST_CONFIG_BOOL_DEFAULT").unwrap() {
+                        Value::Bool(val) => *val,
+                        _ => unreachable!(),
+                    },
+                    false
+                );
+            },
+        )
+    }
+
+    #[test]
+    fn builtin_validation_passes() {
+        temp_env::with_vars(
+            [
+                ("ESP_TEST_CONFIG_POSITIVE_NUMBER", Some("7")),
+                ("ESP_TEST_CONFIG_NEGATIVE_NUMBER", Some("-1")),
+                ("ESP_TEST_CONFIG_NON_NEGATIVE_NUMBER", Some("0")),
+                ("ESP_TEST_CONFIG_RANGE", Some("9")),
+            ],
+            || {
+                generate_config(
+                    "esp-test",
+                    &[
+                        (
+                            "positive_number",
+                            "NA",
+                            Value::Integer(-1),
+                            Some(Validator::PositiveInteger),
+                        ),
+                        (
+                            "negative_number",
+                            "NA",
+                            Value::Integer(1),
+                            Some(Validator::NegativeInteger),
+                        ),
+                        (
+                            "non_negative_number",
+                            "NA",
+                            Value::Integer(-1),
+                            Some(Validator::NonNegativeInteger),
+                        ),
+                        (
+                            "range",
+                            "NA",
+                            Value::Integer(0),
+                            Some(Validator::IntegerInRange(5..10)),
+                        ),
+                    ],
+                    false,
+                )
+            },
+        );
+    }
+
+    #[test]
+    fn custom_validation_passes() {
+        temp_env::with_vars([("ESP_TEST_CONFIG_NUMBER", Some("13"))], || {
+            generate_config(
+                "esp-test",
+                &[(
+                    "number",
+                    "NA",
+                    Value::Integer(-1),
+                    Some(Validator::Custom(Box::new(|value| {
+                        let range = 10..20;
+                        if !value.is_integer() || !range.contains(&value.as_integer()) {
+                            Err(Error::validation("value does not fall within range"))
+                        } else {
+                            Ok(())
+                        }
+                    }))),
+                )],
+                false,
+            )
+        });
+    }
+
+    #[test]
+    #[should_panic]
+    fn builtin_validation_bails() {
+        temp_env::with_vars([("ESP_TEST_CONFIG_POSITIVE_NUMBER", Some("-99"))], || {
+            generate_config(
+                "esp-test",
+                &[(
+                    "positive_number",
+                    "NA",
+                    Value::Integer(-1),
+                    Some(Validator::PositiveInteger),
+                )],
+                false,
+            )
+        });
+    }
+
+    #[test]
+    #[should_panic]
+    fn custom_validation_bails() {
+        temp_env::with_vars([("ESP_TEST_CONFIG_NUMBER", Some("37"))], || {
+            generate_config(
+                "esp-test",
+                &[(
+                    "number",
+                    "NA",
+                    Value::Integer(-1),
+                    Some(Validator::Custom(Box::new(|value| {
+                        let range = 10..20;
+                        if !value.is_integer() || !range.contains(&value.as_integer()) {
+                            Err(Error::validation("value does not fall within range"))
+                        } else {
+                            Ok(())
+                        }
+                    }))),
+                )],
+                false,
+            )
+        });
+    }
+
+    #[test]
+    #[should_panic]
+    fn env_unknown_bails() {
+        temp_env::with_vars(
+            [
+                ("ESP_TEST_CONFIG_NUMBER", Some("0xaa")),
+                ("ESP_TEST_CONFIG_RANDOM_VARIABLE", Some("")),
+            ],
+            || {
+                generate_config(
+                    "esp-test",
+                    &[("number", "NA", Value::Integer(999), None)],
+                    false,
+                );
+            },
+        );
+    }
+
+    #[test]
+    #[should_panic]
+    fn env_invalid_values_bails() {
+        temp_env::with_vars([("ESP_TEST_CONFIG_NUMBER", Some("Hello world"))], || {
+            generate_config(
+                "esp-test",
+                &[("number", "NA", Value::Integer(999), None)],
+                false,
+            );
+        });
+    }
+
+    #[test]
+    fn env_unknown_prefix_is_ignored() {
+        temp_env::with_vars(
+            [("ESP_TEST_OTHER_CONFIG_NUMBER", Some("Hello world"))],
+            || {
+                generate_config(
+                    "esp-test",
+                    &[("number", "NA", Value::Integer(999), None)],
+                    false,
+                );
+            },
+        );
+    }
+}

esp-config/src/lib.rs

@@ -0,0 +1,110 @@
+#![doc = include_str!("../README.md")]
+//! ## Feature Flags
+#![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
+#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
+#![cfg_attr(not(feature = "build"), no_std)]
+#![deny(missing_docs, rust_2018_idioms)]
+
+#[cfg(feature = "build")]
+mod generate;
+#[cfg(feature = "build")]
+pub use generate::{generate_config, Error, Validator, Value};
+
+/// Parse the value of an environment variable as a [bool] at compile time.
+#[macro_export]
+macro_rules! esp_config_bool {
+    ( $var:expr ) => {
+        match env!($var).as_bytes() {
+            b"true" => true,
+            b"false" => false,
+            _ => ::core::panic!("boolean value must be either 'true' or 'false'"),
+        }
+    };
+}
+
+// TODO: From 1.82 on, we can use `<$ty>::from_str_radix(env!($var), 10)`
+/// Parse the value of an environment variable as an integer at compile time.
+#[macro_export]
+macro_rules! esp_config_int {
+    ( $ty:ty, $var:expr ) => {
+        const {
+            const BYTES: &[u8] = env!($var).as_bytes();
+            $crate::esp_config_int_parse!($ty, BYTES)
+        }
+    };
+}
+
+/// Get the string value of an environment variable at compile time.
+#[macro_export]
+macro_rules! esp_config_str {
+    ( $var:expr ) => {
+        env!($var)
+    };
+}
+
+/// Parse a string like "777" into an integer, which _can_ be used in a `const`
+/// context
+#[doc(hidden)] // To avoid confusion with `esp_config_int`, hide this in the docs
+#[macro_export]
+macro_rules! esp_config_int_parse {
+    ( $ty:ty, $bytes:expr ) => {{
+        let mut bytes = $bytes;
+        let mut val: $ty = 0;
+        let mut sign_seen = false;
+        let mut is_negative = false;
+
+        while let [byte, rest @ ..] = bytes {
+            match *byte {
+                b'0'..=b'9' => {
+                    val = val * 10 + (*byte - b'0') as $ty;
+                }
+                b'-' | b'+' if !sign_seen => {
+                    is_negative = *byte == b'-';
+                    sign_seen = true;
+                }
+                _ => ::core::panic!("invalid character encountered while parsing integer"),
+            }
+
+            bytes = rest;
+        }
+
+        if is_negative {
+            let original = val;
+            // Subtract the value twice to get a negative:
+            val -= original;
+            val -= original;
+        }
+
+        val
+    }};
+}
+
+#[cfg(test)]
+mod test {
+    // We can only test success in the const context
+    const _: () = {
+        core::assert!(esp_config_int_parse!(i64, "-77777".as_bytes()) == -77777);
+        core::assert!(esp_config_int_parse!(isize, "-7777".as_bytes()) == -7777);
+        core::assert!(esp_config_int_parse!(i32, "-999".as_bytes()) == -999);
+        core::assert!(esp_config_int_parse!(i16, "-99".as_bytes()) == -99);
+        core::assert!(esp_config_int_parse!(i8, "-9".as_bytes()) == -9);
+
+        core::assert!(esp_config_int_parse!(u64, "77777".as_bytes()) == 77777);
+        core::assert!(esp_config_int_parse!(usize, "7777".as_bytes()) == 7777);
+        core::assert!(esp_config_int_parse!(u32, "999".as_bytes()) == 999);
+        core::assert!(esp_config_int_parse!(u16, "99".as_bytes()) == 99);
+        core::assert!(esp_config_int_parse!(u8, "9".as_bytes()) == 9);
+    };
+
+    #[test]
+    #[should_panic]
+    fn test_expect_positive() {
+        esp_config_int_parse!(u8, "-5".as_bytes());
+    }
+
+    #[test]
+    #[should_panic]
+    fn test_invalid_digit() {
+        esp_config_int_parse!(u32, "a".as_bytes());
+    }
+}

esp-hal-common/Cargo.toml

@@ -1,182 +0,0 @@
-[package]
-name         = "esp-hal-common"
-version      = "0.14.1"
-edition      = "2021"
-rust-version = "1.67.0"
-description  = "HAL implementations for peripherals common among Espressif devices; should not be used directly"
-repository   = "https://github.com/esp-rs/esp-hal"
-license      = "MIT OR Apache-2.0"
-
-# Prevent multiple copies of this crate in the same binary.
-# Needed because different copies might get different features, causing
-# confusing build errors due to expected features not getting enabled
-# on the unintentional copy.
-# This is especially common when mixing crates from crates.io and git.
-links = "esp-hal-common"
-
-[dependencies]
-bitflags             = "2.4.1"
-bitfield             = "0.14.0"
-cfg-if               = "1.0.0"
-critical-section     = "1.1.2"
-defmt                = { version = "=0.3.5", optional = true }
-embedded-can         = { version = "0.4.1", optional = true }
-embedded-dma         = "0.2.0"
-embedded-hal         = { version = "0.2.7", features = ["unproven"] }
-embedded-hal-1       = { version = "=1.0.0-rc.2", optional = true, package = "embedded-hal" }
-embedded-hal-nb      = { version = "=1.0.0-rc.2", optional = true }
-embedded-io          = { version = "0.6.1", optional = true }
-enumset              = "1.1.3"
-esp-synopsys-usb-otg = { version = "0.4.0", optional = true, features = ["fs", "esp32sx"] }
-fugit                = "0.3.7"
-heapless             = "0.8.0"
-log                  = { version = "0.4.20", optional = true }
-nb                   = "1.1.0"
-paste                = "1.0.14"
-portable-atomic      = { version = "1.6.0", default-features = false }
-procmacros           = { version = "0.8.0", features = ["enum-dispatch", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
-strum                = { version = "0.25.0", default-features = false, features = ["derive"] }
-void                 = { version = "1.0.2", default-features = false }
-usb-device           = { version = "0.3.1", optional = true }
-
-# async
-embedded-hal-async = { version = "=1.0.0-rc.2", optional = true }
-embedded-io-async  = { version = "0.6.1", optional = true }
-embassy-executor   = { version = "0.4.0", optional = true }
-embassy-futures    = { version = "0.1.1", optional = true }
-embassy-sync       = { version = "0.5.0", optional = true }
-embassy-time       = { version = "0.2.0", optional = true }
-
-# RISC-V
-esp-riscv-rt = { version = "0.6.0", optional = true, path = "../esp-riscv-rt" }
-
-# Xtensa
-xtensa-lx    = { version = "0.8.0",  optional = true }
-xtensa-lx-rt = { version = "0.16.0", optional = true }
-
-# Part of `ufmt` containing only `uWrite` trait
-ufmt-write = { version = "0.1.0", optional = true }
-
-# IMPORTANT:
-# Each supported device MUST have its PAC included below along with a
-# corresponding feature.
-esp32   = { version = "0.28.0", features = ["critical-section"], optional = true }
-esp32c2 = { version = "0.17.0", features = ["critical-section"], optional = true }
-esp32c3 = { version = "0.20.0", features = ["critical-section"], optional = true }
-esp32c6 = { version = "0.11.0", features = ["critical-section"], optional = true }
-esp32h2 = { version = "0.7.0",  features = ["critical-section"], optional = true }
-esp32s2 = { version = "0.19.0", features = ["critical-section"], optional = true }
-esp32s3 = { version = "0.23.0", features = ["critical-section"], optional = true }
-
-[build-dependencies]
-basic-toml = "0.1.7"
-serde      = { version = "1.0.193", features = ["derive"] }
-
-[features]
-esp32   = ["xtensa", "esp32/rt",   "procmacros/esp32",   "xtensa-lx/esp32",   "xtensa-lx-rt/esp32"]
-esp32c2 = ["riscv",  "esp32c2/rt", "procmacros/esp32c2", "portable-atomic/unsafe-assume-single-core"]
-esp32c3 = ["riscv",  "esp32c3/rt", "procmacros/esp32c3", "portable-atomic/unsafe-assume-single-core"]
-esp32c6 = ["riscv",  "esp32c6/rt", "procmacros/esp32c6"]
-esp32h2 = ["riscv",  "esp32h2/rt", "procmacros/esp32h2"]
-esp32s2 = ["xtensa", "esp32s2/rt", "procmacros/esp32s2", "xtensa-lx/esp32s2", "xtensa-lx-rt/esp32s2", "usb-otg", "portable-atomic/critical-section"]
-esp32s3 = ["xtensa", "esp32s3/rt", "procmacros/esp32s3", "xtensa-lx/esp32s3", "xtensa-lx-rt/esp32s3", "usb-otg"]
-
-# Crystal frequency selection (ESP32 and ESP32-C2 only!)
-xtal-26mhz = []
-xtal-40mhz = []
-
-# Only certain chips support flip-link (ESP32-C6 and ESPS32-H2)
-flip-link = ["esp-riscv-rt/fix-sp"]
-
-# PSRAM support
-psram-2m = []
-psram-4m = []
-psram-8m = []
-
-# Octal RAM support
-opsram-2m  = []
-opsram-4m  = []
-opsram-8m  = []
-opsram-16m = []
-
-# USB OTG support (ESP32-S2 and ESP32-S3 only! Enabled by default)
-usb-otg = ["esp-synopsys-usb-otg", "usb-device"]
-
-# Interrupt-related feature:
-#  - Use direct interrupt vectoring (RISC-V only!)
-#  - Use interrupt preemption (RISC-V only!)
-#  - Use vectored interrupts (calling the handlers defined in the PAC)
-direct-vectoring     = ["esp-riscv-rt/direct-vectoring"]
-interrupt-preemption = ["esp-riscv-rt/interrupt-preemption"]
-vectored             = ["procmacros/interrupt"]
-
-# Enable logging
-log = ["dep:log"]
-
-# Trait implementation features:
-#  - Implement the `embedded-hal@1.0.0-rc.x` traits (and friends)
-#  - Implement the `embedded-io` traits where able
-#  - Implement the `ufmt_write::Write` trait where able
-eh1         = ["embedded-hal-1", "embedded-hal-nb", "embedded-can"]
-embedded-io = ["dep:embedded-io"]
-ufmt        = ["ufmt-write"]
-
-# Support for asynchronous operation, implementing traits from
-# `embedded-hal-async` and `embedded-io-async`
-async = [
-    "embedded-hal-async",
-    "eh1",
-    "embassy-sync",
-    "embassy-futures",
-    "embedded-io",
-    "embedded-io-async",
-]
-
-# Embassy support
-embassy = ["embassy-time", "procmacros/embassy"]
-
-embassy-executor-interrupt = ["embassy", "embassy-executor"]
-embassy-executor-thread    = ["embassy", "embassy-executor"]
-
-embassy-time-systick = []
-embassy-time-timg0   = []
-
-# Prefer integrated timers, but allow using the generic queue if needed
-embassy-integrated-timers = ["embassy-executor?/integrated-timers"]
-embassy-generic-queue-8   = ["embassy-time/generic-queue-8"]
-embassy-generic-queue-16  = ["embassy-time/generic-queue-16"]
-embassy-generic-queue-32  = ["embassy-time/generic-queue-32"]
-embassy-generic-queue-64  = ["embassy-time/generic-queue-64"]
-embassy-generic-queue-128 = ["embassy-time/generic-queue-128"]
-
-# Architecture-specific features (intended for internal use)
-riscv  = ["critical-section/restore-state-u8", "esp-riscv-rt", "esp-riscv-rt/zero-bss"]
-xtensa = ["critical-section/restore-state-u32"]
-
-# Initialize / clear data sections and RTC memory
-rv-init-data     = ["esp-riscv-rt/init-data", "esp-riscv-rt/init-rw-text"]
-rv-zero-rtc-bss  = ["esp-riscv-rt/zero-rtc-fast-bss"]
-rv-init-rtc-data = ["esp-riscv-rt/init-rtc-fast-data", "esp-riscv-rt/init-rtc-fast-text"]
-
-# Enable the `impl-register-debug` feature for the selected PAC
-debug = [
-    "esp32?/impl-register-debug",
-    "esp32c2?/impl-register-debug",
-    "esp32c3?/impl-register-debug",
-    "esp32c6?/impl-register-debug",
-    "esp32h2?/impl-register-debug",
-    "esp32s2?/impl-register-debug",
-    "esp32s3?/impl-register-debug",
-]
-
-# Enable support for `defmt`, for `esp-hal-common` and also for all our dependencies
-defmt = [
-    "dep:defmt",
-    "embassy-executor?/defmt",
-    "embassy-futures?/defmt",
-    "embassy-sync?/defmt",
-    "embassy-time?/defmt",
-    "embedded-hal-1?/defmt-03",
-    "embedded-io/defmt-03",
-    "embedded-io-async?/defmt-03",
-]

esp-hal-common/README.md

@@ -1,37 +0,0 @@
-# esp-hal-common
-
-[![Crates.io](https://img.shields.io/crates/v/esp-hal-common?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-hal-common)
-[![docs.rs](https://img.shields.io/docsrs/esp-hal-common?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-hal-common)
-![Crates.io](https://img.shields.io/crates/l/esp-hal-common?labelColor=1C2C2E&style=flat-square)
-[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
-
-`no_std` HAL implementations for the peripherals which are common among Espressif devices. Implements a number of the traits defined by [embedded-hal](https://github.com/rust-embedded/embedded-hal).
-
-This crate should not be used directly; you should use one of the device-specific HAL crates instead:
-
-- [esp32-hal](../esp32-hal/README.md)
-- [esp32c2-hal](../esp32c2-hal/README.md)
-- [esp32c3-hal](../esp32c3-hal/README.md)
-- [esp32c6-hal](../esp32c6-hal/README.md)
-- [esp32h2-hal](../esp32h2-hal/README.md)
-- [esp32s2-hal](../esp32s2-hal/README.md)
-- [esp32s3-hal](../esp32s3-hal/README.md)
-
-## [Documentation]
-
-[documentation]: https://docs.rs/esp-hal-common/
-
-## License
-
-Licensed under either of:
-
-- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
-- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
-
-at your option.
-
-### Contribution
-
-Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
-the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
-any additional terms or conditions.

esp-hal-common/build.rs

@@ -1,416 +0,0 @@
-use std::{
-    env,
-    error::Error,
-    fs::{self, File},
-    io::{BufRead, BufReader, Write},
-    path::{Path, PathBuf},
-};
-
-use serde::Deserialize;
-
-// Macros taken from:
-// https://github.com/TheDan64/inkwell/blob/36c3b10/src/lib.rs#L81-L110
-
-// Given some features, assert that AT MOST one of the features is enabled.
-macro_rules! assert_unique_features {
-    () => {};
-
-    ( $first:tt $(,$rest:tt)* ) => {
-        $(
-            #[cfg(all(feature = $first, feature = $rest))]
-            compile_error!(concat!("Features \"", $first, "\" and \"", $rest, "\" cannot be used together"));
-        )*
-        assert_unique_features!($($rest),*);
-    };
-}
-
-// Given some features, assert that AT LEAST one of the features is enabled.
-macro_rules! assert_used_features {
-    ( $all:tt ) => {
-        #[cfg(not(feature = $all))]
-        compile_error!(concat!("The feature flag must be provided: ", $all));
-    };
-
-    ( $($all:tt),+ ) => {
-        #[cfg(not(any($(feature = $all),*)))]
-        compile_error!(concat!("One of the feature flags must be provided: ", $($all, ", "),*));
-    };
-}
-
-// Given some features, assert that EXACTLY one of the features is enabled.
-macro_rules! assert_unique_used_features {
-    ( $($all:tt),* ) => {
-        assert_unique_features!($($all),*);
-        assert_used_features!($($all),*);
-    }
-}
-
-#[derive(Debug, Deserialize)]
-enum Arch {
-    #[serde(rename = "riscv")]
-    RiscV,
-    #[serde(rename = "xtensa")]
-    Xtensa,
-}
-
-impl std::fmt::Display for Arch {
-    fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
-        write!(
-            f,
-            "{}",
-            match self {
-                Arch::RiscV => "riscv",
-                Arch::Xtensa => "xtensa",
-            }
-        )
-    }
-}
-
-#[derive(Debug, Deserialize)]
-enum CoreCount {
-    #[serde(rename = "single_core")]
-    Single,
-    #[serde(rename = "multi_core")]
-    Multi,
-}
-
-impl std::fmt::Display for CoreCount {
-    fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
-        write!(
-            f,
-            "{}",
-            match self {
-                CoreCount::Single => "single_core",
-                CoreCount::Multi => "multi_core",
-            }
-        )
-    }
-}
-
-#[derive(Debug, Deserialize)]
-struct Device {
-    pub arch: Arch,
-    pub cores: CoreCount,
-    pub peripherals: Vec<String>,
-    pub symbols: Vec<String>,
-}
-
-#[derive(Debug, Deserialize)]
-struct Config {
-    pub device: Device,
-}
-
-fn main() -> Result<(), Box<dyn Error>> {
-    // NOTE: update when adding new device support!
-    // Ensure that exactly one chip has been specified:
-    assert_unique_used_features!(
-        "esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s2", "esp32s3"
-    );
-
-    // Handle the features for the ESP32's and ESP32-C2's different crystal
-    // frequencies:
-    #[cfg(any(feature = "esp32", feature = "esp32c2"))]
-    {
-        assert_unique_used_features!("xtal-26mhz", "xtal-40mhz");
-    }
-
-    // If the `embassy` feature is enabled, ensure that a time driver implementation
-    // is available:
-    #[cfg(feature = "embassy")]
-    {
-        #[cfg(feature = "esp32")]
-        assert_unique_used_features!("embassy-time-timg0");
-
-        #[cfg(not(feature = "esp32"))]
-        assert_unique_used_features!("embassy-time-systick", "embassy-time-timg0");
-    }
-
-    #[cfg(feature = "flip-link")]
-    {
-        #[cfg(not(any(feature = "esp32c6", feature = "esp32h2")))]
-        panic!("flip-link is only available on ESP32-C6/ESP32-H2");
-    }
-
-    // NOTE: update when adding new device support!
-    // Determine the name of the configured device:
-    let device_name = if cfg!(feature = "esp32") {
-        "esp32"
-    } else if cfg!(feature = "esp32c2") {
-        "esp32c2"
-    } else if cfg!(feature = "esp32c3") {
-        "esp32c3"
-    } else if cfg!(feature = "esp32c6") {
-        "esp32c6"
-    } else if cfg!(feature = "esp32h2") {
-        "esp32h2"
-    } else if cfg!(feature = "esp32s2") {
-        "esp32s2"
-    } else if cfg!(feature = "esp32s3") {
-        "esp32s3"
-    } else {
-        unreachable!() // We've confirmed exactly one known device was selected
-    };
-
-    if detect_atomic_extension("a") || detect_atomic_extension("s32c1i") {
-        panic!(
-            "Atomic emulation flags detected in `.cargo/config.toml`, this is no longer supported!"
-        );
-    }
-
-    // Load the configuration file for the configured device:
-    let chip_toml_path = PathBuf::from(env!("CARGO_MANIFEST_DIR"))
-        .join("devices")
-        .join(device_name)
-        .join("device.toml")
-        .canonicalize()?;
-
-    let config = fs::read_to_string(chip_toml_path)?;
-    let config: Config = basic_toml::from_str(&config)?;
-    let device = &config.device;
-
-    // Check PSRAM features are only given if the target supports PSRAM:
-    if !&device.symbols.contains(&String::from("psram"))
-        && (cfg!(feature = "psram-2m") || cfg!(feature = "psram-4m") || cfg!(feature = "psram-8m"))
-    {
-        panic!("The target does not support PSRAM");
-    }
-
-    // Define all necessary configuration symbols for the configured device:
-    println!("cargo:rustc-cfg={}", device_name);
-    println!("cargo:rustc-cfg={}", device.arch);
-    println!("cargo:rustc-cfg={}", device.cores);
-
-    for peripheral in &device.peripherals {
-        println!("cargo:rustc-cfg={peripheral}");
-    }
-
-    for symbol in &device.symbols {
-        println!("cargo:rustc-cfg={symbol}");
-    }
-
-    let mut config_symbols = Vec::new();
-    let arch = device.arch.to_string();
-    let cores = device.cores.to_string();
-    config_symbols.push(device_name);
-    config_symbols.push(&arch);
-    config_symbols.push(&cores);
-
-    for peripheral in &device.peripherals {
-        config_symbols.push(peripheral);
-    }
-
-    for symbol in &device.symbols {
-        config_symbols.push(symbol);
-    }
-
-    #[cfg(feature = "flip-link")]
-    config_symbols.push("flip-link");
-
-    // Place all linker scripts in `OUT_DIR`, and instruct Cargo how to find these
-    // files:
-    let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
-    println!("cargo:rustc-link-search={}", out.display());
-
-    if cfg!(feature = "esp32") || cfg!(feature = "esp32s2") || cfg!(feature = "esp32s3") {
-        fs::copy("ld/xtensa/hal-defaults.x", out.join("hal-defaults.x"))?;
-
-        let (irtc, drtc) = if cfg!(feature = "esp32s3") {
-            ("rtc_fast_seg", "rtc_fast_seg")
-        } else {
-            ("rtc_fast_iram_seg", "rtc_fast_dram_seg")
-        };
-
-        let alias = format!(
-            r#"
-            REGION_ALIAS("ROTEXT", irom_seg);
-            REGION_ALIAS("RWTEXT", iram_seg);
-            REGION_ALIAS("RODATA", drom_seg);
-            REGION_ALIAS("RWDATA", dram_seg);
-            REGION_ALIAS("RTC_FAST_RWTEXT", {});
-            REGION_ALIAS("RTC_FAST_RWDATA", {});
-        "#,
-            irtc, drtc
-        );
-
-        fs::write(out.join("alias.x"), alias)?;
-    } else {
-        preprocess_file(
-            &config_symbols,
-            "ld/riscv/hal-defaults.x",
-            out.join("hal-defaults.x"),
-        )?;
-        preprocess_file(&config_symbols, "ld/riscv/asserts.x", out.join("asserts.x"))?;
-        preprocess_file(&config_symbols, "ld/riscv/debug.x", out.join("debug.x"))?;
-    }
-
-    copy_dir_all(&config_symbols, "ld/sections", &out)?;
-    copy_dir_all(&config_symbols, format!("ld/{device_name}"), &out)?;
-
-    // Generate the eFuse table from the selected device's CSV file:
-    gen_efuse_table(device_name, out)?;
-
-    Ok(())
-}
-
-fn copy_dir_all(
-    config_symbols: &Vec<&str>,
-    src: impl AsRef<Path>,
-    dst: impl AsRef<Path>,
-) -> std::io::Result<()> {
-    fs::create_dir_all(&dst)?;
-    for entry in fs::read_dir(src)? {
-        let entry = entry?;
-        let ty = entry.file_type()?;
-        if ty.is_dir() {
-            copy_dir_all(
-                config_symbols,
-                entry.path(),
-                dst.as_ref().join(entry.file_name()),
-            )?;
-        } else {
-            preprocess_file(
-                config_symbols,
-                entry.path(),
-                dst.as_ref().join(entry.file_name()),
-            )?;
-        }
-    }
-    Ok(())
-}
-
-/// A naive pre-processor for linker scripts
-fn preprocess_file(
-    config: &Vec<&str>,
-    src: impl AsRef<Path>,
-    dst: impl AsRef<Path>,
-) -> std::io::Result<()> {
-    let file = File::open(src)?;
-    let mut out_file = File::create(dst)?;
-
-    let mut take = Vec::new();
-    take.push(true);
-
-    for line in std::io::BufReader::new(file).lines() {
-        let line = line?;
-        println!("{} >> {}", *take.last().unwrap(), line);
-        let trimmed = line.trim();
-
-        if trimmed.starts_with("#IF ") {
-            let condition = &trimmed[4..];
-            let should_take = take.iter().all(|v| *v == true);
-            let should_take = should_take && config.contains(&condition);
-            take.push(should_take);
-            continue;
-        } else if trimmed == "#ELSE" {
-            let taken = take.pop().unwrap();
-            let should_take = take.iter().all(|v| *v == true);
-            let should_take = should_take && !taken;
-            take.push(should_take);
-            continue;
-        } else if trimmed == "#ENDIF" {
-            take.pop();
-            continue;
-        }
-
-        if *take.last().unwrap() {
-            out_file.write(line.as_bytes())?;
-            out_file.write(b"\n")?;
-        }
-    }
-    Ok(())
-}
-
-fn gen_efuse_table(device_name: &str, out_dir: impl AsRef<Path>) -> Result<(), Box<dyn Error>> {
-    let src_path = PathBuf::from(format!("devices/{device_name}/efuse.csv"));
-    let out_path = out_dir.as_ref().join("efuse_fields.rs");
-
-    println!("cargo:rerun-if-changed={}", src_path.display());
-
-    let mut writer = File::create(out_path)?;
-    let mut reader = BufReader::new(File::open(src_path)?);
-    let mut line = String::with_capacity(128);
-
-    while reader.read_line(&mut line)? > 0 {
-        if line.ends_with("\n") {
-            line.pop();
-            if line.ends_with("\r") {
-                line.pop();
-            }
-        }
-        // drop comment and trim
-        line.truncate(
-            if let Some((pfx, _cmt)) = line.split_once("#") {
-                pfx
-            } else {
-                &line
-            }
-            .trim()
-            .len(),
-        );
-        // skip empty
-        if line.is_empty() {
-            continue;
-        }
-
-        let mut fields = line.split(",");
-        match (
-            fields.next().map(|s| s.trim().replace(".", "_")),
-            fields
-                .next()
-                .map(|s| s.trim().replace(|c: char| !c.is_ascii_digit(), "")),
-            fields
-                .next()
-                .map(|s| s.trim())
-                .and_then(|s| s.parse::<u32>().ok()),
-            fields
-                .next()
-                .map(|s| s.trim())
-                .and_then(|s| s.parse::<u32>().ok()),
-            fields.next().map(|s| s.trim()),
-        ) {
-            (Some(name), Some(block), Some(bit_off), Some(bit_len), Some(desc)) => {
-                let desc = desc.replace('[', "`[").replace(']', "]`");
-                writeln!(writer, "/// {desc}")?;
-                writeln!(
-                    writer,
-                    "pub const {name}: EfuseField = EfuseField::new(EfuseBlock::Block{block}, {bit_off}, {bit_len});"
-                )?;
-            }
-            other => eprintln!("Invalid data: {other:?}"),
-        }
-
-        line.clear();
-    }
-
-    Ok(())
-}
-
-fn detect_atomic_extension(ext: &str) -> bool {
-    let rustflags = env::var_os("CARGO_ENCODED_RUSTFLAGS")
-        .unwrap()
-        .into_string()
-        .unwrap();
-
-    // Users can pass -Ctarget-feature to the compiler multiple times, so we have to
-    // handle that
-    let target_flags = rustflags
-        .split(0x1f as char)
-        .filter(|s| s.starts_with("target-feature="))
-        .map(|s| s.strip_prefix("target-feature="))
-        .flatten();
-    for tf in target_flags {
-        let tf = tf
-            .split(",")
-            .map(|s| s.trim())
-            .filter(|s| s.starts_with('+'))
-            .map(|s| s.strip_prefix('+'))
-            .flatten();
-        for tf in tf {
-            if tf == ext {
-                return true;
-            }
-        }
-    }
-
-    false
-}

esp-hal-common/devices/esp32/efuse.csv

@@ -1,118 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 369d2d860d34e777c0f7d545a7dfc3c4
-
-WR_DIS,                                          EFUSE_BLK0,   0,  16, [] Efuse write disable mask
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS
-WR_DIS.WR_DIS,                                   EFUSE_BLK0,   1,   1, [] wr_dis of WR_DIS
-WR_DIS.FLASH_CRYPT_CNT,                          EFUSE_BLK0,   2,   1, [] wr_dis of FLASH_CRYPT_CNT
-WR_DIS.UART_DOWNLOAD_DIS,                        EFUSE_BLK0,   2,   1, [] wr_dis of UART_DOWNLOAD_DIS
-WR_DIS.MAC,                                      EFUSE_BLK0,   3,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.MAC_CRC,                                  EFUSE_BLK0,   3,   1, [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC
-WR_DIS.DISABLE_APP_CPU,                          EFUSE_BLK0,   3,   1, [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU
-WR_DIS.DISABLE_BT,                               EFUSE_BLK0,   3,   1, [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT
-WR_DIS.DIS_CACHE,                                EFUSE_BLK0,   3,   1, [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE
-WR_DIS.VOL_LEVEL_HP_INV,                         EFUSE_BLK0,   3,   1, [] wr_dis of VOL_LEVEL_HP_INV
-WR_DIS.CLK8M_FREQ,                               EFUSE_BLK0,   4,   1, [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ
-WR_DIS.ADC_VREF,                                 EFUSE_BLK0,   4,   1, [] wr_dis of ADC_VREF
-WR_DIS.XPD_SDIO_REG,                             EFUSE_BLK0,   5,   1, [] wr_dis of XPD_SDIO_REG
-WR_DIS.XPD_SDIO_TIEH,                            EFUSE_BLK0,   5,   1, [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH
-WR_DIS.XPD_SDIO_FORCE,                           EFUSE_BLK0,   5,   1, [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE
-WR_DIS.SPI_PAD_CONFIG_CLK,                       EFUSE_BLK0,   6,   1, [] wr_dis of SPI_PAD_CONFIG_CLK
-WR_DIS.SPI_PAD_CONFIG_Q,                         EFUSE_BLK0,   6,   1, [] wr_dis of SPI_PAD_CONFIG_Q
-WR_DIS.SPI_PAD_CONFIG_D,                         EFUSE_BLK0,   6,   1, [] wr_dis of SPI_PAD_CONFIG_D
-WR_DIS.SPI_PAD_CONFIG_CS0,                       EFUSE_BLK0,   6,   1, [] wr_dis of SPI_PAD_CONFIG_CS0
-WR_DIS.BLOCK1,                                   EFUSE_BLK0,   7,   1, [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1
-WR_DIS.BLOCK2,                                   EFUSE_BLK0,   8,   1, [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2
-WR_DIS.BLOCK3,                                   EFUSE_BLK0,   9,   1, [WR_DIS.BLK3] wr_dis of BLOCK3
-WR_DIS.CUSTOM_MAC_CRC,                           EFUSE_BLK0,   9,   1, [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,   9,   1, [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.ADC1_TP_LOW,                              EFUSE_BLK0,   9,   1, [] wr_dis of ADC1_TP_LOW
-WR_DIS.ADC1_TP_HIGH,                             EFUSE_BLK0,   9,   1, [] wr_dis of ADC1_TP_HIGH
-WR_DIS.ADC2_TP_LOW,                              EFUSE_BLK0,   9,   1, [] wr_dis of ADC2_TP_LOW
-WR_DIS.ADC2_TP_HIGH,                             EFUSE_BLK0,   9,   1, [] wr_dis of ADC2_TP_HIGH
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,   9,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.MAC_VERSION,                              EFUSE_BLK0,   9,   1, [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION
-WR_DIS.BLK3_PART_RESERVE,                        EFUSE_BLK0,  10,   1, [] wr_dis of BLK3_PART_RESERVE
-WR_DIS.FLASH_CRYPT_CONFIG,                       EFUSE_BLK0,  10,   1, [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG
-WR_DIS.CODING_SCHEME,                            EFUSE_BLK0,  10,   1, [] wr_dis of CODING_SCHEME
-WR_DIS.KEY_STATUS,                               EFUSE_BLK0,  10,   1, [] wr_dis of KEY_STATUS
-WR_DIS.ABS_DONE_0,                               EFUSE_BLK0,  12,   1, [] wr_dis of ABS_DONE_0
-WR_DIS.ABS_DONE_1,                               EFUSE_BLK0,  13,   1, [] wr_dis of ABS_DONE_1
-WR_DIS.JTAG_DISABLE,                             EFUSE_BLK0,  14,   1, [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE
-WR_DIS.CONSOLE_DEBUG_DISABLE,                    EFUSE_BLK0,  15,   1, [] wr_dis of CONSOLE_DEBUG_DISABLE
-WR_DIS.DISABLE_DL_ENCRYPT,                       EFUSE_BLK0,  15,   1, [] wr_dis of DISABLE_DL_ENCRYPT
-WR_DIS.DISABLE_DL_DECRYPT,                       EFUSE_BLK0,  15,   1, [] wr_dis of DISABLE_DL_DECRYPT
-WR_DIS.DISABLE_DL_CACHE,                         EFUSE_BLK0,  15,   1, [] wr_dis of DISABLE_DL_CACHE
-RD_DIS,                                          EFUSE_BLK0,  16,   4, [] Disable reading from BlOCK1-3
-RD_DIS.BLOCK1,                                   EFUSE_BLK0,  16,   1, [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1
-RD_DIS.BLOCK2,                                   EFUSE_BLK0,  17,   1, [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2
-RD_DIS.BLOCK3,                                   EFUSE_BLK0,  18,   1, [RD_DIS.BLK3] rd_dis of BLOCK3
-RD_DIS.CUSTOM_MAC_CRC,                           EFUSE_BLK0,  18,   1, [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC
-RD_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  18,   1, [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC
-RD_DIS.ADC1_TP_LOW,                              EFUSE_BLK0,  18,   1, [] rd_dis of ADC1_TP_LOW
-RD_DIS.ADC1_TP_HIGH,                             EFUSE_BLK0,  18,   1, [] rd_dis of ADC1_TP_HIGH
-RD_DIS.ADC2_TP_LOW,                              EFUSE_BLK0,  18,   1, [] rd_dis of ADC2_TP_LOW
-RD_DIS.ADC2_TP_HIGH,                             EFUSE_BLK0,  18,   1, [] rd_dis of ADC2_TP_HIGH
-RD_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] rd_dis of SECURE_VERSION
-RD_DIS.MAC_VERSION,                              EFUSE_BLK0,  18,   1, [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION
-RD_DIS.BLK3_PART_RESERVE,                        EFUSE_BLK0,  19,   1, [] rd_dis of BLK3_PART_RESERVE
-RD_DIS.FLASH_CRYPT_CONFIG,                       EFUSE_BLK0,  19,   1, [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG
-RD_DIS.CODING_SCHEME,                            EFUSE_BLK0,  19,   1, [] rd_dis of CODING_SCHEME
-RD_DIS.KEY_STATUS,                               EFUSE_BLK0,  19,   1, [] rd_dis of KEY_STATUS
-FLASH_CRYPT_CNT,                                 EFUSE_BLK0,  20,   7, [] Flash encryption is enabled if this field has an odd number of bits set
-UART_DOWNLOAD_DIS,                               EFUSE_BLK0,  27,   1, [] Disable UART download mode. Valid for ESP32 V3 and newer; only
-MAC_FACTORY,                                     EFUSE_BLK0,  32,   48, [MAC_FACTORY] MAC address
-MAC_CRC,                                         EFUSE_BLK0,  80,   8, [MAC_FACTORY_CRC] CRC8 for MAC address
-DISABLE_APP_CPU,                                 EFUSE_BLK0,  96,   1, [CHIP_VER_DIS_APP_CPU] Disables APP CPU
-DISABLE_BT,                                      EFUSE_BLK0,  97,   1, [CHIP_VER_DIS_BT] Disables Bluetooth
-CHIP_PACKAGE_4BIT,                               EFUSE_BLK0,  98,   1, [CHIP_VER_PKG_4BIT] Chip package identifier #4bit
-DIS_CACHE,                                       EFUSE_BLK0,  99,   1, [CHIP_VER_DIS_CACHE] Disables cache
-SPI_PAD_CONFIG_HD,                               EFUSE_BLK0, 100,   5, [] read for SPI_pad_config_hd
-CHIP_PACKAGE,                                    EFUSE_BLK0, 105,   3, [CHIP_VER_PKG] Chip package identifier
-CHIP_CPU_FREQ_LOW,                               EFUSE_BLK0, 108,   1, [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise
-CHIP_CPU_FREQ_RATED,                             EFUSE_BLK0, 109,   1, [] If set; the ESP32's maximum CPU frequency has been rated
-BLK3_PART_RESERVE,                               EFUSE_BLK0, 110,   1, [] BLOCK3 partially served for ADC calibration data
-CHIP_VER_REV1,                                   EFUSE_BLK0, 111,   1, [] bit is set to 1 for rev1 silicon
-CLK8M_FREQ,                                      EFUSE_BLK0, 128,   8, [CK8M_FREQ] 8MHz clock freq override
-ADC_VREF,                                        EFUSE_BLK0, 136,   5, [] True ADC reference voltage
-XPD_SDIO_REG,                                    EFUSE_BLK0, 142,   1, [] read for XPD_SDIO_REG
-XPD_SDIO_TIEH,                                   EFUSE_BLK0, 143,   1, [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"}
-XPD_SDIO_FORCE,                                  EFUSE_BLK0, 144,   1, [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset
-SPI_PAD_CONFIG_CLK,                              EFUSE_BLK0, 160,   5, [] Override SD_CLK pad (GPIO6/SPICLK)
-SPI_PAD_CONFIG_Q,                                EFUSE_BLK0, 165,   5, [] Override SD_DATA_0 pad (GPIO7/SPIQ)
-SPI_PAD_CONFIG_D,                                EFUSE_BLK0, 170,   5, [] Override SD_DATA_1 pad (GPIO8/SPID)
-SPI_PAD_CONFIG_CS0,                              EFUSE_BLK0, 175,   5, [] Override SD_CMD pad (GPIO11/SPICS0)
-CHIP_VER_REV2,                                   EFUSE_BLK0, 180,   1, []
-VOL_LEVEL_HP_INV,                                EFUSE_BLK0, 182,   2, [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
-WAFER_VERSION_MINOR,                             EFUSE_BLK0, 184,   2, []
-FLASH_CRYPT_CONFIG,                              EFUSE_BLK0, 188,   4, [ENCRYPT_CONFIG] Flash encryption config (key tweak bits)
-CODING_SCHEME,                                   EFUSE_BLK0, 192,   2, [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)"; 1: "3/4 (BLK1-3 len=192 bits)"; 2: "REPEAT (BLK1-3 len=128 bits) not supported"; 3: "NONE (BLK1-3 len=256 bits)"}
-CONSOLE_DEBUG_DISABLE,                           EFUSE_BLK0, 194,   1, [] Disable ROM BASIC interpreter fallback
-DISABLE_SDIO_HOST,                               EFUSE_BLK0, 195,   1, []
-ABS_DONE_0,                                      EFUSE_BLK0, 196,   1, [] Secure boot V1 is enabled for bootloader image
-ABS_DONE_1,                                      EFUSE_BLK0, 197,   1, [] Secure boot V2 is enabled for bootloader image
-JTAG_DISABLE,                                    EFUSE_BLK0, 198,   1, [DISABLE_JTAG] Disable JTAG
-DISABLE_DL_ENCRYPT,                              EFUSE_BLK0, 199,   1, [] Disable flash encryption in UART bootloader
-DISABLE_DL_DECRYPT,                              EFUSE_BLK0, 200,   1, [] Disable flash decryption in UART bootloader
-DISABLE_DL_CACHE,                                EFUSE_BLK0, 201,   1, [] Disable flash cache in UART bootloader
-KEY_STATUS,                                      EFUSE_BLK0, 202,   1, [] Usage of efuse block 3 (reserved)
-BLOCK1,                                          EFUSE_BLK1,   0, MAX_BLK_LEN, [ENCRYPT_FLASH_KEY] Flash encryption key
-BLOCK2,                                          EFUSE_BLK2,   0, MAX_BLK_LEN, [SECURE_BOOT_KEY] Security boot key
-CUSTOM_MAC_CRC,                                  EFUSE_BLK3,   0,   8, [MAC_CUSTOM_CRC] CRC8 for custom MAC address
-MAC_CUSTOM,                                      EFUSE_BLK3,   8,  48, [MAC_CUSTOM] Custom MAC address
-ADC1_TP_LOW,                                     EFUSE_BLK3,  96,   7, [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
-ADC1_TP_HIGH,                                    EFUSE_BLK3, 103,   9, [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
-ADC2_TP_LOW,                                     EFUSE_BLK3, 112,   7, [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
-ADC2_TP_HIGH,                                    EFUSE_BLK3, 119,   9, [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
-SECURE_VERSION,                                  EFUSE_BLK3, 128,  32, [] Secure version for anti-rollback
-MAC_VERSION,                                     EFUSE_BLK3, 184,   8, [MAC_CUSTOM_VER] Version of the MAC field {1: "Custom MAC in BLOCK3"}

esp-hal-common/devices/esp32c2/efuse.csv

@@ -1,107 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 897499b0349a608b895d467abbcf006b
-
-WR_DIS,                                          EFUSE_BLK0,   0,   8, [] Disable programming of individual eFuses
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
-WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   1,   1, [] wr_dis of WDT_DELAY_SEL
-WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   1,   1, [] wr_dis of DIS_PAD_JTAG
-WR_DIS.DIS_DOWNLOAD_ICACHE,                      EFUSE_BLK0,   1,   1, [] wr_dis of DIS_DOWNLOAD_ICACHE
-WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
-WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   2,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
-WR_DIS.XTS_KEY_LENGTH_256,                       EFUSE_BLK0,   2,   1, [] wr_dis of XTS_KEY_LENGTH_256
-WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,   2,   1, [] wr_dis of SECURE_BOOT_EN
-WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,   3,   1, [] wr_dis of UART_PRINT_CONTROL
-WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,   3,   1, [] wr_dis of FORCE_SEND_RESUME
-WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,   3,   1, [] wr_dis of DIS_DOWNLOAD_MODE
-WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,   3,   1, [] wr_dis of DIS_DIRECT_BOOT
-WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,   3,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
-WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,   3,   1, [] wr_dis of FLASH_TPUW
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,   4,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.CUSTOM_MAC_USED,                          EFUSE_BLK0,   4,   1, [WR_DIS.ENABLE_CUSTOM_MAC] wr_dis of CUSTOM_MAC_USED
-WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,   4,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
-WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,   4,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,   5,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.MAC,                                      EFUSE_BLK0,   6,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.WAFER_VERSION_MINOR,                      EFUSE_BLK0,   6,   1, [] wr_dis of WAFER_VERSION_MINOR
-WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,   6,   1, [] wr_dis of WAFER_VERSION_MAJOR
-WR_DIS.PKG_VERSION,                              EFUSE_BLK0,   6,   1, [] wr_dis of PKG_VERSION
-WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,   6,   1, [] wr_dis of BLK_VERSION_MINOR
-WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,   6,   1, [] wr_dis of BLK_VERSION_MAJOR
-WR_DIS.OCODE,                                    EFUSE_BLK0,   6,   1, [] wr_dis of OCODE
-WR_DIS.TEMP_CALIB,                               EFUSE_BLK0,   6,   1, [] wr_dis of TEMP_CALIB
-WR_DIS.ADC1_INIT_CODE_ATTEN0,                    EFUSE_BLK0,   6,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
-WR_DIS.ADC1_INIT_CODE_ATTEN3,                    EFUSE_BLK0,   6,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
-WR_DIS.ADC1_CAL_VOL_ATTEN0,                      EFUSE_BLK0,   6,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
-WR_DIS.ADC1_CAL_VOL_ATTEN3,                      EFUSE_BLK0,   6,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
-WR_DIS.DIG_DBIAS_HVT,                            EFUSE_BLK0,   6,   1, [] wr_dis of DIG_DBIAS_HVT
-WR_DIS.DIG_LDO_SLP_DBIAS2,                       EFUSE_BLK0,   6,   1, [] wr_dis of DIG_LDO_SLP_DBIAS2
-WR_DIS.DIG_LDO_SLP_DBIAS26,                      EFUSE_BLK0,   6,   1, [] wr_dis of DIG_LDO_SLP_DBIAS26
-WR_DIS.DIG_LDO_ACT_DBIAS26,                      EFUSE_BLK0,   6,   1, [] wr_dis of DIG_LDO_ACT_DBIAS26
-WR_DIS.DIG_LDO_ACT_STEPD10,                      EFUSE_BLK0,   6,   1, [] wr_dis of DIG_LDO_ACT_STEPD10
-WR_DIS.RTC_LDO_SLP_DBIAS13,                      EFUSE_BLK0,   6,   1, [] wr_dis of RTC_LDO_SLP_DBIAS13
-WR_DIS.RTC_LDO_SLP_DBIAS29,                      EFUSE_BLK0,   6,   1, [] wr_dis of RTC_LDO_SLP_DBIAS29
-WR_DIS.RTC_LDO_SLP_DBIAS31,                      EFUSE_BLK0,   6,   1, [] wr_dis of RTC_LDO_SLP_DBIAS31
-WR_DIS.RTC_LDO_ACT_DBIAS31,                      EFUSE_BLK0,   6,   1, [] wr_dis of RTC_LDO_ACT_DBIAS31
-WR_DIS.RTC_LDO_ACT_DBIAS13,                      EFUSE_BLK0,   6,   1, [] wr_dis of RTC_LDO_ACT_DBIAS13
-WR_DIS.ADC_CALIBRATION_3,                        EFUSE_BLK0,   6,   1, [] wr_dis of ADC_CALIBRATION_3
-WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,   7,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
-RD_DIS,                                          EFUSE_BLK0,  32,   2, [] Disable reading from BlOCK3
-RD_DIS.KEY0,                                     EFUSE_BLK0,  32,   2, [] Read protection for EFUSE_BLK3. KEY0
-RD_DIS.KEY0.LOW,                                 EFUSE_BLK0,  32,   1, [] Read protection for EFUSE_BLK3. KEY0 lower 128-bit key
-RD_DIS.KEY0.HI,                                  EFUSE_BLK0,  33,   1, [] Read protection for EFUSE_BLK3. KEY0 higher 128-bit key
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  34,   2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
-DIS_PAD_JTAG,                                    EFUSE_BLK0,  36,   1, [] Set this bit to disable pad jtag
-DIS_DOWNLOAD_ICACHE,                             EFUSE_BLK0,  37,   1, [] The bit be set to disable icache in download mode
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  38,   1, [] The bit be set to disable manual encryption
-SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  39,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
-XTS_KEY_LENGTH_256,                              EFUSE_BLK0,  42,   1, [] Flash encryption key length {0: "128 bits key"; 1: "256 bits key"}
-UART_PRINT_CONTROL,                              EFUSE_BLK0,  43,   2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
-FORCE_SEND_RESUME,                               EFUSE_BLK0,  45,   1, [] Set this bit to force ROM code to send a resume command during SPI boot
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0,  46,   1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7)
-DIS_DIRECT_BOOT,                                 EFUSE_BLK0,  47,   1, [] This bit set means disable direct_boot mode
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0,  48,   1, [] Set this bit to enable secure UART download mode
-FLASH_TPUW,                                      EFUSE_BLK0,  49,   4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value.  Otherwise; the waiting time is twice the configurable value
-SECURE_BOOT_EN,                                  EFUSE_BLK0,  53,   1, [] The bit be set to enable secure boot
-SECURE_VERSION,                                  EFUSE_BLK0,  54,   4, [] Secure version for anti-rollback
-CUSTOM_MAC_USED,                                 EFUSE_BLK0,  58,   1, [ENABLE_CUSTOM_MAC] True if MAC_CUSTOM is burned
-DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK0,  59,   1, [] Disables check of wafer version major
-DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK0,  60,   1, [] Disables check of blk version major
-USER_DATA,                                       EFUSE_BLK1,   0,  88, [] User data block
-USER_DATA.MAC_CUSTOM,                            EFUSE_BLK1,   0,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address
-MAC_FACTORY,                                     EFUSE_BLK2,   0,  48, [MAC_FACTORY] MAC address
-WAFER_VERSION_MINOR,                             EFUSE_BLK2,  48,   4, [] WAFER_VERSION_MINOR
-WAFER_VERSION_MAJOR,                             EFUSE_BLK2,  52,   2, [] WAFER_VERSION_MAJOR
-PKG_VERSION,                                     EFUSE_BLK2,  54,   3, [] EFUSE_PKG_VERSION
-BLK_VERSION_MINOR,                               EFUSE_BLK2,  57,   3, [] Minor version of BLOCK2 {0: "No calib"; 1: "With calib"}
-BLK_VERSION_MAJOR,                               EFUSE_BLK2,  60,   2, [] Major version of BLOCK2
-OCODE,                                           EFUSE_BLK2,  62,   7, [] OCode
-TEMP_CALIB,                                      EFUSE_BLK2,  69,   9, [] Temperature calibration data
-ADC1_INIT_CODE_ATTEN0,                           EFUSE_BLK2,  78,   8, [] ADC1 init code at atten0
-ADC1_INIT_CODE_ATTEN3,                           EFUSE_BLK2,  86,   5, [] ADC1 init code at atten3
-ADC1_CAL_VOL_ATTEN0,                             EFUSE_BLK2,  91,   8, [] ADC1 calibration voltage at atten0
-ADC1_CAL_VOL_ATTEN3,                             EFUSE_BLK2,  99,   6, [] ADC1 calibration voltage at atten3
-DIG_DBIAS_HVT,                                   EFUSE_BLK2, 105,   5, [] BLOCK2 digital dbias when hvt
-DIG_LDO_SLP_DBIAS2,                              EFUSE_BLK2, 110,   7, [] BLOCK2 DIG_LDO_DBG0_DBIAS2
-DIG_LDO_SLP_DBIAS26,                             EFUSE_BLK2, 117,   8, [] BLOCK2 DIG_LDO_DBG0_DBIAS26
-DIG_LDO_ACT_DBIAS26,                             EFUSE_BLK2, 125,   6, [] BLOCK2 DIG_LDO_ACT_DBIAS26
-DIG_LDO_ACT_STEPD10,                             EFUSE_BLK2, 131,   4, [] BLOCK2 DIG_LDO_ACT_STEPD10
-RTC_LDO_SLP_DBIAS13,                             EFUSE_BLK2, 135,   7, [] BLOCK2 DIG_LDO_SLP_DBIAS13
-RTC_LDO_SLP_DBIAS29,                             EFUSE_BLK2, 142,   9, [] BLOCK2 DIG_LDO_SLP_DBIAS29
-RTC_LDO_SLP_DBIAS31,                             EFUSE_BLK2, 151,   6, [] BLOCK2 DIG_LDO_SLP_DBIAS31
-RTC_LDO_ACT_DBIAS31,                             EFUSE_BLK2, 157,   6, [] BLOCK2 DIG_LDO_ACT_DBIAS31
-RTC_LDO_ACT_DBIAS13,                             EFUSE_BLK2, 163,   8, [] BLOCK2 DIG_LDO_ACT_DBIAS13
-ADC_CALIBRATION_3,                               EFUSE_BLK2, 192,  11, [] Store the bit [86:96] of ADC calibration data
-KEY0,                                            EFUSE_BLK3,   0, 256, [BLOCK_KEY0] BLOCK_BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption
-KEY0.FE_256BIT,                                  EFUSE_BLK3,   0, 256, [] 256bit FE key
-KEY0.FE_128BIT,                                  EFUSE_BLK3,   0, 128, [] 128bit FE key
-KEY0.SB_128BIT,                                  EFUSE_BLK3, 128, 128, [] 128bit SB key

esp-hal-common/devices/esp32c3/efuse.csv

@@ -1,187 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: a85f874ae2b6538ca48b7c3db4a79531
-
-WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
-WR_DIS.DIS_ICACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_ICACHE
-WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
-WR_DIS.DIS_DOWNLOAD_ICACHE,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_ICACHE
-WR_DIS.DIS_USB_SERIAL_JTAG,                      EFUSE_BLK0,   2,   1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG
-WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
-WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
-WR_DIS.JTAG_SEL_ENABLE,                          EFUSE_BLK0,   2,   1, [] wr_dis of JTAG_SEL_ENABLE
-WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_PAD_JTAG
-WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
-WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   3,   1, [] wr_dis of WDT_DELAY_SEL
-WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
-WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
-WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
-WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
-WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
-WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
-WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
-WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
-WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
-WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
-WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
-WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
-WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
-WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
-WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT
-WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
-WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
-WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
-WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.ERR_RST_ENABLE,                           EFUSE_BLK0,  19,   1, [] wr_dis of ERR_RST_ENABLE
-WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,  19,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
-WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  19,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
-WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
-WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.SPI_PAD_CONFIG_CLK,                       EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_CLK
-WR_DIS.SPI_PAD_CONFIG_Q,                         EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_Q
-WR_DIS.SPI_PAD_CONFIG_D,                         EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D
-WR_DIS.SPI_PAD_CONFIG_CS,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_CS
-WR_DIS.SPI_PAD_CONFIG_HD,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_HD
-WR_DIS.SPI_PAD_CONFIG_WP,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_WP
-WR_DIS.SPI_PAD_CONFIG_DQS,                       EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_DQS
-WR_DIS.SPI_PAD_CONFIG_D4,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D4
-WR_DIS.SPI_PAD_CONFIG_D5,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D5
-WR_DIS.SPI_PAD_CONFIG_D6,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D6
-WR_DIS.SPI_PAD_CONFIG_D7,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D7
-WR_DIS.WAFER_VERSION_MINOR_LO,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR_LO
-WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
-WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MINOR
-WR_DIS.K_RTC_LDO,                                EFUSE_BLK0,  20,   1, [] wr_dis of K_RTC_LDO
-WR_DIS.K_DIG_LDO,                                EFUSE_BLK0,  20,   1, [] wr_dis of K_DIG_LDO
-WR_DIS.V_RTC_DBIAS20,                            EFUSE_BLK0,  20,   1, [] wr_dis of V_RTC_DBIAS20
-WR_DIS.V_DIG_DBIAS20,                            EFUSE_BLK0,  20,   1, [] wr_dis of V_DIG_DBIAS20
-WR_DIS.DIG_DBIAS_HVT,                            EFUSE_BLK0,  20,   1, [] wr_dis of DIG_DBIAS_HVT
-WR_DIS.THRES_HVT,                                EFUSE_BLK0,  20,   1, [] wr_dis of THRES_HVT
-WR_DIS.WAFER_VERSION_MINOR_HI,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR_HI
-WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR
-WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
-WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
-WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MAJOR
-WR_DIS.TEMP_CALIB,                               EFUSE_BLK0,  21,   1, [] wr_dis of TEMP_CALIB
-WR_DIS.OCODE,                                    EFUSE_BLK0,  21,   1, [] wr_dis of OCODE
-WR_DIS.ADC1_INIT_CODE_ATTEN0,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
-WR_DIS.ADC1_INIT_CODE_ATTEN1,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
-WR_DIS.ADC1_INIT_CODE_ATTEN2,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
-WR_DIS.ADC1_INIT_CODE_ATTEN3,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
-WR_DIS.ADC1_CAL_VOL_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
-WR_DIS.ADC1_CAL_VOL_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
-WR_DIS.ADC1_CAL_VOL_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
-WR_DIS.ADC1_CAL_VOL_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
-WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
-WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
-WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
-WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
-WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
-WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
-WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
-WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
-WR_DIS.VDD_SPI_AS_GPIO,                          EFUSE_BLK0,  30,   1, [] wr_dis of VDD_SPI_AS_GPIO
-WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
-RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
-RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
-RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
-RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
-RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
-RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
-RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
-RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
-DIS_ICACHE,                                      EFUSE_BLK0,  40,   1, [] Set this bit to disable Icache
-DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Set this bit to disable function of usb switch to jtag in module of usb device
-DIS_DOWNLOAD_ICACHE,                             EFUSE_BLK0,  42,   1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
-DIS_USB_SERIAL_JTAG,                             EFUSE_BLK0,  43,   1, [DIS_USB_DEVICE] USB-Serial-JTAG {0: "Enable"; 1: "Disable"}
-DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Set this bit to disable the function that forces chip into download mode
-DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [DIS_CAN] Set this bit to disable CAN function
-JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
-SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
-DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Set this bit to disable flash encryption when in download boot modes
-USB_EXCHG_PINS,                                  EFUSE_BLK0,  57,   1, [] Set this bit to exchange USB D+ and D- pins
-VDD_SPI_AS_GPIO,                                 EFUSE_BLK0,  58,   1, [] Set this bit to vdd spi pin function as gpio
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
-SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
-SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
-SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
-SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
-KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Purpose of Key0
-KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Purpose of Key1
-KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Purpose of Key2
-KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Purpose of Key3
-KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Purpose of Key4
-KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Purpose of Key5
-SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Set this bit to enable secure boot
-SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Set this bit to enable revoking aggressive secure boot
-FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value; Otherwise; the waiting time is twice the configurable value
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
-DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode
-DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}
-DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [DIS_USB_DOWNLOAD_MODE] Disable UART download mode through USB-Serial-JTAG
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Set this bit to enable secure UART download mode
-UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
-FORCE_SEND_RESUME,                               EFUSE_BLK0, 141,   1, [] Set this bit to force ROM code to send a resume command during SPI boot
-SECURE_VERSION,                                  EFUSE_BLK0, 142,  16, [] Secure version (used by ESP-IDF anti-rollback feature)
-ERR_RST_ENABLE,                                  EFUSE_BLK0, 159,   1, [] Use BLOCK0 to check error record registers {0: "without check"; 1: "with check"}
-DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK0, 160,   1, [] Disables check of wafer version major
-DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK0, 161,   1, [] Disables check of blk version major
-MAC_FACTORY,                                     EFUSE_BLK1,   0,  48, [MAC_FACTORY] MAC address
-SPI_PAD_CONFIG_CLK,                              EFUSE_BLK1,  48,   6, [] SPI PAD CLK
-SPI_PAD_CONFIG_Q,                                EFUSE_BLK1,  54,   6, [] SPI PAD Q(D1)
-SPI_PAD_CONFIG_D,                                EFUSE_BLK1,  60,   6, [] SPI PAD D(D0)
-SPI_PAD_CONFIG_CS,                               EFUSE_BLK1,  66,   6, [] SPI PAD CS
-SPI_PAD_CONFIG_HD,                               EFUSE_BLK1,  72,   6, [] SPI PAD HD(D3)
-SPI_PAD_CONFIG_WP,                               EFUSE_BLK1,  78,   6, [] SPI PAD WP(D2)
-SPI_PAD_CONFIG_DQS,                              EFUSE_BLK1,  84,   6, [] SPI PAD DQS
-SPI_PAD_CONFIG_D4,                               EFUSE_BLK1,  90,   6, [] SPI PAD D4
-SPI_PAD_CONFIG_D5,                               EFUSE_BLK1,  96,   6, [] SPI PAD D5
-SPI_PAD_CONFIG_D6,                               EFUSE_BLK1, 102,   6, [] SPI PAD D6
-SPI_PAD_CONFIG_D7,                               EFUSE_BLK1, 108,   6, [] SPI PAD D7
-WAFER_VERSION_MINOR_LO,                          EFUSE_BLK1, 114,   3, [] WAFER_VERSION_MINOR least significant bits
-PKG_VERSION,                                     EFUSE_BLK1, 117,   3, [] Package version
-BLK_VERSION_MINOR,                               EFUSE_BLK1, 120,   3, [] BLK_VERSION_MINOR
-K_RTC_LDO,                                       EFUSE_BLK1, 135,   7, [] BLOCK1 K_RTC_LDO
-K_DIG_LDO,                                       EFUSE_BLK1, 142,   7, [] BLOCK1 K_DIG_LDO
-V_RTC_DBIAS20,                                   EFUSE_BLK1, 149,   8, [] BLOCK1 voltage of rtc dbias20
-V_DIG_DBIAS20,                                   EFUSE_BLK1, 157,   8, [] BLOCK1 voltage of digital dbias20
-DIG_DBIAS_HVT,                                   EFUSE_BLK1, 165,   5, [] BLOCK1 digital dbias when hvt
-THRES_HVT,                                       EFUSE_BLK1, 170,  10, [] BLOCK1 pvt threshold when hvt
-WAFER_VERSION_MINOR_HI,                          EFUSE_BLK1, 183,   1, [] WAFER_VERSION_MINOR most significant bit
-WAFER_VERSION_MAJOR,                             EFUSE_BLK1, 184,   2, [] WAFER_VERSION_MAJOR
-OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
-BLK_VERSION_MAJOR,                               EFUSE_BLK2, 128,   2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calibration"; 1: "With calibration"}
-TEMP_CALIB,                                      EFUSE_BLK2, 131,   9, [] Temperature calibration data
-OCODE,                                           EFUSE_BLK2, 140,   8, [] ADC OCode
-ADC1_INIT_CODE_ATTEN0,                           EFUSE_BLK2, 148,  10, [] ADC1 init code at atten0
-ADC1_INIT_CODE_ATTEN1,                           EFUSE_BLK2, 158,  10, [] ADC1 init code at atten1
-ADC1_INIT_CODE_ATTEN2,                           EFUSE_BLK2, 168,  10, [] ADC1 init code at atten2
-ADC1_INIT_CODE_ATTEN3,                           EFUSE_BLK2, 178,  10, [] ADC1 init code at atten3
-ADC1_CAL_VOL_ATTEN0,                             EFUSE_BLK2, 188,  10, [] ADC1 calibration voltage at atten0
-ADC1_CAL_VOL_ATTEN1,                             EFUSE_BLK2, 198,  10, [] ADC1 calibration voltage at atten1
-ADC1_CAL_VOL_ATTEN2,                             EFUSE_BLK2, 208,  10, [] ADC1 calibration voltage at atten2
-ADC1_CAL_VOL_ATTEN3,                             EFUSE_BLK2, 218,  10, [] ADC1 calibration voltage at atten3
-USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
-USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC address
-KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
-KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
-KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
-KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
-KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
-KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
-SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

esp-hal-common/devices/esp32c6/efuse.csv

@@ -1,181 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 709e8ea096e8a03a10006d40d5451a49
-
-WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
-WR_DIS.CRYPT_DPA_ENABLE,                         EFUSE_BLK0,   1,   1, [] wr_dis of CRYPT_DPA_ENABLE
-WR_DIS.SWAP_UART_SDIO_EN,                        EFUSE_BLK0,   2,   1, [] wr_dis of SWAP_UART_SDIO_EN
-WR_DIS.DIS_ICACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_ICACHE
-WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
-WR_DIS.DIS_DOWNLOAD_ICACHE,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_ICACHE
-WR_DIS.DIS_USB_SERIAL_JTAG,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_SERIAL_JTAG
-WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
-WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
-WR_DIS.JTAG_SEL_ENABLE,                          EFUSE_BLK0,   2,   1, [] wr_dis of JTAG_SEL_ENABLE
-WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_PAD_JTAG
-WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
-WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   3,   1, [] wr_dis of WDT_DELAY_SEL
-WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
-WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
-WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
-WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
-WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
-WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
-WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
-WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
-WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
-WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
-WR_DIS.SEC_DPA_LEVEL,                            EFUSE_BLK0,  14,   1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL
-WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
-WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
-WR_DIS.SPI_DOWNLOAD_MSPI_DIS,                    EFUSE_BLK0,  17,   1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
-WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
-WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
-WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DIRECT_BOOT
-WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
-WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
-WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
-WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,            EFUSE_BLK0,  19,   1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
-WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,  19,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
-WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  19,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
-WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
-WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.MAC_EXT,                                  EFUSE_BLK0,  20,   1, [] wr_dis of MAC_EXT
-WR_DIS.WAFER_VERSION_MINOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR
-WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR
-WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
-WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MINOR
-WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MAJOR
-WR_DIS.FLASH_CAP,                                EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_CAP
-WR_DIS.FLASH_TEMP,                               EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_TEMP
-WR_DIS.FLASH_VENDOR,                             EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_VENDOR
-WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
-WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
-WR_DIS.TEMP_CALIB,                               EFUSE_BLK0,  21,   1, [] wr_dis of TEMP_CALIB
-WR_DIS.OCODE,                                    EFUSE_BLK0,  21,   1, [] wr_dis of OCODE
-WR_DIS.ADC1_INIT_CODE_ATTEN0,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
-WR_DIS.ADC1_INIT_CODE_ATTEN1,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
-WR_DIS.ADC1_INIT_CODE_ATTEN2,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
-WR_DIS.ADC1_INIT_CODE_ATTEN3,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
-WR_DIS.ADC1_CAL_VOL_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
-WR_DIS.ADC1_CAL_VOL_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
-WR_DIS.ADC1_CAL_VOL_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
-WR_DIS.ADC1_CAL_VOL_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5
-WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6
-WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
-WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
-WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
-WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
-WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
-WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
-WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
-WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
-WR_DIS.VDD_SPI_AS_GPIO,                          EFUSE_BLK0,  30,   1, [] wr_dis of VDD_SPI_AS_GPIO
-WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
-RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
-RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
-RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
-RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
-RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
-RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
-RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
-RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
-SWAP_UART_SDIO_EN,                               EFUSE_BLK0,  39,   1, [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped
-DIS_ICACHE,                                      EFUSE_BLK0,  40,   1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
-DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
-DIS_DOWNLOAD_ICACHE,                             EFUSE_BLK0,  42,   1, [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled
-DIS_USB_SERIAL_JTAG,                             EFUSE_BLK0,  43,   1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
-DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
-SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  45,   1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
-DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
-JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
-SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
-DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
-USB_EXCHG_PINS,                                  EFUSE_BLK0,  57,   1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
-VDD_SPI_AS_GPIO,                                 EFUSE_BLK0,  58,   1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
-SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
-SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
-SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
-SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
-KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Represents the purpose of Key0
-KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Represents the purpose of Key1
-KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Represents the purpose of Key2
-KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Represents the purpose of Key3
-KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Represents the purpose of Key4
-KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Represents the purpose of Key5
-SEC_DPA_LEVEL,                                   EFUSE_BLK0, 112,   2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode
-CRYPT_DPA_ENABLE,                                EFUSE_BLK0, 114,   1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
-SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
-SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
-FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
-DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
-DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
-DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
-UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
-FORCE_SEND_RESUME,                               EFUSE_BLK0, 141,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
-SECURE_VERSION,                                  EFUSE_BLK0, 142,  16, [] Represents the version used by ESP-IDF anti-rollback feature
-SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 158,   1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
-DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK0, 160,   1, [] Disables check of wafer version major
-DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK0, 161,   1, [] Disables check of blk version major
-MAC_FACTORY,                                     EFUSE_BLK1,   0,  48, [MAC_FACTORY] MAC address
-MAC_EXT,                                         EFUSE_BLK1,  48,  16, [] Stores the extended bits of MAC address
-WAFER_VERSION_MINOR,                             EFUSE_BLK1, 114,   4, []
-WAFER_VERSION_MAJOR,                             EFUSE_BLK1, 118,   2, []
-PKG_VERSION,                                     EFUSE_BLK1, 120,   3, [] Package version
-BLK_VERSION_MINOR,                               EFUSE_BLK1, 123,   3, [] BLK_VERSION_MINOR of BLOCK2
-BLK_VERSION_MAJOR,                               EFUSE_BLK1, 126,   2, [] BLK_VERSION_MAJOR of BLOCK2
-FLASH_CAP,                                       EFUSE_BLK1, 128,   3, []
-FLASH_TEMP,                                      EFUSE_BLK1, 131,   2, []
-FLASH_VENDOR,                                    EFUSE_BLK1, 133,   3, []
-OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
-TEMP_CALIB,                                      EFUSE_BLK2, 128,   9, [] Temperature calibration data
-OCODE,                                           EFUSE_BLK2, 137,   8, [] ADC OCode
-ADC1_INIT_CODE_ATTEN0,                           EFUSE_BLK2, 145,  10, [] ADC1 init code at atten0
-ADC1_INIT_CODE_ATTEN1,                           EFUSE_BLK2, 155,  10, [] ADC1 init code at atten1
-ADC1_INIT_CODE_ATTEN2,                           EFUSE_BLK2, 165,  10, [] ADC1 init code at atten2
-ADC1_INIT_CODE_ATTEN3,                           EFUSE_BLK2, 175,  10, [] ADC1 init code at atten3
-ADC1_CAL_VOL_ATTEN0,                             EFUSE_BLK2, 185,  10, [] ADC1 calibration voltage at atten0
-ADC1_CAL_VOL_ATTEN1,                             EFUSE_BLK2, 195,  10, [] ADC1 calibration voltage at atten1
-ADC1_CAL_VOL_ATTEN2,                             EFUSE_BLK2, 205,  10, [] ADC1 calibration voltage at atten2
-ADC1_CAL_VOL_ATTEN3,                             EFUSE_BLK2, 215,  10, [] ADC1 calibration voltage at atten3
-ADC1_INIT_CODE_ATTEN0_CH0,                       EFUSE_BLK2, 225,   4, [] ADC1 init code at atten0 ch0
-ADC1_INIT_CODE_ATTEN0_CH1,                       EFUSE_BLK2, 229,   4, [] ADC1 init code at atten0 ch1
-ADC1_INIT_CODE_ATTEN0_CH2,                       EFUSE_BLK2, 233,   4, [] ADC1 init code at atten0 ch2
-ADC1_INIT_CODE_ATTEN0_CH3,                       EFUSE_BLK2, 237,   4, [] ADC1 init code at atten0 ch3
-ADC1_INIT_CODE_ATTEN0_CH4,                       EFUSE_BLK2, 241,   4, [] ADC1 init code at atten0 ch4
-ADC1_INIT_CODE_ATTEN0_CH5,                       EFUSE_BLK2, 245,   4, [] ADC1 init code at atten0 ch5
-ADC1_INIT_CODE_ATTEN0_CH6,                       EFUSE_BLK2, 249,   4, [] ADC1 init code at atten0 ch6
-USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
-USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
-KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
-KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
-KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
-KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
-KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
-KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
-SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

esp-hal-common/devices/esp32h2/efuse.csv

@@ -1,155 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 4df10f83de85f2d830b7c466aabb28e7
-
-WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
-WR_DIS.DIS_ICACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_ICACHE
-WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
-WR_DIS.POWERGLITCH_EN,                           EFUSE_BLK0,   2,   1, [] wr_dis of POWERGLITCH_EN
-WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
-WR_DIS.SPI_DOWNLOAD_MSPI_DIS,                    EFUSE_BLK0,   2,   1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
-WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
-WR_DIS.JTAG_SEL_ENABLE,                          EFUSE_BLK0,   2,   1, [] wr_dis of JTAG_SEL_ENABLE
-WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_PAD_JTAG
-WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
-WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   3,   1, [] wr_dis of WDT_DELAY_SEL
-WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
-WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
-WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
-WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
-WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
-WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
-WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
-WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
-WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
-WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
-WR_DIS.SEC_DPA_LEVEL,                            EFUSE_BLK0,  14,   1, [] wr_dis of SEC_DPA_LEVEL
-WR_DIS.CRYPT_DPA_ENABLE,                         EFUSE_BLK0,  14,   1, [] wr_dis of CRYPT_DPA_ENABLE
-WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
-WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
-WR_DIS.ECDSA_FORCE_USE_HARDWARE_K,               EFUSE_BLK0,  17,   1, [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K
-WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
-WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
-WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DIRECT_BOOT
-WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
-WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
-WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
-WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,            EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
-WR_DIS.HYS_EN_PAD0,                              EFUSE_BLK0,  19,   1, [] wr_dis of HYS_EN_PAD0
-WR_DIS.HYS_EN_PAD1,                              EFUSE_BLK0,  19,   1, [] wr_dis of HYS_EN_PAD1
-WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
-WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.MAC_EXT,                                  EFUSE_BLK0,  20,   1, [] wr_dis of MAC_EXT
-WR_DIS.RXIQ_VERSION,                             EFUSE_BLK0,  20,   1, [] wr_dis of RXIQ_VERSION
-WR_DIS.RXIQ_0,                                   EFUSE_BLK0,  20,   1, [] wr_dis of RXIQ_0
-WR_DIS.RXIQ_1,                                   EFUSE_BLK0,  20,   1, [] wr_dis of RXIQ_1
-WR_DIS.WAFER_VERSION_MINOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR
-WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR
-WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,  20,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
-WR_DIS.FLASH_CAP,                                EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_CAP
-WR_DIS.FLASH_TEMP,                               EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_TEMP
-WR_DIS.FLASH_VENDOR,                             EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_VENDOR
-WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
-WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
-WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
-WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MINOR
-WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MAJOR
-WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  21,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
-WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
-WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
-WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
-WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
-WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
-WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
-WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
-WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
-WR_DIS.VDD_SPI_AS_GPIO,                          EFUSE_BLK0,  30,   1, [] wr_dis of VDD_SPI_AS_GPIO
-WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
-RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
-RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
-RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
-RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
-RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
-RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
-RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
-RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
-DIS_ICACHE,                                      EFUSE_BLK0,  40,   1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
-DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
-POWERGLITCH_EN,                                  EFUSE_BLK0,  42,   1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
-DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
-SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  45,   1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
-DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
-JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
-DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
-USB_EXCHG_PINS,                                  EFUSE_BLK0,  57,   1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
-VDD_SPI_AS_GPIO,                                 EFUSE_BLK0,  58,   1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
-SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
-SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
-SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
-SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
-KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Represents the purpose of Key0
-KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Represents the purpose of Key1
-KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Represents the purpose of Key2
-KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Represents the purpose of Key3
-KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Represents the purpose of Key4
-KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Represents the purpose of Key5
-SEC_DPA_LEVEL,                                   EFUSE_BLK0, 112,   2, [] Represents the spa secure level by configuring the clock random divide mode
-ECDSA_FORCE_USE_HARDWARE_K,                      EFUSE_BLK0, 114,   1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
-CRYPT_DPA_ENABLE,                                EFUSE_BLK0, 115,   1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
-SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
-SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
-FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
-DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
-DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot
-DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
-UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
-FORCE_SEND_RESUME,                               EFUSE_BLK0, 136,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
-SECURE_VERSION,                                  EFUSE_BLK0, 137,  16, [] Represents the version used by ESP-IDF anti-rollback feature
-SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 153,   1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
-HYS_EN_PAD0,                                     EFUSE_BLK0, 154,   6, [] Set bits to enable hysteresis function of PAD0~5
-HYS_EN_PAD1,                                     EFUSE_BLK0, 160,  22, [] Set bits to enable hysteresis function of PAD6~27
-MAC_FACTORY,                                     EFUSE_BLK1,   0,  48, [MAC_FACTORY] MAC address
-MAC_EXT,                                         EFUSE_BLK1,  48,  16, [] Stores the extended bits of MAC address
-RXIQ_VERSION,                                    EFUSE_BLK1,  64,   3, [] RF Calibration data. RXIQ version
-RXIQ_0,                                          EFUSE_BLK1,  67,   7, [] RF Calibration data. RXIQ data 0
-RXIQ_1,                                          EFUSE_BLK1,  74,   7, [] RF Calibration data. RXIQ data 1
-WAFER_VERSION_MINOR,                             EFUSE_BLK1, 114,   3, []
-WAFER_VERSION_MAJOR,                             EFUSE_BLK1, 117,   2, []
-DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK1, 119,   1, [] Disables check of wafer version major
-FLASH_CAP,                                       EFUSE_BLK1, 120,   3, []
-FLASH_TEMP,                                      EFUSE_BLK1, 123,   2, []
-FLASH_VENDOR,                                    EFUSE_BLK1, 125,   3, []
-PKG_VERSION,                                     EFUSE_BLK1, 128,   3, [] Package version
-OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
-BLK_VERSION_MINOR,                               EFUSE_BLK2, 130,   3, [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
-BLK_VERSION_MAJOR,                               EFUSE_BLK2, 133,   2, [] BLK_VERSION_MAJOR of BLOCK2
-DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK2, 135,   1, [] Disables check of blk version major
-USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
-USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
-KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
-KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
-KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
-KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
-KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
-KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
-SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

esp-hal-common/devices/esp32s2/efuse.csv

@@ -1,207 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 888a61f6f500d9c7ee0aa32016b0bee7
-
-WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
-WR_DIS.DIS_ICACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_ICACHE
-WR_DIS.DIS_DCACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DCACHE
-WR_DIS.DIS_DOWNLOAD_ICACHE,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_ICACHE
-WR_DIS.DIS_DOWNLOAD_DCACHE,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_DCACHE
-WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
-WR_DIS.DIS_USB,                                  EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB
-WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
-WR_DIS.DIS_BOOT_REMAP,                           EFUSE_BLK0,   2,   1, [] wr_dis of DIS_BOOT_REMAP
-WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,   2,   1, [] wr_dis of SOFT_DIS_JTAG
-WR_DIS.HARD_DIS_JTAG,                            EFUSE_BLK0,   2,   1, [] wr_dis of HARD_DIS_JTAG
-WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
-WR_DIS.VDD_SPI_XPD,                              EFUSE_BLK0,   3,   1, [] wr_dis of VDD_SPI_XPD
-WR_DIS.VDD_SPI_TIEH,                             EFUSE_BLK0,   3,   1, [] wr_dis of VDD_SPI_TIEH
-WR_DIS.VDD_SPI_FORCE,                            EFUSE_BLK0,   3,   1, [] wr_dis of VDD_SPI_FORCE
-WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   3,   1, [] wr_dis of WDT_DELAY_SEL
-WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
-WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
-WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
-WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
-WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
-WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
-WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
-WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
-WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
-WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
-WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
-WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
-WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
-WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
-WR_DIS.DIS_LEGACY_SPI_BOOT,                      EFUSE_BLK0,  18,   1, [] wr_dis of DIS_LEGACY_SPI_BOOT
-WR_DIS.UART_PRINT_CHANNEL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CHANNEL
-WR_DIS.DIS_USB_DOWNLOAD_MODE,                    EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_DOWNLOAD_MODE
-WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
-WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
-WR_DIS.PIN_POWER_SELECTION,                      EFUSE_BLK0,  18,   1, [] wr_dis of PIN_POWER_SELECTION
-WR_DIS.FLASH_TYPE,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TYPE
-WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
-WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.SPI_PAD_CONFIG_CLK,                       EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_CLK
-WR_DIS.SPI_PAD_CONFIG_Q,                         EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_Q
-WR_DIS.SPI_PAD_CONFIG_D,                         EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D
-WR_DIS.SPI_PAD_CONFIG_CS,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_CS
-WR_DIS.SPI_PAD_CONFIG_HD,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_HD
-WR_DIS.SPI_PAD_CONFIG_WP,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_WP
-WR_DIS.SPI_PAD_CONFIG_DQS,                       EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_DQS
-WR_DIS.SPI_PAD_CONFIG_D4,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D4
-WR_DIS.SPI_PAD_CONFIG_D5,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D5
-WR_DIS.SPI_PAD_CONFIG_D6,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D6
-WR_DIS.SPI_PAD_CONFIG_D7,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D7
-WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR
-WR_DIS.WAFER_VERSION_MINOR_HI,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR_HI
-WR_DIS.FLASH_VERSION,                            EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_VERSION
-WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MAJOR
-WR_DIS.PSRAM_VERSION,                            EFUSE_BLK0,  20,   1, [] wr_dis of PSRAM_VERSION
-WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
-WR_DIS.WAFER_VERSION_MINOR_LO,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR_LO
-WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
-WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
-WR_DIS.ADC_CALIB,                                EFUSE_BLK0,  21,   1, [] wr_dis of ADC_CALIB
-WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MINOR
-WR_DIS.TEMP_CALIB,                               EFUSE_BLK0,  21,   1, [] wr_dis of TEMP_CALIB
-WR_DIS.RTCCALIB_V1IDX_A10H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A10H
-WR_DIS.RTCCALIB_V1IDX_A11H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A11H
-WR_DIS.RTCCALIB_V1IDX_A12H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A12H
-WR_DIS.RTCCALIB_V1IDX_A13H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A13H
-WR_DIS.RTCCALIB_V1IDX_A20H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A20H
-WR_DIS.RTCCALIB_V1IDX_A21H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A21H
-WR_DIS.RTCCALIB_V1IDX_A22H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A22H
-WR_DIS.RTCCALIB_V1IDX_A23H,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A23H
-WR_DIS.RTCCALIB_V1IDX_A10L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A10L
-WR_DIS.RTCCALIB_V1IDX_A11L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A11L
-WR_DIS.RTCCALIB_V1IDX_A12L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A12L
-WR_DIS.RTCCALIB_V1IDX_A13L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A13L
-WR_DIS.RTCCALIB_V1IDX_A20L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A20L
-WR_DIS.RTCCALIB_V1IDX_A21L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A21L
-WR_DIS.RTCCALIB_V1IDX_A22L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A22L
-WR_DIS.RTCCALIB_V1IDX_A23L,                      EFUSE_BLK0,  21,   1, [] wr_dis of RTCCALIB_V1IDX_A23L
-WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
-WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
-WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
-WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
-WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
-WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
-WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
-WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
-WR_DIS.USB_EXT_PHY_ENABLE,                       EFUSE_BLK0,  30,   1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
-WR_DIS.USB_FORCE_NOPERSIST,                      EFUSE_BLK0,  30,   1, [] wr_dis of USB_FORCE_NOPERSIST
-WR_DIS.BLOCK0_VERSION,                           EFUSE_BLK0,  30,   1, [] wr_dis of BLOCK0_VERSION
-RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
-RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
-RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
-RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
-RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
-RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
-RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
-RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
-DIS_ICACHE,                                      EFUSE_BLK0,  40,   1, [] Set this bit to disable Icache
-DIS_DCACHE,                                      EFUSE_BLK0,  41,   1, [] Set this bit to disable Dcache
-DIS_DOWNLOAD_ICACHE,                             EFUSE_BLK0,  42,   1, [] Disables Icache when SoC is in Download mode
-DIS_DOWNLOAD_DCACHE,                             EFUSE_BLK0,  43,   1, [] Disables Dcache when SoC is in Download mode
-DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Set this bit to disable the function that forces chip into download mode
-DIS_USB,                                         EFUSE_BLK0,  45,   1, [] Set this bit to disable USB OTG function
-DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [DIS_CAN] Set this bit to disable the TWAI Controller function
-DIS_BOOT_REMAP,                                  EFUSE_BLK0,  47,   1, [] Disables capability to Remap RAM to ROM address space
-SOFT_DIS_JTAG,                                   EFUSE_BLK0,  49,   1, [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral
-HARD_DIS_JTAG,                                   EFUSE_BLK0,  50,   1, [] Hardware disables JTAG permanently
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  51,   1, [] Disables flash encryption when in download boot modes
-USB_EXCHG_PINS,                                  EFUSE_BLK0,  56,   1, [] Set this bit to exchange USB D+ and D- pins
-USB_EXT_PHY_ENABLE,                              EFUSE_BLK0,  57,   1, [EXT_PHY_ENABLE] Set this bit to enable external USB PHY
-USB_FORCE_NOPERSIST,                             EFUSE_BLK0,  58,   1, [] If set; forces USB BVALID to 1
-BLOCK0_VERSION,                                  EFUSE_BLK0,  59,   2, [] BLOCK0 efuse version
-VDD_SPI_XPD,                                     EFUSE_BLK0,  68,   1, [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on
-VDD_SPI_TIEH,                                    EFUSE_BLK0,  69,   1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
-VDD_SPI_FORCE,                                   EFUSE_BLK0,  70,   1, [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
-SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
-SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
-SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
-SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
-KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Purpose of KEY0
-KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Purpose of KEY1
-KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Purpose of KEY2
-KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Purpose of KEY3
-KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Purpose of KEY4
-KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Purpose of KEY5
-SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Set this bit to enable secure boot
-SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Set this bit to enable aggressive secure boot key revocation mode
-FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Set this bit to disable all download boot modes
-DIS_LEGACY_SPI_BOOT,                             EFUSE_BLK0, 129,   1, [] Set this bit to disable Legacy SPI boot mode
-UART_PRINT_CHANNEL,                              EFUSE_BLK0, 130,   1, [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"}
-DIS_USB_DOWNLOAD_MODE,                           EFUSE_BLK0, 132,   1, [] Set this bit to disable use of USB OTG in UART download boot mode
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Set this bit to enable secure UART download mode (read/write flash only)
-UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
-PIN_POWER_SELECTION,                             EFUSE_BLK0, 136,   1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
-FLASH_TYPE,                                      EFUSE_BLK0, 137,   1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
-FORCE_SEND_RESUME,                               EFUSE_BLK0, 138,   1, [] If set; forces ROM code to send an SPI flash resume command during SPI boot
-SECURE_VERSION,                                  EFUSE_BLK0, 139,  16, [] Secure version (used by ESP-IDF anti-rollback feature)
-DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK0, 160,   1, [] Disables check of wafer version major
-DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK0, 161,   1, [] Disables check of blk version major
-MAC_FACTORY,                                     EFUSE_BLK1,   0,  48, [MAC_FACTORY] MAC address
-SPI_PAD_CONFIG_CLK,                              EFUSE_BLK1,  48,   6, [] SPI_PAD_configure CLK
-SPI_PAD_CONFIG_Q,                                EFUSE_BLK1,  54,   6, [] SPI_PAD_configure Q(D1)
-SPI_PAD_CONFIG_D,                                EFUSE_BLK1,  60,   6, [] SPI_PAD_configure D(D0)
-SPI_PAD_CONFIG_CS,                               EFUSE_BLK1,  66,   6, [] SPI_PAD_configure CS
-SPI_PAD_CONFIG_HD,                               EFUSE_BLK1,  72,   6, [] SPI_PAD_configure HD(D3)
-SPI_PAD_CONFIG_WP,                               EFUSE_BLK1,  78,   6, [] SPI_PAD_configure WP(D2)
-SPI_PAD_CONFIG_DQS,                              EFUSE_BLK1,  84,   6, [] SPI_PAD_configure DQS
-SPI_PAD_CONFIG_D4,                               EFUSE_BLK1,  90,   6, [] SPI_PAD_configure D4
-SPI_PAD_CONFIG_D5,                               EFUSE_BLK1,  96,   6, [] SPI_PAD_configure D5
-SPI_PAD_CONFIG_D6,                               EFUSE_BLK1, 102,   6, [] SPI_PAD_configure D6
-SPI_PAD_CONFIG_D7,                               EFUSE_BLK1, 108,   6, [] SPI_PAD_configure D7
-WAFER_VERSION_MAJOR,                             EFUSE_BLK1, 114,   2, [] WAFER_VERSION_MAJOR
-WAFER_VERSION_MINOR_HI,                          EFUSE_BLK1, 116,   1, [] WAFER_VERSION_MINOR most significant bit
-FLASH_VERSION,                                   EFUSE_BLK1, 117,   4, [] Flash version
-BLK_VERSION_MAJOR,                               EFUSE_BLK1, 121,   2, [] BLK_VERSION_MAJOR
-PSRAM_VERSION,                                   EFUSE_BLK1, 124,   4, [] PSRAM version
-PKG_VERSION,                                     EFUSE_BLK1, 128,   4, [] Package version
-WAFER_VERSION_MINOR_LO,                          EFUSE_BLK1, 132,   3, [] WAFER_VERSION_MINOR least significant bits
-OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
-ADC_CALIB,                                       EFUSE_BLK2, 128,   4, [] 4 bit of ADC calibration
-BLK_VERSION_MINOR,                               EFUSE_BLK2, 132,   3, [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"}
-TEMP_CALIB,                                      EFUSE_BLK2, 135,   9, [] Temperature calibration data
-RTCCALIB_V1IDX_A10H,                             EFUSE_BLK2, 144,   8, []
-RTCCALIB_V1IDX_A11H,                             EFUSE_BLK2, 152,   8, []
-RTCCALIB_V1IDX_A12H,                             EFUSE_BLK2, 160,   8, []
-RTCCALIB_V1IDX_A13H,                             EFUSE_BLK2, 168,   8, []
-RTCCALIB_V1IDX_A20H,                             EFUSE_BLK2, 176,   8, []
-RTCCALIB_V1IDX_A21H,                             EFUSE_BLK2, 184,   8, []
-RTCCALIB_V1IDX_A22H,                             EFUSE_BLK2, 192,   8, []
-RTCCALIB_V1IDX_A23H,                             EFUSE_BLK2, 200,   8, []
-RTCCALIB_V1IDX_A10L,                             EFUSE_BLK2, 208,   6, []
-RTCCALIB_V1IDX_A11L,                             EFUSE_BLK2, 214,   6, []
-RTCCALIB_V1IDX_A12L,                             EFUSE_BLK2, 220,   6, []
-RTCCALIB_V1IDX_A13L,                             EFUSE_BLK2, 226,   6, []
-RTCCALIB_V1IDX_A20L,                             EFUSE_BLK2, 232,   6, []
-RTCCALIB_V1IDX_A21L,                             EFUSE_BLK2, 238,   6, []
-RTCCALIB_V1IDX_A22L,                             EFUSE_BLK2, 244,   6, []
-RTCCALIB_V1IDX_A23L,                             EFUSE_BLK2, 250,   6, []
-USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
-USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
-KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
-KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
-KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
-KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
-KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
-KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
-SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

esp-hal-common/devices/esp32s3/efuse.csv

@@ -1,227 +0,0 @@
-
-# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
-#                   |     EFUSE_BLK1  |            |            |        #
-#                   |        ...)     |            |            |        #
-##########################################################################
-# !!!!!!!!!!! #
-# After editing this file, run the command manually "idf.py efuse-common-table"
-# this will generate new source files, next rebuild all the sources.
-# !!!!!!!!!!! #
-
-# This file was generated by regtools.py based on the efuses.yaml file with the version: 6925129eca795b8b087d31be539740ec
-
-WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
-WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
-WR_DIS.DIS_ICACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_ICACHE
-WR_DIS.DIS_DCACHE,                               EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DCACHE
-WR_DIS.DIS_DOWNLOAD_ICACHE,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_ICACHE
-WR_DIS.DIS_DOWNLOAD_DCACHE,                      EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_DCACHE
-WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
-WR_DIS.DIS_USB_OTG,                              EFUSE_BLK0,   2,   1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG
-WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
-WR_DIS.DIS_APP_CPU,                              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_APP_CPU
-WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG
-WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
-WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
-WR_DIS.DIS_USB_SERIAL_JTAG,                      EFUSE_BLK0,   2,   1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG
-WR_DIS.STRAP_JTAG_SEL,                           EFUSE_BLK0,   2,   1, [] wr_dis of STRAP_JTAG_SEL
-WR_DIS.USB_PHY_SEL,                              EFUSE_BLK0,   2,   1, [] wr_dis of USB_PHY_SEL
-WR_DIS.VDD_SPI_XPD,                              EFUSE_BLK0,   3,   1, [] wr_dis of VDD_SPI_XPD
-WR_DIS.VDD_SPI_TIEH,                             EFUSE_BLK0,   3,   1, [] wr_dis of VDD_SPI_TIEH
-WR_DIS.VDD_SPI_FORCE,                            EFUSE_BLK0,   3,   1, [] wr_dis of VDD_SPI_FORCE
-WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,   3,   1, [] wr_dis of WDT_DELAY_SEL
-WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
-WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
-WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
-WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
-WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
-WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
-WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
-WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
-WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
-WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
-WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
-WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
-WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
-WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
-WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT
-WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
-WR_DIS.FLASH_ECC_MODE,                           EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_ECC_MODE
-WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
-WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
-WR_DIS.PIN_POWER_SELECTION,                      EFUSE_BLK0,  18,   1, [] wr_dis of PIN_POWER_SELECTION
-WR_DIS.FLASH_TYPE,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TYPE
-WR_DIS.FLASH_PAGE_SIZE,                          EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_PAGE_SIZE
-WR_DIS.FLASH_ECC_EN,                             EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_ECC_EN
-WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
-WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
-WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE,                EFUSE_BLK0,  19,   1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
-WR_DIS.DISABLE_WAFER_VERSION_MAJOR,              EFUSE_BLK0,  19,   1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
-WR_DIS.DISABLE_BLK_VERSION_MAJOR,                EFUSE_BLK0,  19,   1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
-WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
-WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
-WR_DIS.SPI_PAD_CONFIG_CLK,                       EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_CLK
-WR_DIS.SPI_PAD_CONFIG_Q,                         EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_Q
-WR_DIS.SPI_PAD_CONFIG_D,                         EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D
-WR_DIS.SPI_PAD_CONFIG_CS,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_CS
-WR_DIS.SPI_PAD_CONFIG_HD,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_HD
-WR_DIS.SPI_PAD_CONFIG_WP,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_WP
-WR_DIS.SPI_PAD_CONFIG_DQS,                       EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_DQS
-WR_DIS.SPI_PAD_CONFIG_D4,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D4
-WR_DIS.SPI_PAD_CONFIG_D5,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D5
-WR_DIS.SPI_PAD_CONFIG_D6,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D6
-WR_DIS.SPI_PAD_CONFIG_D7,                        EFUSE_BLK0,  20,   1, [] wr_dis of SPI_PAD_CONFIG_D7
-WR_DIS.WAFER_VERSION_MINOR_LO,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR_LO
-WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
-WR_DIS.BLK_VERSION_MINOR,                        EFUSE_BLK0,  20,   1, [] wr_dis of BLK_VERSION_MINOR
-WR_DIS.K_RTC_LDO,                                EFUSE_BLK0,  20,   1, [] wr_dis of K_RTC_LDO
-WR_DIS.K_DIG_LDO,                                EFUSE_BLK0,  20,   1, [] wr_dis of K_DIG_LDO
-WR_DIS.V_RTC_DBIAS20,                            EFUSE_BLK0,  20,   1, [] wr_dis of V_RTC_DBIAS20
-WR_DIS.V_DIG_DBIAS20,                            EFUSE_BLK0,  20,   1, [] wr_dis of V_DIG_DBIAS20
-WR_DIS.DIG_DBIAS_HVT,                            EFUSE_BLK0,  20,   1, [] wr_dis of DIG_DBIAS_HVT
-WR_DIS.WAFER_VERSION_MINOR_HI,                   EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MINOR_HI
-WR_DIS.WAFER_VERSION_MAJOR,                      EFUSE_BLK0,  20,   1, [] wr_dis of WAFER_VERSION_MAJOR
-WR_DIS.ADC2_CAL_VOL_ATTEN3,                      EFUSE_BLK0,  20,   1, [] wr_dis of ADC2_CAL_VOL_ATTEN3
-WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
-WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
-WR_DIS.BLK_VERSION_MAJOR,                        EFUSE_BLK0,  21,   1, [] wr_dis of BLK_VERSION_MAJOR
-WR_DIS.TEMP_CALIB,                               EFUSE_BLK0,  21,   1, [] wr_dis of TEMP_CALIB
-WR_DIS.OCODE,                                    EFUSE_BLK0,  21,   1, [] wr_dis of OCODE
-WR_DIS.ADC1_INIT_CODE_ATTEN0,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
-WR_DIS.ADC1_INIT_CODE_ATTEN1,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
-WR_DIS.ADC1_INIT_CODE_ATTEN2,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
-WR_DIS.ADC1_INIT_CODE_ATTEN3,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
-WR_DIS.ADC2_INIT_CODE_ATTEN0,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_INIT_CODE_ATTEN0
-WR_DIS.ADC2_INIT_CODE_ATTEN1,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_INIT_CODE_ATTEN1
-WR_DIS.ADC2_INIT_CODE_ATTEN2,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_INIT_CODE_ATTEN2
-WR_DIS.ADC2_INIT_CODE_ATTEN3,                    EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_INIT_CODE_ATTEN3
-WR_DIS.ADC1_CAL_VOL_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
-WR_DIS.ADC1_CAL_VOL_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
-WR_DIS.ADC1_CAL_VOL_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
-WR_DIS.ADC1_CAL_VOL_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
-WR_DIS.ADC2_CAL_VOL_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_CAL_VOL_ATTEN0
-WR_DIS.ADC2_CAL_VOL_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_CAL_VOL_ATTEN1
-WR_DIS.ADC2_CAL_VOL_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_CAL_VOL_ATTEN2
-WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
-WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
-WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
-WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
-WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
-WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
-WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
-WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
-WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
-WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
-WR_DIS.USB_EXT_PHY_ENABLE,                       EFUSE_BLK0,  30,   1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
-WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
-RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
-RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
-RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
-RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
-RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
-RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
-RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
-RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
-DIS_ICACHE,                                      EFUSE_BLK0,  40,   1, [] Set this bit to disable Icache
-DIS_DCACHE,                                      EFUSE_BLK0,  41,   1, [] Set this bit to disable Dcache
-DIS_DOWNLOAD_ICACHE,                             EFUSE_BLK0,  42,   1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
-DIS_DOWNLOAD_DCACHE,                             EFUSE_BLK0,  43,   1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
-DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Set this bit to disable the function that forces chip into download mode
-DIS_USB_OTG,                                     EFUSE_BLK0,  45,   1, [DIS_USB] Set this bit to disable USB function
-DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [DIS_CAN] Set this bit to disable CAN function
-DIS_APP_CPU,                                     EFUSE_BLK0,  47,   1, [] Disable app cpu
-SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
-DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
-DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Set this bit to disable flash encryption when in download boot modes
-USB_EXCHG_PINS,                                  EFUSE_BLK0,  57,   1, [] Set this bit to exchange USB D+ and D- pins
-USB_EXT_PHY_ENABLE,                              EFUSE_BLK0,  58,   1, [EXT_PHY_ENABLE] Set this bit to enable external PHY
-VDD_SPI_XPD,                                     EFUSE_BLK0,  68,   1, [] SPI regulator power up signal
-VDD_SPI_TIEH,                                    EFUSE_BLK0,  69,   1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
-VDD_SPI_FORCE,                                   EFUSE_BLK0,  70,   1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI
-WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
-SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
-SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
-SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
-SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
-KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Purpose of Key0
-KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Purpose of Key1
-KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Purpose of Key2
-KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Purpose of Key3
-KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Purpose of Key4
-KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Purpose of Key5
-SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Set this bit to enable secure boot
-SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Set this bit to enable revoking aggressive secure boot
-DIS_USB_JTAG,                                    EFUSE_BLK0, 118,   1, [] Set this bit to disable function of usb switch to jtag in module of usb device
-DIS_USB_SERIAL_JTAG,                             EFUSE_BLK0, 119,   1, [DIS_USB_DEVICE] Set this bit to disable usb device
-STRAP_JTAG_SEL,                                  EFUSE_BLK0, 120,   1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
-USB_PHY_SEL,                                     EFUSE_BLK0, 121,   1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}
-FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value.  Otherwise; the waiting time is twice the configurable value
-DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
-DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode
-DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}
-FLASH_ECC_MODE,                                  EFUSE_BLK0, 131,   1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"}
-DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB
-ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Set this bit to enable secure UART download mode
-UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
-PIN_POWER_SELECTION,                             EFUSE_BLK0, 136,   1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
-FLASH_TYPE,                                      EFUSE_BLK0, 137,   1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
-FLASH_PAGE_SIZE,                                 EFUSE_BLK0, 138,   2, [] Set Flash page size
-FLASH_ECC_EN,                                    EFUSE_BLK0, 140,   1, [] Set 1 to enable ECC for flash boot
-FORCE_SEND_RESUME,                               EFUSE_BLK0, 141,   1, [] Set this bit to force ROM code to send a resume command during SPI boot
-SECURE_VERSION,                                  EFUSE_BLK0, 142,  16, [] Secure version (used by ESP-IDF anti-rollback feature)
-DIS_USB_OTG_DOWNLOAD_MODE,                       EFUSE_BLK0, 159,   1, [] Set this bit to disable download through USB-OTG
-DISABLE_WAFER_VERSION_MAJOR,                     EFUSE_BLK0, 160,   1, [] Disables check of wafer version major
-DISABLE_BLK_VERSION_MAJOR,                       EFUSE_BLK0, 161,   1, [] Disables check of blk version major
-MAC_FACTORY,                                     EFUSE_BLK1,   0,  48, [MAC_FACTORY] MAC address
-SPI_PAD_CONFIG_CLK,                              EFUSE_BLK1,  48,   6, [] SPI_PAD_configure CLK
-SPI_PAD_CONFIG_Q,                                EFUSE_BLK1,  54,   6, [] SPI_PAD_configure Q(D1)
-SPI_PAD_CONFIG_D,                                EFUSE_BLK1,  60,   6, [] SPI_PAD_configure D(D0)
-SPI_PAD_CONFIG_CS,                               EFUSE_BLK1,  66,   6, [] SPI_PAD_configure CS
-SPI_PAD_CONFIG_HD,                               EFUSE_BLK1,  72,   6, [] SPI_PAD_configure HD(D3)
-SPI_PAD_CONFIG_WP,                               EFUSE_BLK1,  78,   6, [] SPI_PAD_configure WP(D2)
-SPI_PAD_CONFIG_DQS,                              EFUSE_BLK1,  84,   6, [] SPI_PAD_configure DQS
-SPI_PAD_CONFIG_D4,                               EFUSE_BLK1,  90,   6, [] SPI_PAD_configure D4
-SPI_PAD_CONFIG_D5,                               EFUSE_BLK1,  96,   6, [] SPI_PAD_configure D5
-SPI_PAD_CONFIG_D6,                               EFUSE_BLK1, 102,   6, [] SPI_PAD_configure D6
-SPI_PAD_CONFIG_D7,                               EFUSE_BLK1, 108,   6, [] SPI_PAD_configure D7
-WAFER_VERSION_MINOR_LO,                          EFUSE_BLK1, 114,   3, [] WAFER_VERSION_MINOR least significant bits
-PKG_VERSION,                                     EFUSE_BLK1, 117,   3, [] Package version
-BLK_VERSION_MINOR,                               EFUSE_BLK1, 120,   3, [] BLK_VERSION_MINOR
-K_RTC_LDO,                                       EFUSE_BLK1, 141,   7, [] BLOCK1 K_RTC_LDO
-K_DIG_LDO,                                       EFUSE_BLK1, 148,   7, [] BLOCK1 K_DIG_LDO
-V_RTC_DBIAS20,                                   EFUSE_BLK1, 155,   8, [] BLOCK1 voltage of rtc dbias20
-V_DIG_DBIAS20,                                   EFUSE_BLK1, 163,   8, [] BLOCK1 voltage of digital dbias20
-DIG_DBIAS_HVT,                                   EFUSE_BLK1, 171,   5, [] BLOCK1 digital dbias when hvt
-WAFER_VERSION_MINOR_HI,                          EFUSE_BLK1, 183,   1, [] WAFER_VERSION_MINOR most significant bit
-WAFER_VERSION_MAJOR,                             EFUSE_BLK1, 184,   2, [] WAFER_VERSION_MAJOR
-ADC2_CAL_VOL_ATTEN3,                             EFUSE_BLK1, 186,   6, [] ADC2 calibration voltage at atten3
-OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
-BLK_VERSION_MAJOR,                               EFUSE_BLK2, 128,   2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"}
-TEMP_CALIB,                                      EFUSE_BLK2, 132,   9, [] Temperature calibration data
-OCODE,                                           EFUSE_BLK2, 141,   8, [] ADC OCode
-ADC1_INIT_CODE_ATTEN0,                           EFUSE_BLK2, 149,   8, [] ADC1 init code at atten0
-ADC1_INIT_CODE_ATTEN1,                           EFUSE_BLK2, 157,   6, [] ADC1 init code at atten1
-ADC1_INIT_CODE_ATTEN2,                           EFUSE_BLK2, 163,   6, [] ADC1 init code at atten2
-ADC1_INIT_CODE_ATTEN3,                           EFUSE_BLK2, 169,   6, [] ADC1 init code at atten3
-ADC2_INIT_CODE_ATTEN0,                           EFUSE_BLK2, 175,   8, [] ADC2 init code at atten0
-ADC2_INIT_CODE_ATTEN1,                           EFUSE_BLK2, 183,   6, [] ADC2 init code at atten1
-ADC2_INIT_CODE_ATTEN2,                           EFUSE_BLK2, 189,   6, [] ADC2 init code at atten2
-ADC2_INIT_CODE_ATTEN3,                           EFUSE_BLK2, 195,   6, [] ADC2 init code at atten3
-ADC1_CAL_VOL_ATTEN0,                             EFUSE_BLK2, 201,   8, [] ADC1 calibration voltage at atten0
-ADC1_CAL_VOL_ATTEN1,                             EFUSE_BLK2, 209,   8, [] ADC1 calibration voltage at atten1
-ADC1_CAL_VOL_ATTEN2,                             EFUSE_BLK2, 217,   8, [] ADC1 calibration voltage at atten2
-ADC1_CAL_VOL_ATTEN3,                             EFUSE_BLK2, 225,   8, [] ADC1 calibration voltage at atten3
-ADC2_CAL_VOL_ATTEN0,                             EFUSE_BLK2, 233,   8, [] ADC2 calibration voltage at atten0
-ADC2_CAL_VOL_ATTEN1,                             EFUSE_BLK2, 241,   7, [] ADC2 calibration voltage at atten1
-ADC2_CAL_VOL_ATTEN2,                             EFUSE_BLK2, 248,   7, [] ADC2 calibration voltage at atten2
-USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
-USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
-KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
-KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
-KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
-KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
-KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
-KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
-SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

esp-hal-common/ld/esp32/rom-functions.x

@@ -1,29 +0,0 @@
-PROVIDE(ets_delay_us = 0x40008534);
-PROVIDE(ets_update_cpu_frequency_rom = 0x40008550);
-PROVIDE(rom_i2c_writeReg = 0x400041a4);
-PROVIDE(rom_i2c_writeReg_Mask = 0x400041fc);
-PROVIDE(rtc_get_reset_reason = 0x400081d4);
-PROVIDE(software_reset = 0x4000824c);
-PROVIDE(software_reset_cpu = 0x40008264);
-
-PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );
-PROVIDE ( esp_rom_efuse_get_flash_gpio_info    = ets_efuse_get_spiconfig );
-PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
-PROVIDE ( gpio_matrix_out = 0x40009f0c );
-PROVIDE ( gpio_matrix_in = 0x40009edc );
-PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
-PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
-PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );
-PROVIDE ( g_rom_flashchip = 0x3ffae270 );
-PROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );
-
-PROVIDE (esp_rom_crc32_be = 0x4005d024);
-PROVIDE (esp_rom_crc16_be = 0x4005d09c);
-PROVIDE (esp_rom_crc8_be = 0x4005d114);
-PROVIDE (esp_rom_crc32_le = 0x4005cfec);
-PROVIDE (esp_rom_crc16_le = 0x4005d05c);
-PROVIDE (esp_rom_crc8_le = 0x4005d0e0);
-
-PROVIDE (esp_rom_md5_init   = 0x4005da7c);
-PROVIDE (esp_rom_md5_update = 0x4005da9c);
-PROVIDE (esp_rom_md5_final  = 0x4005db1c);

esp-hal-common/ld/esp32c2/rom-functions.x

@@ -1,18 +0,0 @@
-PROVIDE(ets_delay_us = 0x40000044);
-PROVIDE(ets_update_cpu_frequency_rom = 0x40000774);
-PROVIDE(rom_i2c_writeReg = 0x400022f4);
-PROVIDE(rom_i2c_writeReg_Mask = 0x400022fc);
-PROVIDE(rtc_get_reset_reason = 0x40000018);
-PROVIDE(software_reset = 0x40000088);
-PROVIDE(software_reset_cpu = 0x4000008c);
-
-PROVIDE(esp_rom_crc32_be = 0x40000808);
-PROVIDE(esp_rom_crc16_be = 0x4000080c);
-PROVIDE(esp_rom_crc8_be = 0x40000810);
-PROVIDE(esp_rom_crc32_le = 0x400007fc);
-PROVIDE(esp_rom_crc16_le = 0x40000800);
-PROVIDE(esp_rom_crc8_le = 0x40000804);
-
-PROVIDE(esp_rom_mbedtls_md5_starts_ret = 0x40002be4);
-PROVIDE(esp_rom_mbedtls_md5_update_ret = 0x40002be8);
-PROVIDE(esp_rom_mbedtls_md5_finish_ret = 0x40002bec);

esp-hal-common/ld/esp32c3/rom-functions.x

@@ -1,25 +0,0 @@
-ets_printf = 0x40000040;
-PROVIDE(esp_rom_printf = ets_printf);
-PROVIDE(cache_invalidate_icache_all = 0x400004d8);
-PROVIDE(cache_suspend_icache = 0x40000524);
-PROVIDE(cache_resume_icache = 0x40000528);
-PROVIDE(cache_ibus_mmu_set = 0x40000560);
-PROVIDE(cache_dbus_mmu_set = 0x40000564);
-PROVIDE(ets_delay_us = 0x40000050);
-PROVIDE(ets_update_cpu_frequency_rom = 0x40000588);
-PROVIDE(rom_i2c_writeReg = 0x4000195c);
-PROVIDE(rom_i2c_writeReg_Mask = 0x40001960);
-PROVIDE(rtc_get_reset_reason = 0x40000018);
-PROVIDE(software_reset = 0x40000090);
-PROVIDE(software_reset_cpu = 0x40000094);
-
-PROVIDE(esp_rom_crc32_be = 0x4000062c);
-PROVIDE(esp_rom_crc16_be = 0x40000634);
-PROVIDE(esp_rom_crc8_be = 0x4000063c);
-PROVIDE(esp_rom_crc32_le = 0x40000628);
-PROVIDE(esp_rom_crc16_le = 0x40000630);
-PROVIDE(esp_rom_crc8_le = 0x40000638);
-
-PROVIDE(esp_rom_md5_init = 0x40000614);
-PROVIDE(esp_rom_md5_update = 0x40000618);
-PROVIDE(esp_rom_md5_final = 0x4000061c);

esp-hal-common/ld/esp32c6/rom-functions.x

@@ -1,25 +0,0 @@
-ets_printf = 0x40000028;
-ets_update_cpu_frequency = ets_update_cpu_frequency_rom;
-PROVIDE(esp_rom_printf = ets_printf);
-PROVIDE(cache_invalidate_icache_all = 0x4000064c);
-PROVIDE(cache_suspend_icache = 0x40000698);
-PROVIDE(cache_resume_icache = 0x4000069c);
-/* TODO PROVIDE(cache_ibus_mmu_set = 0x40000560); */
-/* TODO PROVIDE(cache_dbus_mmu_set = 0x40000564); */
-PROVIDE(ets_delay_us = 0x40000040);
-PROVIDE(ets_update_cpu_frequency_rom = 0x40000048);
-PROVIDE(rtc_get_reset_reason = 0x40000018);
-ets_update_cpu_frequency = 0x40000048;
-PROVIDE(software_reset = 0x40000090);
-PROVIDE(software_reset_cpu = 0x40000094);
-
-PROVIDE(esp_rom_crc32_be = 0x40000764);
-PROVIDE(esp_rom_crc16_be = 0x40000768);
-PROVIDE(esp_rom_crc8_be = 0x4000076c);
-PROVIDE(esp_rom_crc32_le = 0x40000758);
-PROVIDE(esp_rom_crc16_le = 0x4000075c);
-PROVIDE(esp_rom_crc8_le = 0x40000760);
-
-PROVIDE(esp_rom_md5_init = 0x4000074c);
-PROVIDE(esp_rom_md5_update = 0x40000750);
-PROVIDE(esp_rom_md5_final = 0x40000754);

esp-hal-common/ld/esp32h2/rom-functions.x

@@ -1,25 +0,0 @@
-ets_printf = 0x40000028;
-ets_update_cpu_frequency = ets_update_cpu_frequency_rom;
-PROVIDE(esp_rom_printf = ets_printf);
-PROVIDE(cache_invalidate_icache_all = 0x40000620);
-PROVIDE(cache_suspend_icache = 0x4000066c);
-PROVIDE(cache_resume_icache = 0x40000670);
-/* TODO PROVIDE(cache_ibus_mmu_set = 0x40000560); */
-/* TODO PROVIDE(cache_dbus_mmu_set = 0x40000564); */
-PROVIDE(ets_delay_us = 0x40000040);
-PROVIDE(ets_update_cpu_frequency_rom = 0x40000048);
-PROVIDE(rtc_get_reset_reason = 0x40000018);
-ets_update_cpu_frequency = 0x40000048;
-PROVIDE(software_reset = 0x40000090);
-PROVIDE(software_reset_cpu = 0x40000094);
-
-PROVIDE(esp_rom_crc32_be = 0x40000730);
-PROVIDE(esp_rom_crc16_be = 0x40000734);
-PROVIDE(esp_rom_crc8_be = 0x40000738);
-PROVIDE(esp_rom_crc32_le = 0x40000724);
-PROVIDE(esp_rom_crc16_le = 0x40000728);
-PROVIDE(esp_rom_crc8_le = 0x4000072c);
-
-PROVIDE(esp_rom_md5_init = 0x40000718);
-PROVIDE(esp_rom_md5_update = 0x4000071c);
-PROVIDE(esp_rom_md5_final = 0x40000720);

esp-hal-common/ld/esp32s2/rom-functions.x

@@ -1,29 +0,0 @@
-PROVIDE(ets_delay_us = 0x4000d888);
-PROVIDE(ets_update_cpu_frequency_rom = 0x4000d8a4);
-PROVIDE(rom_i2c_writeReg = 0x4000a9a8);
-PROVIDE(rom_i2c_writeReg_Mask = 0x4000aa00);
-PROVIDE(rtc_get_reset_reason = 0x4000ff58);
-PROVIDE(software_reset = 0x40010068);
-PROVIDE(software_reset_cpu = 0x40010080);
-
-PROVIDE ( cache_dbus_mmu_set = 0x40018eb0 );
-PROVIDE ( Cache_Allocate_SRAM = 0x40018d6c );
-PROVIDE ( Cache_Invalidate_DCache_All = 0x4001842c );
-PROVIDE ( Cache_Set_DCache_Mode = 0x40018074 );
-PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 );
-PROVIDE ( esp_rom_efuse_get_flash_gpio_info    = ets_efuse_get_spiconfig );
-PROVIDE ( esp_rom_efuse_get_flash_wp_gpio      = ets_efuse_get_wp_pad );
-PROVIDE ( ets_efuse_get_wp_pad = 0x4000e444 );
-PROVIDE ( esp_rom_spiflash_select_qio_pins = SelectSpiQIO );
-PROVIDE ( SelectSpiQIO = 0x40015b88 );
-PROVIDE ( esp_rom_spi_set_op_mode = 0x400179e8 );
-PROVIDE ( esp_rom_spi_cmd_start = 0x40017ba8 );
-PROVIDE ( esp_rom_spi_cmd_config = 0x40017c58 );
-
-PROVIDE(esp_rom_crc32_le = 0x400119dc);
-PROVIDE(esp_rom_crc16_le = 0x40011a10);
-PROVIDE(esp_rom_crc8_le = 0x40011a4c);
-
-PROVIDE(esp_rom_md5_final = 0x4000530c);
-PROVIDE(esp_rom_md5_init = 0x4000526c);
-PROVIDE(esp_rom_md5_update = 0x4000528c);

esp-hal-common/ld/esp32s3/rom-functions.x

@@ -1,36 +0,0 @@
-PROVIDE(ets_delay_us = 0x40000600);
-PROVIDE(ets_update_cpu_frequency_rom = 0x40043164);
-PROVIDE(rom_i2c_writeReg = 0x40005d60);
-PROVIDE(rom_i2c_writeReg_Mask = 0x40005d6c);
-PROVIDE(rtc_get_reset_reason = 0x4000057c);
-PROVIDE(rom_config_instruction_cache_mode = 0x40001a1c);
-PROVIDE(software_reset = 0x400006d8);
-PROVIDE(software_reset_cpu = 0x400006e4);
-PROVIDE(cache_dbus_mmu_set = 0x400019b0);
-PROVIDE(ets_efuse_get_spiconfig = 0x40001f74);
-PROVIDE(esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig);
-PROVIDE(esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad);
-PROVIDE(esp_rom_spiflash_select_qio_pins = 0x40000a68 );
-PROVIDE(esp_rom_spi_set_op_mode = 0x400008a0 );
-PROVIDE(esp_rom_spi_cmd_start = 0x40000888);
-PROVIDE(esp_rom_spi_cmd_config = 0x4000087c);
-PROVIDE(Cache_Suspend_DCache = 0x400018b4 );
-PROVIDE(Cache_Resume_DCache = 0x400018c0 );
-PROVIDE(rom_config_data_cache_mode = 0x40001a28 );
-PROVIDE(rom_config_instruction_cache_mode = 0x40001a1c );
-PROVIDE(ets_efuse_get_wp_pad = 0x40001fa4);
-
-PROVIDE(esp_rom_crc32_be = 0x40001ca4);
-PROVIDE(esp_rom_crc16_be = 0x40001cbc);
-PROVIDE(esp_rom_crc8_be = 0x40001cd4);
-PROVIDE(esp_rom_crc32_le = 0x40001c98);
-PROVIDE(esp_rom_crc16_le = 0x40001cb0);
-PROVIDE(esp_rom_crc8_le = 0x40001cc8);
-
-PROVIDE(esp_rom_md5_init = 0x40001c5c);
-PROVIDE(esp_rom_md5_update = 0x40001c68);
-PROVIDE(esp_rom_md5_final = 0x40001c74);
-
-PROVIDE (esp_rom_opiflash_exec_cmd = 0x400008b8);
-PROVIDE( esp_rom_spi_set_dtr_swap_mode = 0x4000093c );
-PROVIDE( esp_rom_opiflash_pin_config = 0x40000894 );

esp-hal-common/ld/sections/text.x

@@ -1,10 +0,0 @@
-
-
-SECTIONS {
-
-  .text : ALIGN(4)
-  {
-    *(.literal .text .literal.* .text.*)
-  } > ROTEXT
-
-}

esp-hal-common/src/aes/mod.rs

@@ -1,563 +0,0 @@
-//! # Advanced Encryption Standard (AES) support.
-//!
-//! ## Overview
-//!
-//! The AES module provides an interface to interact with the AES peripheral,
-//! provides encryption and decryption capabilities for ESP chips using the AES
-//! algorithm. We currently support the following AES encryption modes:
-//!
-//! * AES-128
-//! * AES-192
-//! * AES-256
-//!
-//! ## Example
-//!
-//! ### Initialization
-//!
-//! ```no_run
-//! let mut aes = Aes::new(peripherals.AES);
-//! ```
-//!
-//! ### Creating key and block Buffer
-//!
-//! ```no_run
-//! let keytext = "SUp4SeCp@sSw0rd".as_bytes();
-//! let plaintext = "message".as_bytes();
-//!
-//! // create an array with aes128 key size
-//! let mut keybuf = [0_u8; 16];
-//! keybuf[..keytext.len()].copy_from_slice(keytext);
-//!
-//! // create an array with aes block size
-//! let mut block_buf = [0_u8; 16];
-//! block_buf[..plaintext.len()].copy_from_slice(plaintext);
-//! ```
-//!
-//! ### Encrypting and Decrypting (using hardware)
-//!
-//! ```no_run
-//! let mut block = block_buf.clone();
-//! aes.process(&mut block, Mode::Encryption128, &keybuf);
-//! let hw_encrypted = block.clone();
-//!
-//! aes.process(&mut block, Mode::Decryption128, &keybuf);
-//! let hw_decrypted = block;
-//! ```
-//!
-//! ### Encrypting and Decrypting (using software)
-//!
-//! ```no_run
-//! let key = GenericArray::from(keybuf);
-//!
-//! let mut block = GenericArray::from(block_buf);
-//! let cipher = Aes128SW::new(&key);
-//! cipher.encrypt_block(&mut block);
-//!
-//! let sw_encrypted = block.clone();
-//! cipher.decrypt_block(&mut block);
-//!
-//! let sw_decrypted = block;
-//! ```
-//!
-//! ### Implementation State
-//!
-//! * DMA mode is currently not supported on ESP32 and ESP32S2 ⚠️
-//!
-//! ## DMA-AES Mode
-//!
-//! Supports 6 block cipher modes including `ECB/CBC/OFB/CTR/CFB8/CFB128`.
-//!
-//! * Initialization vector (IV) is currently not supported ⚠️
-//!
-//! ## Example
-//!
-//! ### Initialization
-//!
-//! ```no_run
-//! let dma = Gdma::new(peripherals.DMA);
-//! let dma_channel = dma.channel0;
-//!
-//! let mut descriptors = [0u32; 8 * 3];
-//! let mut rx_descriptors = [0u32; 8 * 3];
-//!
-//! let aes = Aes::new(peripherals.AES).with_dma(dma_channel.configure(
-//!     false,
-//!     &mut descriptors,
-//!     &mut rx_descriptors,
-//!     DmaPriority::Priority0,
-//! ));
-//! ```
-//!
-//! ### Operation
-//!
-//! ```no_run
-//! let transfer = aes
-//!     .process(
-//!         plaintext,
-//!         hw_encrypted,
-//!         Mode::Encryption128,
-//!         CipherMode::Ecb,
-//!         keybuf,
-//!     )
-//!     .unwrap();
-//! let (hw_encrypted, plaintext, aes) = transfer.wait().unwrap();
-//! ```
-
-#[cfg(esp32)]
-use crate::peripherals::generic::{Readable, Reg, RegisterSpec};
-#[cfg(not(esp32))]
-use crate::reg_access::AlignmentHelper;
-use crate::{
-    peripheral::{Peripheral, PeripheralRef},
-    peripherals::AES,
-};
-
-#[cfg_attr(esp32, path = "esp32.rs")]
-#[cfg_attr(esp32s3, path = "esp32s3.rs")]
-#[cfg_attr(esp32s2, path = "esp32s2.rs")]
-#[cfg_attr(esp32c3, path = "esp32cX.rs")]
-#[cfg_attr(esp32c6, path = "esp32cX.rs")]
-#[cfg_attr(esp32h2, path = "esp32cX.rs")]
-mod aes_spec_impl;
-
-const ALIGN_SIZE: usize = core::mem::size_of::<u32>();
-
-pub enum Mode {
-    Encryption128 = 0,
-    Encryption256 = 2,
-    Decryption128 = 4,
-    Decryption256 = 6,
-}
-
-/// AES peripheral container
-pub struct Aes<'d> {
-    aes: PeripheralRef<'d, AES>,
-    #[cfg(not(esp32))]
-    alignment_helper: AlignmentHelper,
-}
-
-impl<'d> Aes<'d> {
-    pub fn new(aes: impl Peripheral<P = AES> + 'd) -> Self {
-        crate::into_ref!(aes);
-        let mut ret = Self {
-            aes: aes,
-            #[cfg(not(esp32))]
-            alignment_helper: AlignmentHelper::default(),
-        };
-        ret.init();
-
-        ret
-    }
-
-    /// Encrypts/Decrypts the given buffer based on `mode` parameter
-    pub fn process(&mut self, block: &mut [u8; 16], mode: Mode, key: &[u8; 16]) {
-        self.write_key(key);
-        self.set_mode(mode as u8);
-        self.set_block(block);
-        self.start();
-        while !(self.is_idle()) {}
-        self.get_block(block);
-    }
-
-    fn set_mode(&mut self, mode: u8) {
-        self.write_mode(mode as u32);
-    }
-
-    fn is_idle(&mut self) -> bool {
-        self.read_idle()
-    }
-
-    fn set_block(&mut self, block: &[u8; 16]) {
-        self.write_block(block);
-    }
-
-    fn get_block(&self, block: &mut [u8; 16]) {
-        self.read_block(block);
-    }
-
-    fn start(&mut self) {
-        self.write_start();
-    }
-
-    // TODO: for some reason, the `volatile read/write` helpers from `reg_access`
-    // don't work for ESP32
-    #[cfg(esp32)]
-    fn write_to_regset(input: &[u8], n_offset: usize, reg_0: *mut u32) {
-        let chunks = input.chunks_exact(ALIGN_SIZE);
-        for (offset, chunk) in (0..n_offset).zip(chunks) {
-            let to_write = u32::from_ne_bytes(chunk.try_into().unwrap());
-            unsafe {
-                let p = reg_0.add(offset);
-                p.write_volatile(to_write);
-            }
-        }
-    }
-
-    // TODO: for some reason, the `volatile read/write` helpers from `reg_access`
-    // don't work for ESP32
-    #[cfg(esp32)]
-    fn read_from_regset<T>(out_buf: &mut [u8], n_offset: usize, reg_0: &Reg<T>)
-    where
-        T: RegisterSpec<Ux = u32> + Readable,
-    {
-        let chunks = out_buf.chunks_exact_mut(ALIGN_SIZE);
-        for (offset, chunk) in (0..n_offset).zip(chunks) {
-            unsafe {
-                let p = reg_0.as_ptr().add(offset);
-                let read_val: [u8; ALIGN_SIZE] = p.read_volatile().to_ne_bytes();
-                chunk.copy_from_slice(&read_val);
-            }
-        }
-    }
-}
-
-mod sealed {
-    /// Specifications for AES flavours
-    pub trait AesFlavour {
-        type KeyType<'b>;
-        const ENCRYPT_MODE: u32;
-        const DECRYPT_MODE: u32;
-    }
-}
-
-use sealed::AesFlavour;
-
-/// Marker type for AES-128
-pub struct Aes128;
-
-/// Marker type for AES-192
-#[cfg(any(esp32, esp32s2))]
-pub struct Aes192;
-
-/// Marker type for AES-256
-pub struct Aes256;
-
-/// State matrix endianness
-#[cfg(any(esp32, esp32s2))]
-pub enum Endianness {
-    BigEndian    = 1,
-    LittleEndian = 0,
-}
-
-#[cfg(any(esp32c3, esp32c6, esp32h2, esp32s3))]
-pub mod dma {
-    use core::mem;
-
-    use embedded_dma::{ReadBuffer, WriteBuffer};
-
-    use crate::{
-        aes::Mode,
-        dma::{
-            AesPeripheral,
-            Channel,
-            ChannelTypes,
-            DmaError,
-            DmaPeripheral,
-            DmaTransferRxTx,
-            RxPrivate,
-            TxPrivate,
-        },
-    };
-
-    const ALIGN_SIZE: usize = core::mem::size_of::<u32>();
-
-    pub enum CipherMode {
-        Ecb = 0,
-        Cbc,
-        Ofb,
-        Ctr,
-        Cfb8,
-        Cfb128,
-    }
-
-    /// A DMA capable AES instance.
-    pub struct AesDma<'d, C>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        pub aes: super::Aes<'d>,
-
-        pub(crate) channel: Channel<'d, C>,
-    }
-
-    pub trait WithDmaAes<'d, C>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        fn with_dma(self, channel: Channel<'d, C>) -> AesDma<'d, C>;
-    }
-
-    impl<'d, C> WithDmaAes<'d, C> for crate::aes::Aes<'d>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        fn with_dma(self, mut channel: Channel<'d, C>) -> AesDma<'d, C> {
-            channel.tx.init_channel(); // no need to call this for both, TX and RX
-
-            AesDma { aes: self, channel }
-        }
-    }
-
-    /// An in-progress DMA transfer
-    pub struct AesDmaTransferRxTx<'d, C, RBUFFER, TBUFFER>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        aes_dma: AesDma<'d, C>,
-        rbuffer: RBUFFER,
-        tbuffer: TBUFFER,
-    }
-
-    impl<'d, C, RXBUF, TXBUF> DmaTransferRxTx<RXBUF, TXBUF, AesDma<'d, C>>
-        for AesDmaTransferRxTx<'d, C, RXBUF, TXBUF>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        /// Wait for the DMA transfer to complete and return the buffers and the
-        /// AES instance.
-        fn wait(
-            self,
-        ) -> Result<(RXBUF, TXBUF, AesDma<'d, C>), (DmaError, RXBUF, TXBUF, AesDma<'d, C>)>
-        {
-            // Waiting for the DMA transfer is not enough. We need to wait for the
-            // peripheral to finish flushing its buffers, too.
-            while self.aes_dma.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2
-                && !self.aes_dma.channel.tx.is_done()
-            {
-                // wait until done
-            }
-
-            self.aes_dma.finish_transform();
-
-            let err = self.aes_dma.channel.rx.has_error() || self.aes_dma.channel.tx.has_error();
-
-            // `DmaTransferRxTx` needs to have a `Drop` implementation, because we accept
-            // managed buffers that can free their memory on drop. Because of that
-            // we can't move out of the `DmaTransferRxTx`'s fields, so we use `ptr::read`
-            // and `mem::forget`.
-            //
-            // NOTE(unsafe) There is no panic branch between getting the resources
-            // and forgetting `self`.
-            unsafe {
-                let rbuffer = core::ptr::read(&self.rbuffer);
-                let tbuffer = core::ptr::read(&self.tbuffer);
-                let payload = core::ptr::read(&self.aes_dma);
-                mem::forget(self);
-                if err {
-                    Err((DmaError::DescriptorError, rbuffer, tbuffer, payload))
-                } else {
-                    Ok((rbuffer, tbuffer, payload))
-                }
-            }
-        }
-
-        /// Check if the DMA transfer is complete
-        fn is_done(&self) -> bool {
-            let ch = &self.aes_dma.channel;
-            ch.tx.is_done() && ch.rx.is_done()
-        }
-    }
-
-    impl<'d, C, RXBUF, TXBUF> Drop for AesDmaTransferRxTx<'d, C, RXBUF, TXBUF>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        fn drop(&mut self) {
-            self.aes_dma
-                .aes
-                .aes
-                .dma_exit()
-                .write(|w| w.dma_exit().set_bit());
-        }
-    }
-
-    impl<'d, C> core::fmt::Debug for AesDma<'d, C>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-            f.debug_struct("AesDma").finish()
-        }
-    }
-
-    impl<'d, C> AesDma<'d, C>
-    where
-        C: ChannelTypes,
-        C::P: AesPeripheral,
-    {
-        pub fn write_key(&mut self, key: &[u8]) {
-            debug_assert!(key.len() <= 8 * ALIGN_SIZE);
-            debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
-            self.aes.write_key(key);
-        }
-
-        pub fn write_block(&mut self, block: &[u8]) {
-            debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
-            self.aes.write_key(block);
-        }
-
-        /// Perform a DMA transfer.
-        ///
-        /// This will return a [AesDmaTransferRxTx] owning the buffer(s) and the
-        /// AES instance. The maximum amount of data to be sent/received
-        /// is 32736 bytes.
-        pub fn process<TXBUF, RXBUF>(
-            mut self,
-            words: TXBUF,
-            mut read_buffer: RXBUF,
-            mode: Mode,
-            cipher_mode: CipherMode,
-            key: [u8; 16],
-        ) -> Result<AesDmaTransferRxTx<'d, C, RXBUF, TXBUF>, crate::dma::DmaError>
-        where
-            TXBUF: ReadBuffer<Word = u8>,
-            RXBUF: WriteBuffer<Word = u8>,
-        {
-            let (write_ptr, write_len) = unsafe { words.read_buffer() };
-            let (read_ptr, read_len) = unsafe { read_buffer.write_buffer() };
-
-            self.start_transfer_dma(
-                write_ptr,
-                write_len,
-                read_ptr,
-                read_len,
-                mode,
-                cipher_mode,
-                key,
-            )?;
-
-            Ok(AesDmaTransferRxTx {
-                aes_dma: self,
-                rbuffer: read_buffer,
-                tbuffer: words,
-            })
-        }
-
-        fn start_transfer_dma<'w>(
-            &mut self,
-            write_buffer_ptr: *const u8,
-            write_buffer_len: usize,
-            read_buffer_ptr: *mut u8,
-            read_buffer_len: usize,
-            mode: Mode,
-            cipher_mode: CipherMode,
-            key: [u8; 16],
-        ) -> Result<(), crate::dma::DmaError> {
-            // AES has to be restarted after each calculation
-            self.reset_aes();
-
-            self.channel.tx.is_done();
-            self.channel.rx.is_done();
-
-            self.channel
-                .tx
-                .prepare_transfer_without_start(
-                    self.dma_peripheral(),
-                    false,
-                    write_buffer_ptr,
-                    write_buffer_len,
-                )
-                .and_then(|_| self.channel.tx.start_transfer())?;
-            self.channel
-                .rx
-                .prepare_transfer_without_start(
-                    false,
-                    self.dma_peripheral(),
-                    read_buffer_ptr,
-                    read_buffer_len,
-                )
-                .and_then(|_| self.channel.rx.start_transfer())?;
-            self.enable_dma(true);
-            self.enable_interrupt();
-            self.set_mode(mode);
-            self.set_cipher_mode(cipher_mode);
-            self.write_key(&key);
-
-            // TODO: verify 16?
-            self.set_num_block(16);
-
-            self.start_transform();
-
-            Ok(())
-        }
-
-        #[cfg(any(esp32c3, esp32s3))]
-        pub fn reset_aes(&self) {
-            unsafe {
-                let s = crate::peripherals::SYSTEM::steal();
-                s.perip_rst_en1()
-                    .modify(|_, w| w.crypto_aes_rst().set_bit());
-                s.perip_rst_en1()
-                    .modify(|_, w| w.crypto_aes_rst().clear_bit());
-            }
-        }
-
-        #[cfg(any(esp32c6, esp32h2))]
-        pub fn reset_aes(&self) {
-            unsafe {
-                let s = crate::peripherals::PCR::steal();
-                s.aes_conf().modify(|_, w| w.aes_rst_en().set_bit());
-                s.aes_conf().modify(|_, w| w.aes_rst_en().clear_bit());
-            }
-        }
-
-        fn dma_peripheral(&self) -> DmaPeripheral {
-            DmaPeripheral::Aes
-        }
-
-        fn enable_dma(&self, enable: bool) {
-            self.aes
-                .aes
-                .dma_enable()
-                .write(|w| w.dma_enable().bit(enable));
-        }
-
-        fn enable_interrupt(&self) {
-            self.aes.aes.int_ena().write(|w| w.int_ena().set_bit());
-        }
-
-        pub fn set_cipher_mode(&self, mode: CipherMode) {
-            self.aes
-                .aes
-                .block_mode()
-                .modify(|_, w| unsafe { w.bits(mode as u32) });
-
-            if self.aes.aes.block_mode().read().block_mode().bits() == CipherMode::Ctr as u8 {
-                self.aes
-                    .aes
-                    .inc_sel()
-                    .modify(|_, w| w.inc_sel().clear_bit());
-            }
-        }
-
-        pub fn set_mode(&self, mode: Mode) {
-            self.aes
-                .aes
-                .mode()
-                .modify(|_, w| w.mode().variant(mode as u8));
-        }
-
-        fn start_transform(&self) {
-            self.aes.aes.trigger().write(|w| w.trigger().set_bit());
-        }
-
-        pub fn finish_transform(&self) {
-            self.aes.aes.dma_exit().write(|w| w.dma_exit().set_bit());
-            self.enable_dma(false);
-        }
-
-        fn set_num_block(&self, block: u32) {
-            self.aes
-                .aes
-                .block_num()
-                .modify(|_, w| unsafe { w.block_num().bits(block) });
-        }
-    }
-}

esp-hal-common/src/analog/adc/esp32.rs

@@ -1,505 +0,0 @@
-use core::marker::PhantomData;
-
-use embedded_hal::adc::{Channel, OneShot};
-
-pub use crate::analog::{ADC1, ADC2};
-use crate::{
-    peripheral::PeripheralRef,
-    peripherals::{RTC_IO, SENS},
-};
-
-/// The sampling/readout resolution of the ADC
-#[derive(PartialEq, Eq, Clone, Copy)]
-pub enum Resolution {
-    Resolution9Bit  = 0b00,
-    Resolution10Bit = 0b01,
-    Resolution11Bit = 0b10,
-    Resolution12Bit = 0b11,
-}
-
-#[derive(PartialEq, Eq, Clone, Copy)]
-pub enum Attenuation {
-    Attenuation0dB   = 0b00,
-    Attenuation2p5dB = 0b01,
-    Attenuation6dB   = 0b10,
-    Attenuation11dB  = 0b11,
-}
-
-pub struct AdcPin<PIN, ADCI> {
-    pub pin: PIN,
-    _phantom: PhantomData<ADCI>,
-}
-
-impl<PIN: Channel<ADCI, ID = u8>, ADCI> Channel<ADCI> for AdcPin<PIN, ADCI> {
-    type ID = u8;
-
-    fn channel() -> Self::ID {
-        PIN::channel()
-    }
-}
-
-pub struct AdcConfig<ADCI> {
-    pub resolution: Resolution,
-    pub attenuations: [Option<Attenuation>; 10],
-    _phantom: PhantomData<ADCI>,
-}
-
-impl<ADCI> AdcConfig<ADCI>
-where
-    ADCI: RegisterAccess,
-{
-    pub fn new() -> AdcConfig<ADCI> {
-        crate::into_ref!();
-        Self::default()
-    }
-
-    pub fn enable_pin<PIN: Channel<ADCI, ID = u8>>(
-        &mut self,
-        pin: PIN,
-        attenuation: Attenuation,
-    ) -> AdcPin<PIN, ADCI> {
-        self.attenuations[PIN::channel() as usize] = Some(attenuation);
-
-        AdcPin {
-            pin,
-            _phantom: PhantomData::default(),
-        }
-    }
-}
-
-impl<ADCI> Default for AdcConfig<ADCI> {
-    fn default() -> Self {
-        AdcConfig {
-            resolution: Resolution::Resolution12Bit,
-            attenuations: [None; 10],
-            _phantom: PhantomData::default(),
-        }
-    }
-}
-
-pub trait RegisterAccess {
-    fn set_bit_width(resolution: u8);
-
-    fn set_sample_bit(resolution: u8);
-
-    fn set_attenuation(channel: usize, attenuation: u8);
-
-    fn clear_dig_force();
-
-    fn set_start_force();
-
-    fn set_en_pad_force();
-
-    fn set_en_pad(channel: u8);
-
-    fn clear_start_sar();
-
-    fn set_start_sar();
-
-    fn read_done_sar() -> bool;
-
-    fn read_data_sar() -> u16;
-}
-
-#[doc(hidden)]
-impl RegisterAccess for ADC1 {
-    fn set_bit_width(resolution: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_start_force()
-            .modify(|_, w| unsafe { w.sar1_bit_width().bits(resolution) });
-    }
-
-    fn set_sample_bit(resolution: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_read_ctrl()
-            .modify(|_, w| unsafe { w.sar1_sample_bit().bits(resolution) });
-    }
-
-    fn set_attenuation(channel: usize, attenuation: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors.sar_atten1().modify(|r, w| {
-            let new_value = (r.bits() & !(0b11 << (channel * 2)))
-                | (((attenuation as u8 & 0b11) as u32) << (channel * 2));
-
-            unsafe { w.sar1_atten().bits(new_value) }
-        });
-    }
-
-    fn clear_dig_force() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_read_ctrl()
-            .modify(|_, w| w.sar1_dig_force().clear_bit());
-    }
-
-    fn set_start_force() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start1()
-            .modify(|_, w| w.meas1_start_force().set_bit());
-    }
-
-    fn set_en_pad_force() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start1()
-            .modify(|_, w| w.sar1_en_pad_force().set_bit());
-    }
-
-    fn set_en_pad(channel: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start1()
-            .modify(|_, w| unsafe { w.sar1_en_pad().bits(1 << channel) });
-    }
-
-    fn clear_start_sar() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start1()
-            .modify(|_, w| w.meas1_start_sar().clear_bit());
-    }
-
-    fn set_start_sar() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start1()
-            .modify(|_, w| w.meas1_start_sar().set_bit());
-    }
-
-    fn read_done_sar() -> bool {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start1()
-            .read()
-            .meas1_done_sar()
-            .bit_is_set()
-    }
-
-    fn read_data_sar() -> u16 {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors.sar_meas_start1().read().meas1_data_sar().bits() as u16
-    }
-}
-
-impl RegisterAccess for ADC2 {
-    fn set_bit_width(resolution: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_start_force()
-            .modify(|_, w| unsafe { w.sar2_bit_width().bits(resolution) });
-    }
-
-    fn set_sample_bit(resolution: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_read_ctrl2()
-            .modify(|_, w| unsafe { w.sar2_sample_bit().bits(resolution) });
-    }
-
-    fn set_attenuation(channel: usize, attenuation: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors.sar_atten2().modify(|r, w| {
-            let new_value = (r.bits() & !(0b11 << (channel * 2)))
-                | (((attenuation as u8 & 0b11) as u32) << (channel * 2));
-
-            unsafe { w.sar2_atten().bits(new_value) }
-        });
-    }
-
-    fn clear_dig_force() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_read_ctrl2()
-            .modify(|_, w| w.sar2_dig_force().clear_bit());
-    }
-
-    fn set_start_force() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start2()
-            .modify(|_, w| w.meas2_start_force().set_bit());
-    }
-
-    fn set_en_pad_force() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start2()
-            .modify(|_, w| w.sar2_en_pad_force().set_bit());
-    }
-
-    fn set_en_pad(channel: u8) {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start2()
-            .modify(|_, w| unsafe { w.sar2_en_pad().bits(1 << channel) });
-    }
-
-    fn clear_start_sar() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start2()
-            .modify(|_, w| w.meas2_start_sar().clear_bit());
-    }
-
-    fn set_start_sar() {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start2()
-            .modify(|_, w| w.meas2_start_sar().set_bit());
-    }
-
-    fn read_done_sar() -> bool {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_meas_start2()
-            .read()
-            .meas2_done_sar()
-            .bit_is_set()
-    }
-
-    fn read_data_sar() -> u16 {
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors.sar_meas_start2().read().meas2_data_sar().bits() as u16
-    }
-}
-
-pub struct ADC<'d, ADC> {
-    _adc: PeripheralRef<'d, ADC>,
-    attenuations: [Option<Attenuation>; 10],
-    active_channel: Option<u8>,
-}
-
-impl<'d, ADCI> ADC<'d, ADCI>
-where
-    ADCI: RegisterAccess,
-{
-    pub fn adc(
-        adc_instance: impl crate::peripheral::Peripheral<P = ADCI> + 'd,
-        config: AdcConfig<ADCI>,
-    ) -> Result<Self, ()> {
-        let sensors = unsafe { &*SENS::ptr() };
-
-        // Set reading and sampling resolution
-        let resolution: u8 = config.resolution as u8;
-
-        ADCI::set_bit_width(resolution);
-        ADCI::set_sample_bit(resolution);
-
-        // Set attenuation for pins
-        let attenuations = config.attenuations;
-
-        for channel in 0..attenuations.len() {
-            if let Some(attenuation) = attenuations[channel] {
-                ADC1::set_attenuation(channel, attenuation as u8);
-            }
-        }
-
-        // Set controller to RTC
-        ADCI::clear_dig_force();
-        ADCI::set_start_force();
-        ADCI::set_en_pad_force();
-        sensors
-            .sar_touch_ctrl1()
-            .modify(|_, w| w.xpd_hall_force().set_bit());
-        sensors
-            .sar_touch_ctrl1()
-            .modify(|_, w| w.hall_phase_force().set_bit());
-
-        // Set power to SW power on
-        sensors
-            .sar_meas_wait2()
-            .modify(|_, w| unsafe { w.force_xpd_sar().bits(0b11) });
-
-        // disable AMP
-        sensors
-            .sar_meas_wait2()
-            .modify(|_, w| unsafe { w.force_xpd_amp().bits(0b10) });
-        sensors
-            .sar_meas_ctrl()
-            .modify(|_, w| unsafe { w.amp_rst_fb_fsm().bits(0) });
-        sensors
-            .sar_meas_ctrl()
-            .modify(|_, w| unsafe { w.amp_short_ref_fsm().bits(0) });
-        sensors
-            .sar_meas_ctrl()
-            .modify(|_, w| unsafe { w.amp_short_ref_gnd_fsm().bits(0) });
-        sensors
-            .sar_meas_wait1()
-            .modify(|_, w| unsafe { w.sar_amp_wait1().bits(1) });
-        sensors
-            .sar_meas_wait1()
-            .modify(|_, w| unsafe { w.sar_amp_wait2().bits(1) });
-        sensors
-            .sar_meas_wait2()
-            .modify(|_, w| unsafe { w.sar_amp_wait3().bits(1) });
-
-        let adc = ADC {
-            _adc: adc_instance.into_ref(),
-            attenuations: config.attenuations,
-            active_channel: None,
-        };
-
-        Ok(adc)
-    }
-}
-
-impl<'d, ADC1> ADC<'d, ADC1> {
-    pub fn enable_hall_sensor() {
-        // Connect hall sensor
-        let rtcio = unsafe { &*RTC_IO::ptr() };
-        rtcio.hall_sens().modify(|_, w| w.xpd_hall().set_bit());
-    }
-
-    pub fn disable_hall_sensor() {
-        // Disconnect hall sensor
-        let rtcio = unsafe { &*RTC_IO::ptr() };
-        rtcio.hall_sens().modify(|_, w| w.xpd_hall().clear_bit());
-    }
-}
-
-impl<'d, ADCI, PIN> OneShot<ADCI, u16, AdcPin<PIN, ADCI>> for ADC<'d, ADCI>
-where
-    PIN: Channel<ADCI, ID = u8>,
-    ADCI: RegisterAccess,
-{
-    type Error = ();
-
-    fn read(&mut self, _pin: &mut AdcPin<PIN, ADCI>) -> nb::Result<u16, Self::Error> {
-        if self.attenuations[AdcPin::<PIN, ADCI>::channel() as usize] == None {
-            panic!(
-                "Channel {} is not configured reading!",
-                AdcPin::<PIN, ADCI>::channel()
-            );
-        }
-
-        if let Some(active_channel) = self.active_channel {
-            // There is conversion in progress:
-            // - if it's for a different channel try again later
-            // - if it's for the given channel, go ahead and check progress
-            if active_channel != AdcPin::<PIN, ADCI>::channel() {
-                return Err(nb::Error::WouldBlock);
-            }
-        } else {
-            // If no conversions are in progress, start a new one for given channel
-            self.active_channel = Some(AdcPin::<PIN, ADCI>::channel());
-
-            ADCI::set_en_pad(AdcPin::<PIN, ADCI>::channel() as u8);
-
-            ADCI::clear_start_sar();
-            ADCI::set_start_sar();
-        }
-
-        // Wait for ADC to finish conversion
-        let conversion_finished = ADCI::read_done_sar();
-        if !conversion_finished {
-            return Err(nb::Error::WouldBlock);
-        }
-
-        // Get converted value
-        let converted_value = ADCI::read_data_sar();
-
-        // Mark that no conversions are currently in progress
-        self.active_channel = None;
-
-        Ok(converted_value)
-    }
-}
-
-macro_rules! impl_adc_interface {
-    ($adc:ident [
-        $( ($pin:ident, $channel:expr) ,)+
-    ]) => {
-
-        $(
-            impl embedded_hal::adc::Channel<$adc> for crate::gpio::$pin<crate::gpio::Analog> {
-                type ID = u8;
-
-                fn channel() -> u8 { $channel }
-            }
-        )+
-    }
-}
-
-pub use implementation::*;
-
-mod implementation {
-    //! # Analog to digital (ADC) conversion support.
-    //!
-    //! ## Overview
-    //! The `ADC` module in the `analog` driver enables users to perform
-    //! analog-to-digital conversions, allowing them to measure real-world
-    //! analog signals with high accuracy.
-    //!
-    //! This module provides functions for reading analog values from the
-    //! analog to digital converter available on the ESP32: `ADC1` and `ADC2`.
-    //!
-    //! The following pins can be configured for analog readout:
-    //!
-    //! | Channel | ADC1                 | ADC2          |
-    //! |---------|----------------------|---------------|
-    //! | 0       | GPIO36 (SENSOR_VP)   | GPIO4         |
-    //! | 1       | GPIO37 (SENSOR_CAPP) | GPIO0         |
-    //! | 2       | GPIO38 (SENSOR_CAPN) | GPIO2         |
-    //! | 3       | GPIO39 (SENSOR_VN)   | GPIO15 (MTDO) |
-    //! | 4       | GPIO33 (32K_XP)      | GPIO13 (MTCK) |
-    //! | 5       | GPIO32 (32K_XN)      | GPIO12 (MTDI) |
-    //! | 6       | GPIO34 (VDET_1)      | GPIO14 (MTMS) |
-    //! | 7       | GPIO35 (VDET_2)      | GPIO27        |
-    //! | 8       |                      | GPIO25        |
-    //! | 9       |                      | GPIO26        |
-    //!
-    //! ## Example
-    //! #### ADC on Xtensa architecture
-    //! ```no_run
-    //! // Create ADC instances
-    //! let analog = peripherals.SENS.split();
-    //!
-    //! let mut adc1_config = AdcConfig::new();
-    //!
-    //! let mut pin3 =
-    //!     adc1_config.enable_pin(io.pins.gpio3.into_analog(), Attenuation::Attenuation11dB);
-    //!
-    //! let mut adc1 = ADC::<ADC1>::adc(analog.adc1, adc1_config).unwrap();
-    //!
-    //! let mut delay = Delay::new(&clocks);
-    //!
-    //! loop {
-    //!     let pin3_value: u16 = nb::block!(adc1.read(&mut pin3)).unwrap();
-    //!     println!("PIN3 ADC reading = {}", pin3_value);
-    //!     delay.delay_ms(1500u32);
-    //! }
-    //! ```
-
-    use crate::analog::{ADC1, ADC2};
-
-    impl_adc_interface! {
-        ADC1 [
-            (Gpio36, 0), // Alt. name: SENSOR_VP
-            (Gpio37, 1), // Alt. name: SENSOR_CAPP
-            (Gpio38, 2), // Alt. name: SENSOR_CAPN
-            (Gpio39, 3), // Alt. name: SENSOR_VN
-            (Gpio33, 4), // Alt. name: 32K_XP
-            (Gpio32, 5), // Alt. name: 32K_XN
-            (Gpio34, 6), // Alt. name: VDET_1
-            (Gpio35, 7), // Alt. name: VDET_2
-        ]
-    }
-
-    impl_adc_interface! {
-        ADC2 [
-            (Gpio4, 0),
-            (Gpio0, 1),
-            (Gpio2, 2),
-            (Gpio15, 3), // Alt. name: MTDO
-            (Gpio13, 4), // Alt. name: MTCK
-            (Gpio12, 5), // Alt. name: MTDI
-            (Gpio14, 6), // Alt. name: MTMS
-            (Gpio27, 7),
-            (Gpio25, 8),
-            (Gpio26, 9),
-        ]
-    }
-}

esp-hal-common/src/analog/dac.rs

@@ -1,159 +0,0 @@
-//! # Analog peripherals - Digital to Analog Converter
-//!
-//! ## Overview
-//! The `DAC` module is part of the `Analog` driver designed for ESP
-//! microcontrollers, providing functionalities for `digital-to-analog`
-//! conversion.
-//!
-//! This module simplifies digital-to-analog conversion on ESP microcontrollers,
-//! enabling precise control over analog output signals. Developers can choose
-//! the `DAC` channel they want to use based on the GPIO pin assignments for
-//! each channel. By providing a unified interface for DAC control, the module
-//! makes it easier for users to generate accurate analog voltages in their
-//! applications, such as audio generation, sensor calibration, and analog
-//! signal synthesis.
-use crate::peripherals::{RTC_IO, SENS};
-pub trait DAC {
-    fn write(&mut self, value: u8);
-}
-
-trait DAC1Impl {
-    fn set_power(self) -> Self
-    where
-        Self: Sized,
-    {
-        #[cfg(esp32s2)]
-        {
-            let sensors = unsafe { &*SENS::ptr() };
-            sensors
-                .sar_dac_ctrl1()
-                .modify(|_, w| w.dac_clkgate_en().set_bit());
-        }
-
-        let rtcio = unsafe { &*RTC_IO::ptr() };
-
-        rtcio.pad_dac1().modify(|_, w| {
-            w.pdac1_dac_xpd_force().set_bit();
-            w.pdac1_xpd_dac().set_bit()
-        });
-
-        self
-    }
-
-    fn write(&mut self, value: u8) {
-        let rtcio = unsafe { &*RTC_IO::ptr() };
-
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_dac_ctrl2()
-            .modify(|_, w| w.dac_cw_en1().clear_bit());
-
-        rtcio
-            .pad_dac1()
-            .modify(|_, w| unsafe { w.pdac1_dac().bits(value) });
-    }
-}
-
-trait DAC2Impl {
-    fn set_power(self) -> Self
-    where
-        Self: Sized,
-    {
-        #[cfg(esp32s2)]
-        {
-            let sensors = unsafe { &*SENS::ptr() };
-            sensors
-                .sar_dac_ctrl1()
-                .modify(|_, w| w.dac_clkgate_en().set_bit());
-        }
-
-        let rtcio = unsafe { &*RTC_IO::ptr() };
-
-        rtcio.pad_dac2().modify(|_, w| {
-            w.pdac2_dac_xpd_force().set_bit();
-            w.pdac2_xpd_dac().set_bit()
-        });
-
-        self
-    }
-
-    fn write(&mut self, value: u8) {
-        let rtcio = unsafe { &*RTC_IO::ptr() };
-
-        let sensors = unsafe { &*SENS::ptr() };
-        sensors
-            .sar_dac_ctrl2()
-            .modify(|_, w| w.dac_cw_en2().clear_bit());
-
-        rtcio
-            .pad_dac2()
-            .modify(|_, w| unsafe { w.pdac2_dac().bits(value) });
-    }
-}
-
-macro_rules! impl_dac {
-    ($($number:literal => $gpio:ident),+) => {
-        $(
-            paste::paste! {
-                use $crate::analog::dac::[<DAC $number Impl>];
-
-                #[doc = "DAC channel " $number]
-                pub struct [<DAC $number>]<'d, DAC> {
-                    _dac: $crate::peripheral::PeripheralRef<'d, DAC>,
-                    _private: ::core::marker::PhantomData<()>,
-                }
-
-                impl<'d, DAC> [<DAC $number Impl>] for [<DAC $number>]<'d, DAC> {}
-
-                impl<'d, DAC> [<DAC $number>]<'d, DAC> {
-                    /// Constructs a new DAC instance
-                    pub fn dac(
-                        dac: impl $crate::peripheral::Peripheral<P = DAC> +'d,
-                        _pin: $crate::gpio::$gpio<$crate::gpio::Analog>,
-                    ) -> Result<Self, ()> {
-                        let dac = Self {
-                            _dac: dac.into_ref(),
-                            _private: ::core::marker::PhantomData,
-                        }
-                        .set_power();
-                        Ok(dac)
-                    }
-
-                    /// Writes the given value
-                    ///
-                    /// For each DAC channel, the output analog voltage can be calculated as follows:
-                    /// DACn_OUT = VDD3P3_RTC * PDACn_DAC/256
-                    pub fn write(&mut self, value: u8) {
-                        [<DAC $number Impl>]::write(self, value)
-                    }
-                }
-            }
-        )+
-    };
-}
-
-pub use implementation::*;
-
-#[cfg(esp32)]
-mod implementation {
-    //! Digital to analog (DAC) conversion.
-    //!
-    //! This module provides functions for controlling two digital to
-    //! analog converters, available on ESP32: `DAC1` and `DAC2`.
-    //!
-    //! The DAC1 is available on the GPIO pin 25, and DAC2 on pin 26.
-
-    impl_dac!(1 => Gpio25, 2 => Gpio26);
-}
-
-#[cfg(esp32s2)]
-mod implementation {
-    //! Digital to analog (DAC) conversion.
-    //!
-    //! This module provides functions for controlling two digital to
-    //! analog converters, available on ESP32-S2: `DAC1` and `DAC2`.
-    //!
-    //! The DAC1 is available on the GPIO pin 17, and DAC2 on pin 18.
-
-    impl_dac!(1 => Gpio17, 2 => Gpio18);
-}

esp-hal-common/src/analog/mod.rs

@@ -1,260 +0,0 @@
-//! # Analog peripherals
-//!
-//! ## Overview
-//! The `Analog` Driver is a module designed for ESP microcontrollers, that
-//! provides an interface to interact with analog peripherals on the chip. The
-//! module includes support for `Analog-to-Digital Converters (ADC)` and
-//! `Digital-to-Analog Converters (DAC)`, offering functionality for precise
-//! analog measurements and generating analog output signals.
-//!
-//! The `ADC` module in the `analog` driver enables users to perform
-//! analog-to-digital conversions, allowing them to measure real-world analog
-//! signals with high accuracy. The module provides access to multiple ADC
-//! units, such as `ADC1` and `ADC2`, which may differ based on the specific ESP
-//! microcontroller being used.
-//!
-//! The `DAC` module in the `analog` driver enables users to generate
-//! analog output signals with precise control over voltage levels. The module
-//! supports multiple DAC units, such as `DAC1` and `DAC2`, which may vary
-//! depending on the specific ESP microcontroller.
-//!
-//! #### Xtensa architecture
-//! For ESP microcontrollers using the `Xtensa` architecture, the driver
-//! provides access to the `SENS` peripheral, allowing users to split it into
-//! independent parts using the [`AnalogExt`] trait. This extension trait
-//! provides access to the following analog peripherals:
-//!   * ADC1
-//!   * ADC2
-//!   * DAC1
-//!   * DAC2
-//!
-//! #### RISC-V architecture
-//! For ESP microcontrollers using the `RISC-V` architecture, the driver
-//! provides access to the `APB_SARADC` peripheral. The `AnalogExt` trait allows
-//! users to split this peripheral into independent parts, providing access to
-//! the following analog peripheral:
-//!   * ADC1
-//!   * ADC2
-//!
-//! ## Examples
-//! #### ADC on Risc-V architecture
-//! ```no_run
-//! // Create ADC instances
-//! let analog = peripherals.APB_SARADC.split();
-//!
-//! let mut adc1_config = AdcConfig::new();
-//!
-//! let mut pin = adc1_config.enable_pin(io.pins.gpio2.into_analog(), Attenuation::Attenuation11dB);
-//!
-//! let mut adc1 = ADC::<ADC1>::adc(analog.adc1, adc1_config).unwrap();
-//!
-//! let mut delay = Delay::new(&clocks);
-//!
-//! loop {
-//!     let pin_value: u16 = nb::block!(adc1.read(&mut pin)).unwrap();
-//!     println!("PIN2 ADC reading = {}", pin_value);
-//!     delay.delay_ms(1500u32);
-//! }
-//! ```
-//! #### ADC on Xtensa architecture
-//! ```no_run
-//! // Create ADC instances
-//! let analog = peripherals.SENS.split();
-//!
-//! let mut adc1_config = AdcConfig::new();
-//!
-//! let mut pin3 =
-//!     adc1_config.enable_pin(io.pins.gpio3.into_analog(), Attenuation::Attenuation11dB);
-//!
-//! let mut adc1 = ADC::<ADC1>::adc(analog.adc1, adc1_config).unwrap();
-//!
-//! let mut delay = Delay::new(&clocks);
-//!
-//! loop {
-//!     let pin3_value: u16 = nb::block!(adc1.read(&mut pin3)).unwrap();
-//!     println!("PIN3 ADC reading = {}", pin3_value);
-//!     delay.delay_ms(1500u32);
-//! }
-//! ```
-
-#[cfg_attr(esp32, path = "adc/esp32.rs")]
-#[cfg_attr(riscv, path = "adc/riscv.rs")]
-#[cfg_attr(any(esp32s2, esp32s3), path = "adc/xtensa.rs")]
-pub mod adc;
-#[cfg(dac)]
-pub mod dac;
-
-/// A trait abstracting over calibration methods.
-///
-/// The methods in this trait are mostly for internal use. To get
-/// calibrated ADC reads, all you need to do is call `enable_pin_with_cal`
-/// and specify some implementor of this trait.
-pub trait AdcCalScheme<ADCI>: Sized {
-    /// Create a new calibration scheme for the given attenuation.
-    fn new_cal(atten: adc::Attenuation) -> Self;
-
-    /// Return the basic ADC bias value. See [`adc::AdcCalBasic`] for
-    /// details.
-    fn adc_cal(&self) -> u16 {
-        0
-    }
-
-    /// Convert ADC value
-    fn adc_val(&self, val: u16) -> u16 {
-        val
-    }
-}
-
-impl<ADCI> AdcCalScheme<ADCI> for () {
-    fn new_cal(_atten: adc::Attenuation) -> Self {
-        ()
-    }
-}
-
-/// A helper trait to get access to ADC calibration efuses
-pub trait AdcCalEfuse {
-    /// Get ADC calibration init code
-    ///
-    /// Returns digital value for zero voltage for a given attenuation
-    fn get_init_code(atten: adc::Attenuation) -> Option<u16>;
-
-    /// Get ADC calibration reference point voltage
-    ///
-    /// Returns reference voltage (millivolts) for a given attenuation
-    fn get_cal_mv(atten: adc::Attenuation) -> u16;
-
-    /// Get ADC calibration reference point digital value
-    ///
-    /// Returns digital value for reference voltage for a given attenuation
-    fn get_cal_code(atten: adc::Attenuation) -> Option<u16>;
-}
-
-pub struct ADC1 {
-    _private: (),
-}
-
-pub struct ADC2 {
-    _private: (),
-}
-
-pub struct DAC1 {
-    _private: (),
-}
-
-pub struct DAC2 {
-    _private: (),
-}
-
-impl core::ops::Deref for ADC1 {
-    type Target = ADC1;
-
-    fn deref(&self) -> &Self::Target {
-        self
-    }
-}
-
-impl core::ops::DerefMut for ADC1 {
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        self
-    }
-}
-
-impl crate::peripheral::Peripheral for ADC1 {
-    type P = ADC1;
-    #[inline]
-    unsafe fn clone_unchecked(&mut self) -> Self::P {
-        ADC1 { _private: () }
-    }
-}
-
-impl crate::peripheral::sealed::Sealed for ADC1 {}
-
-impl crate::peripheral::Peripheral for ADC2 {
-    type P = ADC2;
-    #[inline]
-    unsafe fn clone_unchecked(&mut self) -> Self::P {
-        ADC2 { _private: () }
-    }
-}
-
-impl crate::peripheral::sealed::Sealed for ADC2 {}
-
-impl crate::peripheral::Peripheral for DAC1 {
-    type P = DAC1;
-    #[inline]
-    unsafe fn clone_unchecked(&mut self) -> Self::P {
-        DAC1 { _private: () }
-    }
-}
-
-impl crate::peripheral::sealed::Sealed for DAC1 {}
-
-impl crate::peripheral::Peripheral for DAC2 {
-    type P = DAC2;
-
-    #[inline]
-    unsafe fn clone_unchecked(&mut self) -> Self::P {
-        DAC2 { _private: () }
-    }
-}
-
-impl crate::peripheral::sealed::Sealed for DAC2 {}
-
-/// Extension trait to split a SENS peripheral in independent parts
-pub trait AnalogExt {
-    fn split(self) -> AvailableAnalog;
-}
-
-cfg_if::cfg_if! {
-    if #[cfg(xtensa)] {
-        pub struct AvailableAnalog {
-            pub adc1: ADC1,
-            pub adc2: ADC2,
-            pub dac1: DAC1,
-            pub dac2: DAC2,
-        }
-
-        impl AnalogExt for crate::peripherals::SENS {
-            fn split(self) -> AvailableAnalog {
-                AvailableAnalog {
-                    adc1: ADC1 {
-                        _private: (),
-                    },
-                    adc2: ADC2 {
-                        _private: (),
-                    },
-                    dac1: DAC1 {
-                        _private: (),
-                    },
-                    dac2: DAC2 {
-                        _private: (),
-                    },
-                }
-            }
-        }
-    }
-}
-
-cfg_if::cfg_if! {
-    if #[cfg(riscv)] {
-        pub struct AvailableAnalog {
-            pub adc1: ADC1,
-            #[cfg(esp32c3)]
-            pub adc2: ADC2,
-        }
-
-        impl AnalogExt for crate::peripherals::APB_SARADC {
-            fn split(self) -> AvailableAnalog {
-                AvailableAnalog {
-                    adc1: ADC1 {
-                        _private: (),
-                    },
-                    #[cfg(esp32c3)]
-                    adc2: ADC2 {
-                        _private: (),
-                    },
-                }
-            }
-        }
-    }
-}

esp-hal-common/src/clock/clocks_ll/esp32.rs

@@ -1,350 +0,0 @@
-use crate::clock::{Clock, PllClock, XtalClock};
-
-const REF_CLK_FREQ: u32 = 1000000;
-
-const MHZ: u32 = 1000000;
-const UINT16_MAX: u32 = 0xffff;
-
-const RTC_CNTL_DBIAS_1V10: u32 = 4;
-const RTC_CNTL_DBIAS_1V25: u32 = 7;
-
-const DIG_DBIAS_80M_160M: u32 = RTC_CNTL_DBIAS_1V10;
-const DIG_DBIAS_XTAL: u32 = RTC_CNTL_DBIAS_1V10;
-
-const I2C_BBPLL: u32 = 0x66;
-const I2C_BBPLL_HOSTID: u32 = 4;
-
-const I2C_BBPLL_IR_CAL_DELAY: u32 = 0;
-const I2C_BBPLL_IR_CAL_EXT_CAP: u32 = 1;
-const I2C_BBPLL_OC_ENB_FCAL: u32 = 4;
-const I2C_BBPLL_OC_ENB_VCON: u32 = 10;
-const I2C_BBPLL_BBADC_CAL_7_0: u32 = 12;
-
-const BBPLL_IR_CAL_DELAY_VAL: u32 = 0x18;
-const BBPLL_IR_CAL_EXT_CAP_VAL: u32 = 0x20;
-const BBPLL_OC_ENB_FCAL_VAL: u32 = 0x9a;
-const BBPLL_OC_ENB_VCON_VAL: u32 = 0x00;
-const BBPLL_BBADC_CAL_7_0_VAL: u32 = 0x00;
-
-const I2C_BBPLL_ENDIV5: u32 = 11;
-
-const BBPLL_ENDIV5_VAL_320M: u32 = 0x43;
-const BBPLL_BBADC_DSMP_VAL_320M: u32 = 0x84;
-const BBPLL_ENDIV5_VAL_480M: u32 = 0xc3;
-const BBPLL_BBADC_DSMP_VAL_480M: u32 = 0x74;
-
-const I2C_BBPLL_BBADC_DSMP: u32 = 9;
-const I2C_BBPLL_OC_LREF: u32 = 2;
-const I2C_BBPLL_OC_DIV_7_0: u32 = 3;
-const I2C_BBPLL_OC_DCUR: u32 = 5;
-
-pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) {
-    let efuse = unsafe { &*crate::peripherals::EFUSE::ptr() };
-    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
-
-    unsafe {
-        let rtc_cntl_dbias_hp_volt: u32 =
-            RTC_CNTL_DBIAS_1V25 - efuse.blk0_rdata5().read().rd_vol_level_hp_inv().bits() as u32;
-        let dig_dbias_240_m: u32 = rtc_cntl_dbias_hp_volt;
-
-        let div_ref: u32;
-        let div7_0: u32;
-        let div10_8: u32;
-        let lref: u32;
-        let dcur: u32;
-        let bw: u32;
-        let i2c_bbpll_lref: u32;
-        let i2c_bbpll_div_7_0: u32;
-        let i2c_bbpll_dcur: u32;
-
-        if matches!(pll_freq, PllClock::Pll320MHz) {
-            // Raise the voltage, if needed
-            rtc_cntl
-                .reg()
-                .modify(|_, w| w.dig_dbias_wak().variant(DIG_DBIAS_80M_160M as u8));
-
-            // Configure 320M PLL
-            match xtal_freq {
-                XtalClock::RtcXtalFreq40M => {
-                    div_ref = 0;
-                    div7_0 = 32;
-                    div10_8 = 0;
-                    lref = 0;
-                    dcur = 6;
-                    bw = 3;
-                }
-
-                XtalClock::RtcXtalFreq26M => {
-                    div_ref = 12;
-                    div7_0 = 224;
-                    div10_8 = 4;
-                    lref = 1;
-                    dcur = 0;
-                    bw = 1;
-                }
-
-                XtalClock::RtcXtalFreq24M => {
-                    div_ref = 11;
-                    div7_0 = 224;
-                    div10_8 = 4;
-                    lref = 1;
-                    dcur = 0;
-                    bw = 1;
-                }
-
-                XtalClock::RtcXtalFreqOther(_) => {
-                    div_ref = 12;
-                    div7_0 = 224;
-                    div10_8 = 4;
-                    lref = 0;
-                    dcur = 0;
-                    bw = 0;
-                }
-            }
-
-            i2c_writereg_rtc(
-                I2C_BBPLL,
-                I2C_BBPLL_HOSTID,
-                I2C_BBPLL_ENDIV5,
-                BBPLL_ENDIV5_VAL_320M,
-            );
-            i2c_writereg_rtc(
-                I2C_BBPLL,
-                I2C_BBPLL_HOSTID,
-                I2C_BBPLL_BBADC_DSMP,
-                BBPLL_BBADC_DSMP_VAL_320M,
-            );
-        } else {
-            // Raise the voltage
-            rtc_cntl
-                .reg()
-                .modify(|_, w| w.dig_dbias_wak().variant(dig_dbias_240_m as u8));
-
-            // Configure 480M PLL
-            match xtal_freq {
-                XtalClock::RtcXtalFreq40M => {
-                    div_ref = 0;
-                    div7_0 = 28;
-                    div10_8 = 0;
-                    lref = 0;
-                    dcur = 6;
-                    bw = 3;
-                }
-
-                XtalClock::RtcXtalFreq26M => {
-                    div_ref = 12;
-                    div7_0 = 144;
-                    div10_8 = 4;
-                    lref = 1;
-                    dcur = 0;
-                    bw = 1;
-                }
-
-                XtalClock::RtcXtalFreq24M => {
-                    div_ref = 11;
-                    div7_0 = 144;
-                    div10_8 = 4;
-                    lref = 1;
-                    dcur = 0;
-                    bw = 1;
-                }
-
-                XtalClock::RtcXtalFreqOther(_) => {
-                    div_ref = 12;
-                    div7_0 = 224;
-                    div10_8 = 4;
-                    lref = 0;
-                    dcur = 0;
-                    bw = 0;
-                }
-            }
-
-            i2c_writereg_rtc(
-                I2C_BBPLL,
-                I2C_BBPLL_HOSTID,
-                I2C_BBPLL_ENDIV5,
-                BBPLL_ENDIV5_VAL_480M,
-            );
-
-            i2c_writereg_rtc(
-                I2C_BBPLL,
-                I2C_BBPLL_HOSTID,
-                I2C_BBPLL_BBADC_DSMP,
-                BBPLL_BBADC_DSMP_VAL_480M,
-            );
-        }
-
-        i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
-        i2c_bbpll_div_7_0 = div7_0;
-        i2c_bbpll_dcur = (bw << 6) | dcur;
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_LREF,
-            i2c_bbpll_lref,
-        );
-
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_DIV_7_0,
-            i2c_bbpll_div_7_0,
-        );
-
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_DCUR,
-            i2c_bbpll_dcur,
-        );
-    }
-}
-
-pub(crate) fn esp32_rtc_bbpll_enable() {
-    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
-
-    unsafe {
-        rtc_cntl.options0().modify(|_, w| {
-            w.bias_i2c_force_pd()
-                .clear_bit()
-                .bb_i2c_force_pd()
-                .clear_bit()
-                .bbpll_force_pd()
-                .clear_bit()
-                .bbpll_i2c_force_pd()
-                .clear_bit()
-        });
-
-        // reset BBPLL configuration
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_IR_CAL_DELAY,
-            BBPLL_IR_CAL_DELAY_VAL,
-        );
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_IR_CAL_EXT_CAP,
-            BBPLL_IR_CAL_EXT_CAP_VAL,
-        );
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_ENB_FCAL,
-            BBPLL_OC_ENB_FCAL_VAL,
-        );
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_ENB_VCON,
-            BBPLL_OC_ENB_VCON_VAL,
-        );
-        i2c_writereg_rtc(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_BBADC_CAL_7_0,
-            BBPLL_BBADC_CAL_7_0_VAL,
-        );
-    }
-}
-
-#[inline(always)]
-unsafe fn i2c_writereg_rtc(block: u32, block_hostid: u32, reg_add: u32, indata: u32) {
-    const ROM_I2C_WRITEREG: u32 = 0x400041a4;
-
-    // cast to usize is just needed because of the way we run clippy in CI
-    let rom_i2c_writereg: fn(block: u32, block_hostid: u32, reg_add: u32, indata: u32) -> i32 =
-        core::mem::transmute(ROM_I2C_WRITEREG as usize);
-
-    rom_i2c_writereg(block, block_hostid, reg_add, indata);
-}
-
-pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) {
-    let apb_cntl = unsafe { &*crate::peripherals::APB_CTRL::ptr() };
-    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
-
-    unsafe {
-        let value = (((freq.hz()) >> 12) & UINT16_MAX) | ((((freq.hz()) >> 12) & UINT16_MAX) << 16);
-        esp32_update_cpu_freq(freq.hz());
-        // set divider from XTAL to APB clock
-        apb_cntl.sysclk_conf().modify(|_, w| {
-            w.pre_div_cnt()
-                .bits(((freq.hz()) / REF_CLK_FREQ - 1) as u16)
-        });
-
-        // adjust ref_tick
-        apb_cntl.xtal_tick_conf().as_ptr().write_volatile(
-            ((freq.hz()) / REF_CLK_FREQ - 1) | apb_cntl.xtal_tick_conf().as_ptr().read_volatile(),
-        ); // TODO make it RW in SVD
-
-        // switch clock source
-        rtc_cntl.clk_conf().modify(|_, w| w.soc_clk_sel().xtal());
-        rtc_cntl
-            .store5()
-            .modify(|_, w| w.scratch5().bits(value as u32));
-
-        // lower the voltage
-        rtc_cntl
-            .reg()
-            .modify(|_, w| w.dig_dbias_wak().variant(DIG_DBIAS_XTAL as u8));
-    }
-}
-
-pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) {
-    let efuse = unsafe { &*crate::peripherals::EFUSE::ptr() };
-    let dport = unsafe { &*crate::peripherals::DPORT::ptr() };
-    let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() };
-
-    unsafe {
-        const RTC_CNTL_DBIAS_1V25: u32 = 7;
-
-        let rtc_cntl_dbias_hp_volt: u32 =
-            RTC_CNTL_DBIAS_1V25 - efuse.blk0_rdata5().read().rd_vol_level_hp_inv().bits() as u32;
-        let dig_dbias_240_m: u32 = rtc_cntl_dbias_hp_volt;
-
-        const CPU_80M: u32 = 0;
-        const CPU_160M: u32 = 1;
-        const CPU_240M: u32 = 2;
-
-        let mut dbias = DIG_DBIAS_80M_160M;
-        let per_conf;
-
-        match cpu_freq_mhz {
-            crate::clock::CpuClock::Clock160MHz => {
-                per_conf = CPU_160M;
-            }
-            crate::clock::CpuClock::Clock240MHz => {
-                dbias = dig_dbias_240_m;
-                per_conf = CPU_240M;
-            }
-            crate::clock::CpuClock::Clock80MHz => {
-                per_conf = CPU_80M;
-            }
-        }
-
-        let value = (((80 * MHZ) >> 12) & UINT16_MAX) | ((((80 * MHZ) >> 12) & UINT16_MAX) << 16);
-        dport
-            .cpu_per_conf()
-            .write(|w| w.cpuperiod_sel().bits(per_conf as u8));
-        rtc_cntl
-            .reg()
-            .modify(|_, w| w.dig_dbias_wak().variant(dbias as u8));
-        rtc_cntl.clk_conf().modify(|_, w| w.soc_clk_sel().pll());
-        rtc_cntl
-            .store5()
-            .modify(|_, w| w.scratch5().bits(value as u32));
-
-        esp32_update_cpu_freq(cpu_freq_mhz.mhz());
-    }
-}
-
-/// Pass the CPU clock in MHz so that ets_delay_us
-/// will be accurate. Call this function when CPU frequency is changed.
-fn esp32_update_cpu_freq(mhz: u32) {
-    const G_TICKS_PER_US_PRO: u32 = 0x3ffe01e0;
-    unsafe {
-        // Update scale factors used by esp_rom_delay_us
-        (G_TICKS_PER_US_PRO as *mut u32).write_volatile(mhz);
-    }
-}

esp-hal-common/src/clock/clocks_ll/esp32c6.rs

@@ -1,369 +0,0 @@
-use crate::clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock};
-
-extern "C" {
-    fn ets_update_cpu_frequency(ticks_per_us: u32);
-}
-
-const I2C_BBPLL: u8 = 0x66;
-const I2C_BBPLL_HOSTID: u8 = 0;
-
-const I2C_BBPLL_OC_REF_DIV: u8 = 2;
-const I2C_BBPLL_OC_DCHGP_LSB: u32 = 4;
-
-const I2C_BBPLL_OC_DIV_7_0: u8 = 3;
-
-const I2C_BBPLL_OC_DR1: u8 = 5;
-const I2C_BBPLL_OC_DR1_MSB: u8 = 2;
-const I2C_BBPLL_OC_DR1_LSB: u8 = 0;
-
-const I2C_BBPLL_OC_DR3: u8 = 5;
-const I2C_BBPLL_OC_DR3_MSB: u8 = 6;
-const I2C_BBPLL_OC_DR3_LSB: u8 = 4;
-
-const I2C_BBPLL_OC_DCUR: u8 = 6;
-
-const I2C_BBPLL_OC_DHREF_SEL_LSB: u32 = 4;
-
-const I2C_BBPLL_OC_DLREF_SEL_LSB: u32 = 6;
-
-const I2C_BBPLL_OC_VCO_DBIAS: u8 = 9;
-const I2C_BBPLL_OC_VCO_DBIAS_MSB: u8 = 1;
-const I2C_BBPLL_OC_VCO_DBIAS_LSB: u8 = 0;
-
-// Analog function control register
-const I2C_MST_ANA_CONF0_REG: u32 = 0x600AF818;
-const I2C_MST_BBPLL_STOP_FORCE_HIGH: u32 = 1 << 2;
-const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 3;
-const I2C_MST_BBPLL_CAL_DONE: u32 = 1 << 24;
-
-const MODEM_LPCON_CLK_CONF_FORCE_ON_REG: u32 = DR_REG_MODEM_LPCON_BASE + 0x1c;
-const MODEM_LPCON_CLK_I2C_MST_FO: u32 = 1 << 2;
-const MODEM_LPCON_I2C_MST_CLK_CONF_REG: u32 = DR_REG_MODEM_LPCON_BASE + 0x10;
-const MODEM_LPCON_CLK_I2C_MST_SEL_160M: u32 = 1 << 0;
-
-pub(crate) fn esp32c6_rtc_bbpll_configure(_xtal_freq: XtalClock, _pll_freq: PllClock) {
-    unsafe {
-        // enable i2c mst clk by force on temporarily
-        (MODEM_LPCON_CLK_CONF_FORCE_ON_REG as *mut u32).write_volatile(
-            (MODEM_LPCON_CLK_CONF_FORCE_ON_REG as *mut u32).read_volatile()
-                | MODEM_LPCON_CLK_I2C_MST_FO,
-        );
-        (MODEM_LPCON_I2C_MST_CLK_CONF_REG as *mut u32).write_volatile(
-            (MODEM_LPCON_I2C_MST_CLK_CONF_REG as *mut u32).read_volatile()
-                | MODEM_LPCON_CLK_I2C_MST_SEL_160M,
-        );
-
-        let i2c_mst_ana_conf0_reg_ptr = I2C_MST_ANA_CONF0_REG as *mut u32;
-        // BBPLL CALIBRATION START
-        i2c_mst_ana_conf0_reg_ptr.write_volatile(
-            i2c_mst_ana_conf0_reg_ptr.read_volatile() & !I2C_MST_BBPLL_STOP_FORCE_HIGH,
-        );
-        i2c_mst_ana_conf0_reg_ptr.write_volatile(
-            i2c_mst_ana_conf0_reg_ptr.read_volatile() | I2C_MST_BBPLL_STOP_FORCE_LOW,
-        );
-
-        let div_ref = 0u32;
-        let div7_0 = 8u32;
-        let dr1 = 0u32;
-        let dr3 = 0u32;
-        let dchgp = 5u32;
-        let dcur = 3u32;
-        let dbias = 2u32;
-
-        let i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref;
-        let i2c_bbpll_div_7_0 = div7_0;
-        let i2c_bbpll_dcur =
-            (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
-
-        regi2c_write(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_REF_DIV,
-            i2c_bbpll_lref as u8,
-        );
-        regi2c_write(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_DIV_7_0,
-            i2c_bbpll_div_7_0 as u8,
-        );
-        regi2c_write_mask(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_DR1,
-            I2C_BBPLL_OC_DR1_MSB,
-            I2C_BBPLL_OC_DR1_LSB,
-            dr1 as u8,
-        );
-        regi2c_write_mask(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_DR3,
-            I2C_BBPLL_OC_DR3_MSB,
-            I2C_BBPLL_OC_DR3_LSB,
-            dr3 as u8,
-        );
-        regi2c_write(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_DCUR,
-            i2c_bbpll_dcur as u8,
-        );
-        regi2c_write_mask(
-            I2C_BBPLL,
-            I2C_BBPLL_HOSTID,
-            I2C_BBPLL_OC_VCO_DBIAS,
-            I2C_BBPLL_OC_VCO_DBIAS_MSB,
-            I2C_BBPLL_OC_VCO_DBIAS_LSB,
-            dbias as u8,
-        );
-
-        // WAIT CALIBRATION DONE
-        while (i2c_mst_ana_conf0_reg_ptr.read_volatile() & I2C_MST_BBPLL_CAL_DONE) == 0 {}
-
-        // BBPLL CALIBRATION STOP
-        i2c_mst_ana_conf0_reg_ptr.write_volatile(
-            i2c_mst_ana_conf0_reg_ptr.read_volatile() | I2C_MST_BBPLL_STOP_FORCE_HIGH,
-        );
-        i2c_mst_ana_conf0_reg_ptr.write_volatile(
-            i2c_mst_ana_conf0_reg_ptr.read_volatile() & !I2C_MST_BBPLL_STOP_FORCE_LOW,
-        );
-    }
-}
-
-pub(crate) fn esp32c6_rtc_bbpll_enable() {
-    let pmu = unsafe { &*crate::peripherals::PMU::PTR };
-
-    pmu.imm_hp_ck_power().modify(|_, w| {
-        w.tie_high_xpd_bb_i2c()
-            .set_bit()
-            .tie_high_xpd_bbpll()
-            .set_bit()
-            .tie_high_xpd_bbpll_i2c()
-            .set_bit()
-    });
-
-    pmu.imm_hp_ck_power()
-        .modify(|_, w| w.tie_high_global_bbpll_icg().set_bit());
-}
-
-pub(crate) fn esp32c6_rtc_update_to_xtal(freq: XtalClock, _div: u8) {
-    let pcr = unsafe { &*crate::peripherals::PCR::PTR };
-    unsafe {
-        ets_update_cpu_frequency(freq.mhz());
-        // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0)
-        // first.
-        pcr.apb_freq_conf()
-            .modify(|_, w| w.apb_div_num().bits(0).apb_div_num().bits(_div - 1));
-
-        // Switch clock source
-        pcr.sysclk_conf().modify(|_, w| w.soc_clk_sel().bits(0));
-    }
-}
-
-pub(crate) fn esp32c6_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) {
-    // On ESP32C6, MSPI source clock's default HS divider leads to 120MHz, which is
-    // unusable before calibration Therefore, before switching SOC_ROOT_CLK to
-    // HS, we need to set MSPI source clock HS divider to make it run at
-    // 80MHz after the switch. PLL = 480MHz, so divider is 6.
-    clk_ll_mspi_fast_set_hs_divider(6);
-
-    let pcr = unsafe { &*crate::peripherals::PCR::PTR };
-    unsafe {
-        pcr.cpu_freq_conf().modify(|_, w| {
-            w.cpu_hs_div_num()
-                .bits(((480 / cpu_clock_speed.mhz() / 3) - 1) as u8)
-                .cpu_hs_120m_force()
-                .clear_bit()
-        });
-
-        pcr.cpu_freq_conf()
-            .modify(|_, w| w.cpu_hs_120m_force().clear_bit());
-
-        pcr.sysclk_conf().modify(|_, w| {
-            w.soc_clk_sel().bits(1) // PLL = 1
-        });
-        ets_update_cpu_frequency(cpu_clock_speed.mhz());
-    }
-}
-
-pub(crate) fn esp32c6_rtc_apb_freq_update(apb_freq: ApbClock) {
-    let lp_aon = unsafe { &*crate::peripherals::LP_AON::ptr() };
-    let value = ((apb_freq.hz() >> 12) & u16::MAX as u32)
-        | (((apb_freq.hz() >> 12) & u16::MAX as u32) << 16);
-
-    lp_aon
-        .store5()
-        .modify(|_, w| unsafe { w.lp_aon_store5().bits(value) });
-}
-
-fn clk_ll_mspi_fast_set_hs_divider(divider: u32) {
-    // SOC_ROOT_CLK ------> MSPI_FAST_CLK
-    // HS divider option: 4, 5, 6 (PCR_MSPI_FAST_HS_DIV_NUM=3, 4, 5)
-    let pcr = unsafe { &*crate::peripherals::PCR::PTR };
-
-    unsafe {
-        match divider {
-            4 => pcr
-                .mspi_clk_conf()
-                .modify(|_, w| w.mspi_fast_hs_div_num().bits(3)),
-            5 => pcr
-                .mspi_clk_conf()
-                .modify(|_, w| w.mspi_fast_hs_div_num().bits(4)),
-            6 => pcr
-                .mspi_clk_conf()
-                .modify(|_, w| w.mspi_fast_hs_div_num().bits(5)),
-            _ => panic!("Unsupported HS MSPI_FAST divider"),
-        }
-    }
-}
-
-fn reg_set_bit(reg: u32, bit: u32) {
-    unsafe {
-        (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() | bit);
-    }
-}
-
-fn reg_clr_bit(reg: u32, bit: u32) {
-    unsafe {
-        (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !bit);
-    }
-}
-
-fn reg_write(reg: u32, v: u32) {
-    unsafe {
-        (reg as *mut u32).write_volatile(v);
-    }
-}
-
-fn reg_get_bit(reg: u32, b: u32) -> u32 {
-    unsafe { (reg as *mut u32).read_volatile() & b }
-}
-
-fn reg_get_field(reg: u32, s: u32, v: u32) -> u32 {
-    unsafe { ((reg as *mut u32).read_volatile() >> s) & v }
-}
-
-const DR_REG_MODEM_LPCON_BASE: u32 = 0x600AF000;
-const MODEM_LPCON_CLK_CONF_REG: u32 = DR_REG_MODEM_LPCON_BASE + 0x18;
-const MODEM_LPCON_CLK_I2C_MST_EN: u32 = 1 << 2;
-const DR_REG_LP_I2C_ANA_MST_BASE: u32 = 0x600B2400;
-const LP_I2C_ANA_MST_DATE_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x3fc;
-const LP_I2C_ANA_MST_I2C_MAT_CLK_EN: u32 = 1 << 28;
-const REGI2C_BIAS: u8 = 0x6a;
-const REGI2C_DIG_REG: u8 = 0x6d;
-const REGI2C_ULP_CAL: u8 = 0x61;
-const REGI2C_SAR_I2C: u8 = 0x69;
-
-const LP_I2C_ANA_MST_DEVICE_EN_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x14;
-const REGI2C_BBPLL_DEVICE_EN: u32 = 1 << 5;
-const REGI2C_BIAS_DEVICE_EN: u32 = 1 << 4;
-const REGI2C_DIG_REG_DEVICE_EN: u32 = 1 << 8;
-const REGI2C_ULP_CAL_DEVICE_EN: u32 = 1 << 6;
-const REGI2C_SAR_I2C_DEVICE_EN: u32 = 1 << 7;
-
-const REGI2C_RTC_SLAVE_ID_V: u8 = 0xFF;
-const REGI2C_RTC_SLAVE_ID_S: u8 = 0;
-const REGI2C_RTC_ADDR_V: u8 = 0xFF;
-const REGI2C_RTC_ADDR_S: u8 = 8;
-const REGI2C_RTC_WR_CNTL_V: u8 = 0x1;
-const REGI2C_RTC_WR_CNTL_S: u8 = 24;
-const REGI2C_RTC_DATA_V: u8 = 0xFF;
-const REGI2C_RTC_DATA_S: u8 = 16;
-
-const LP_I2C_ANA_MST_I2C0_CTRL_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x0;
-const LP_I2C_ANA_MST_I2C0_BUSY: u32 = 1 << 25;
-
-const LP_I2C_ANA_MST_I2C0_DATA_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x8;
-const LP_I2C_ANA_MST_I2C0_RDATA_V: u32 = 0x000000FF;
-const LP_I2C_ANA_MST_I2C0_RDATA_S: u32 = 0;
-
-const REGI2C_BBPLL: u8 = 0x66;
-
-fn regi2c_enable_block(block: u8) {
-    reg_set_bit(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    reg_set_bit(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN);
-
-    // Before config I2C register, enable corresponding slave.
-    match block {
-        REGI2C_BBPLL => {
-            reg_set_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN);
-        }
-        REGI2C_BIAS => {
-            reg_set_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN);
-        }
-        REGI2C_DIG_REG => {
-            reg_set_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN);
-        }
-        REGI2C_ULP_CAL => {
-            reg_set_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN);
-        }
-        REGI2C_SAR_I2C => {
-            reg_set_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN);
-        }
-        _ => (),
-    }
-}
-
-fn regi2c_disable_block(block: u8) {
-    match block {
-        REGI2C_BBPLL => {
-            reg_clr_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN);
-        }
-        REGI2C_BIAS => {
-            reg_clr_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN);
-        }
-        REGI2C_DIG_REG => {
-            reg_clr_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN);
-        }
-        REGI2C_ULP_CAL => {
-            reg_clr_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN);
-        }
-        REGI2C_SAR_I2C => {
-            reg_clr_bit(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN);
-        }
-        _ => (),
-    }
-}
-
-pub(crate) fn regi2c_write(block: u8, _host_id: u8, reg_add: u8, data: u8) {
-    regi2c_enable_block(block);
-
-    let temp: u32 = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32)
-                    | ((reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32)
-                    | ((0x1 & REGI2C_RTC_WR_CNTL_V as u32) << REGI2C_RTC_WR_CNTL_S as u32) // 0: READ I2C register; 1: Write I2C register;
-                    | (((data as u32) & REGI2C_RTC_DATA_V as u32) << REGI2C_RTC_DATA_S as u32);
-    reg_write(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while reg_get_bit(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY) != 0 {}
-
-    regi2c_disable_block(block);
-}
-
-pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, lsb: u8, data: u8) {
-    assert!(msb - lsb < 8);
-    regi2c_enable_block(block);
-
-    // Read the i2c bus register
-    let mut temp: u32 = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32)
-        << REGI2C_RTC_SLAVE_ID_S as u32)
-        | (reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32;
-    reg_write(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while reg_get_bit(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY) != 0 {}
-    temp = reg_get_field(
-        LP_I2C_ANA_MST_I2C0_DATA_REG,
-        LP_I2C_ANA_MST_I2C0_RDATA_S,
-        LP_I2C_ANA_MST_I2C0_RDATA_V,
-    );
-    // Write the i2c bus register
-    temp &= (!(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1));
-    temp =
-        ((data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32)) | temp;
-    temp = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32)
-        | ((reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32)
-        | ((0x1 & REGI2C_RTC_WR_CNTL_V as u32) << REGI2C_RTC_WR_CNTL_S as u32)
-        | ((temp & REGI2C_RTC_DATA_V as u32) << REGI2C_RTC_DATA_S as u32);
-    reg_write(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while reg_get_bit(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY) != 0 {}
-
-    regi2c_disable_block(block);
-}

esp-hal-common/src/clock/mod.rs

@@ -1,677 +0,0 @@
-//! # Clock Control
-//!
-//! ## Overview
-//! This `Clock` driver provides an interface for configuring and managing
-//! various clocks present on the `ESP` microcontrollers.
-//!
-//! Proper clock configuration is essential for the correct functioning of the
-//! microcontroller and its peripherals.
-//!
-//! The `Clock` driver supports configuring multiple clocks, including:
-//!   * CPU clock
-//!   * APB (Advanced Peripheral Bus) clock
-//!   * XTAL clock
-//!   * PLL clock
-//!
-//! and other specific clocks based on the ESP microcontroller's architecture.
-//!
-//! The `CPU clock` is responsible for defining the speed at which the central
-//! processing unit (CPU) operates. This driver provides predefined options for
-//! different CPU clock speeds, such
-//!   * 80 MHz
-//!   * 96 MHz
-//!   * 120 MHz
-//!   * 160 MHz
-//!   * 240 MHz
-//!
-//! and others, depending on the microcontroller model.
-//!
-//! #### Clock Control
-//! The `ClockControl` struct allows users to configure the desired clock
-//! frequencies before applying them. It offers flexibility in selecting
-//! appropriate clock frequencies based on specific application requirements.
-//!
-//! #### Frozen clock frequencies
-//! Once the clock configuration is applied using the `freeze` function of the
-//! ClockControl struct, the clock frequencies become `frozen` and cannot be
-//! changed. The `Clocks` struct is returned after freezing, providing read-only
-//! access to the configured clock frequencies.
-//!
-//! ## Examples
-//!
-//! #### Initialize with default clock frequency for this chip
-//! ```no_run
-//! let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
-//! ```
-//!
-//! #### Initialize with the highest possible frequency for this chip
-//! ```no_run
-//! let clocks = ClockControl::max(system.clock_control).freeze();
-//! ```
-//!
-//! #### Initialize with custom clock frequency
-//! ```no_run
-//! let clocks = ClockControl::configure(system.clock_control, CpuClock::Clock160MHz).freeze();
-//! ```
-use fugit::HertzU32;
-
-use crate::{
-    peripheral::{Peripheral, PeripheralRef},
-    system::SystemClockControl,
-};
-
-#[cfg_attr(esp32, path = "clocks_ll/esp32.rs")]
-#[cfg_attr(esp32c2, path = "clocks_ll/esp32c2.rs")]
-#[cfg_attr(esp32c3, path = "clocks_ll/esp32c3.rs")]
-#[cfg_attr(esp32c6, path = "clocks_ll/esp32c6.rs")]
-#[cfg_attr(esp32h2, path = "clocks_ll/esp32h2.rs")]
-#[cfg_attr(esp32s2, path = "clocks_ll/esp32s2.rs")]
-#[cfg_attr(esp32s3, path = "clocks_ll/esp32s3.rs")]
-pub(crate) mod clocks_ll;
-
-pub trait Clock {
-    fn frequency(&self) -> HertzU32;
-
-    fn mhz(&self) -> u32 {
-        self.frequency().to_MHz()
-    }
-
-    fn hz(&self) -> u32 {
-        self.frequency().to_Hz()
-    }
-}
-
-/// CPU clock speed
-#[derive(Debug, Clone, Copy)]
-pub enum CpuClock {
-    #[cfg(not(esp32h2))]
-    Clock80MHz,
-    #[cfg(esp32h2)]
-    Clock96MHz,
-    #[cfg(esp32c2)]
-    Clock120MHz,
-    #[cfg(not(any(esp32c2, esp32h2)))]
-    Clock160MHz,
-    #[cfg(not(any(esp32c2, esp32c3, esp32c6, esp32h2)))]
-    Clock240MHz,
-}
-
-#[allow(dead_code)]
-impl Clock for CpuClock {
-    fn frequency(&self) -> HertzU32 {
-        match self {
-            #[cfg(not(esp32h2))]
-            CpuClock::Clock80MHz => HertzU32::MHz(80),
-            #[cfg(esp32h2)]
-            CpuClock::Clock96MHz => HertzU32::MHz(96),
-            #[cfg(esp32c2)]
-            CpuClock::Clock120MHz => HertzU32::MHz(120),
-            #[cfg(not(any(esp32c2, esp32h2)))]
-            CpuClock::Clock160MHz => HertzU32::MHz(160),
-            #[cfg(not(any(esp32c2, esp32c3, esp32c6, esp32h2)))]
-            CpuClock::Clock240MHz => HertzU32::MHz(240),
-        }
-    }
-}
-
-#[derive(Debug, Clone, Copy)]
-#[non_exhaustive]
-pub enum XtalClock {
-    #[cfg(esp32)]
-    RtcXtalFreq24M,
-    #[cfg(any(esp32, esp32c2))]
-    RtcXtalFreq26M,
-    #[cfg(any(esp32c3, esp32h2, esp32s3))]
-    RtcXtalFreq32M,
-    #[cfg(not(esp32h2))]
-    RtcXtalFreq40M,
-    RtcXtalFreqOther(u32),
-}
-
-impl Clock for XtalClock {
-    fn frequency(&self) -> HertzU32 {
-        match self {
-            #[cfg(esp32)]
-            XtalClock::RtcXtalFreq24M => HertzU32::MHz(24),
-            #[cfg(any(esp32, esp32c2))]
-            XtalClock::RtcXtalFreq26M => HertzU32::MHz(26),
-            #[cfg(any(esp32c3, esp32h2, esp32s3))]
-            XtalClock::RtcXtalFreq32M => HertzU32::MHz(32),
-            #[cfg(not(esp32h2))]
-            XtalClock::RtcXtalFreq40M => HertzU32::MHz(40),
-            XtalClock::RtcXtalFreqOther(mhz) => HertzU32::MHz(*mhz),
-        }
-    }
-}
-
-#[allow(unused)]
-#[derive(Debug, Clone, Copy)]
-pub(crate) enum PllClock {
-    #[cfg(esp32h2)]
-    Pll8MHz,
-    #[cfg(any(esp32c6, esp32h2))]
-    Pll48MHz,
-    #[cfg(esp32h2)]
-    Pll64MHz,
-    #[cfg(esp32c6)]
-    Pll80MHz,
-    #[cfg(esp32h2)]
-    Pll96MHz,
-    #[cfg(esp32c6)]
-    Pll120MHz,
-    #[cfg(esp32c6)]
-    Pll160MHz,
-    #[cfg(esp32c6)]
-    Pll240MHz,
-    #[cfg(not(any(esp32c2, esp32c6, esp32h2)))]
-    Pll320MHz,
-    #[cfg(not(esp32h2))]
-    Pll480MHz,
-}
-
-#[allow(unused)]
-#[derive(Debug, Clone, Copy)]
-pub(crate) enum ApbClock {
-    #[cfg(esp32h2)]
-    ApbFreq32MHz,
-    #[cfg(not(esp32h2))]
-    ApbFreq40MHz,
-    #[cfg(not(esp32h2))]
-    ApbFreq80MHz,
-    ApbFreqOther(u32),
-}
-
-impl Clock for ApbClock {
-    fn frequency(&self) -> HertzU32 {
-        match self {
-            #[cfg(esp32h2)]
-            ApbClock::ApbFreq32MHz => HertzU32::MHz(32),
-            #[cfg(not(esp32h2))]
-            ApbClock::ApbFreq40MHz => HertzU32::MHz(40),
-            #[cfg(not(esp32h2))]
-            ApbClock::ApbFreq80MHz => HertzU32::MHz(80),
-            ApbClock::ApbFreqOther(mhz) => HertzU32::MHz(*mhz),
-        }
-    }
-}
-
-/// Frozen clock frequencies
-///
-/// The existence of this value indicates that the clock configuration can no
-/// longer be changed
-pub struct Clocks<'d> {
-    _private: PeripheralRef<'d, SystemClockControl>,
-    pub cpu_clock: HertzU32,
-    pub apb_clock: HertzU32,
-    pub xtal_clock: HertzU32,
-    #[cfg(esp32)]
-    pub i2c_clock: HertzU32,
-    #[cfg(esp32)]
-    pub pwm_clock: HertzU32,
-    #[cfg(esp32s3)]
-    pub crypto_pwm_clock: HertzU32,
-    #[cfg(any(esp32c6, esp32h2))]
-    pub crypto_clock: HertzU32,
-    #[cfg(esp32h2)]
-    pub pll_48m_clock: HertzU32,
-    #[cfg(esp32h2)]
-    pub pll_96m_clock: HertzU32,
-    // TODO chip specific additional ones as needed
-}
-
-#[doc(hidden)]
-impl<'d> Clocks<'d> {
-    /// This should not be used in user code.
-    /// The whole point this exists is make it possible to have other crates
-    /// (i.e. esp-wifi) create `Clocks`
-    #[doc(hidden)]
-    pub fn from_raw_clocks(
-        system_clock_control: PeripheralRef<'d, SystemClockControl>,
-        raw_clocks: RawClocks,
-    ) -> Clocks<'d> {
-        Self {
-            _private: system_clock_control,
-            cpu_clock: raw_clocks.cpu_clock,
-            apb_clock: raw_clocks.apb_clock,
-            xtal_clock: raw_clocks.xtal_clock,
-            #[cfg(esp32)]
-            i2c_clock: raw_clocks.i2c_clock,
-            #[cfg(esp32)]
-            pwm_clock: raw_clocks.pwm_clock,
-            #[cfg(esp32s3)]
-            crypto_pwm_clock: raw_clocks.crypto_pwm_clock,
-            #[cfg(any(esp32c6, esp32h2))]
-            crypto_clock: raw_clocks.crypto_clock,
-            #[cfg(esp32h2)]
-            pll_48m_clock: raw_clocks.pll_48m_clock,
-            #[cfg(esp32h2)]
-            pll_96m_clock: raw_clocks.pll_96m_clock,
-        }
-    }
-}
-
-#[doc(hidden)]
-pub struct RawClocks {
-    pub cpu_clock: HertzU32,
-    pub apb_clock: HertzU32,
-    pub xtal_clock: HertzU32,
-    #[cfg(esp32)]
-    pub i2c_clock: HertzU32,
-    #[cfg(esp32)]
-    pub pwm_clock: HertzU32,
-    #[cfg(esp32s3)]
-    pub crypto_pwm_clock: HertzU32,
-    #[cfg(any(esp32c6, esp32h2))]
-    pub crypto_clock: HertzU32,
-    #[cfg(esp32h2)]
-    pub pll_48m_clock: HertzU32,
-    #[cfg(esp32h2)]
-    pub pll_96m_clock: HertzU32,
-    // TODO chip specific additional ones as needed
-}
-
-/// Used to configure the frequencies of the clocks present in the chip.
-///
-/// After setting all frequencies, call the freeze function to apply the
-/// configuration.
-pub struct ClockControl<'d> {
-    _private: PeripheralRef<'d, SystemClockControl>,
-    desired_rates: RawClocks,
-}
-
-impl<'d> ClockControl<'d> {
-    /// Applies the clock configuration and returns a Clocks struct that
-    /// signifies that the clocks are frozen, and contains the frequencies
-    /// used. After this function is called, the clocks can not change
-    pub fn freeze(self) -> Clocks<'d> {
-        Clocks::from_raw_clocks(self._private, self.desired_rates)
-    }
-}
-
-#[cfg(esp32)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        #[cfg(feature = "xtal-40mhz")]
-        return ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-                i2c_clock: HertzU32::MHz(80),
-                pwm_clock: HertzU32::MHz(160),
-            },
-        };
-
-        #[cfg(feature = "xtal-26mhz")]
-        return ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(26),
-                i2c_clock: HertzU32::MHz(80),
-                pwm_clock: HertzU32::MHz(160),
-            },
-        };
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        // like NuttX use 40M hardcoded - if it turns out to be a problem
-        // we will take care then
-        #[cfg(feature = "xtal-40mhz")]
-        let xtal_freq = XtalClock::RtcXtalFreq40M;
-        #[cfg(feature = "xtal-26mhz")]
-        let xtal_freq = XtalClock::RtcXtalFreq26M;
-        let pll_freq = match cpu_clock_speed {
-            CpuClock::Clock80MHz => PllClock::Pll320MHz,
-            CpuClock::Clock160MHz => PllClock::Pll320MHz,
-            CpuClock::Clock240MHz => PllClock::Pll480MHz,
-        };
-
-        clocks_ll::esp32_rtc_update_to_xtal(xtal_freq, 1);
-        clocks_ll::esp32_rtc_bbpll_enable();
-        clocks_ll::esp32_rtc_bbpll_configure(xtal_freq, pll_freq);
-        clocks_ll::set_cpu_freq(cpu_clock_speed);
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-                i2c_clock: HertzU32::MHz(40),
-                // The docs are unclear here. pwm_clock seems to be tied to clocks.apb_clock
-                // while simultaneously being fixed at 160 MHz.
-                // Testing showed 160 MHz to be correct for current clock configurations.
-                pwm_clock: HertzU32::MHz(160),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock240MHz)
-    }
-}
-
-#[cfg(esp32c2)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        #[cfg(feature = "xtal-40mhz")]
-        return ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(40),
-                xtal_clock: HertzU32::MHz(40),
-            },
-        };
-
-        #[cfg(feature = "xtal-26mhz")]
-        return ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(40),
-                xtal_clock: HertzU32::MHz(26),
-            },
-        };
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        let apb_freq;
-        #[cfg(feature = "xtal-40mhz")]
-        let xtal_freq = XtalClock::RtcXtalFreq40M;
-        #[cfg(feature = "xtal-26mhz")]
-        let xtal_freq = XtalClock::RtcXtalFreq26M;
-        let pll_freq = PllClock::Pll480MHz;
-
-        if cpu_clock_speed.mhz() <= xtal_freq.mhz() {
-            apb_freq = ApbClock::ApbFreqOther(cpu_clock_speed.mhz());
-            clocks_ll::esp32c2_rtc_update_to_xtal(xtal_freq, 1);
-            clocks_ll::esp32c2_rtc_apb_freq_update(apb_freq);
-        } else {
-            apb_freq = ApbClock::ApbFreq40MHz;
-            clocks_ll::esp32c2_rtc_bbpll_enable();
-            clocks_ll::esp32c2_rtc_bbpll_configure(xtal_freq, pll_freq);
-            clocks_ll::esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed);
-            clocks_ll::esp32c2_rtc_apb_freq_update(apb_freq);
-        }
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: apb_freq.frequency(),
-                xtal_clock: xtal_freq.frequency(),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock120MHz)
-    }
-}
-
-#[cfg(esp32c3)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-            },
-        }
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        let apb_freq;
-        let xtal_freq = XtalClock::RtcXtalFreq40M;
-        let pll_freq = PllClock::Pll480MHz;
-
-        if cpu_clock_speed.mhz() <= xtal_freq.mhz() {
-            apb_freq = ApbClock::ApbFreqOther(cpu_clock_speed.mhz());
-            clocks_ll::esp32c3_rtc_update_to_xtal(xtal_freq, 1);
-            clocks_ll::esp32c3_rtc_apb_freq_update(apb_freq);
-        } else {
-            apb_freq = ApbClock::ApbFreq80MHz;
-            clocks_ll::esp32c3_rtc_bbpll_enable();
-            clocks_ll::esp32c3_rtc_bbpll_configure(xtal_freq, pll_freq);
-            clocks_ll::esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed);
-            clocks_ll::esp32c3_rtc_apb_freq_update(apb_freq);
-        }
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: apb_freq.frequency(),
-                xtal_clock: xtal_freq.frequency(),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock160MHz)
-    }
-}
-
-#[cfg(esp32c6)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-                crypto_clock: HertzU32::MHz(160),
-            },
-        }
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        let apb_freq;
-        let xtal_freq = XtalClock::RtcXtalFreq40M;
-        let pll_freq = PllClock::Pll480MHz;
-
-        if cpu_clock_speed.mhz() <= xtal_freq.mhz() {
-            apb_freq = ApbClock::ApbFreqOther(cpu_clock_speed.mhz());
-            clocks_ll::esp32c6_rtc_update_to_xtal(xtal_freq, 1);
-            clocks_ll::esp32c6_rtc_apb_freq_update(apb_freq);
-        } else {
-            apb_freq = ApbClock::ApbFreq80MHz;
-            clocks_ll::esp32c6_rtc_bbpll_enable();
-            clocks_ll::esp32c6_rtc_bbpll_configure(xtal_freq, pll_freq);
-            clocks_ll::esp32c6_rtc_freq_to_pll_mhz(cpu_clock_speed);
-            clocks_ll::esp32c6_rtc_apb_freq_update(apb_freq);
-        }
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: apb_freq.frequency(),
-                xtal_clock: xtal_freq.frequency(),
-                crypto_clock: HertzU32::MHz(160),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock160MHz)
-    }
-}
-
-#[cfg(esp32h2)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(96),
-                apb_clock: HertzU32::MHz(32),
-                xtal_clock: HertzU32::MHz(32),
-                pll_48m_clock: HertzU32::MHz(48),
-                crypto_clock: HertzU32::MHz(96),
-                pll_96m_clock: HertzU32::MHz(96),
-            },
-        }
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        let apb_freq;
-        let xtal_freq = XtalClock::RtcXtalFreq32M;
-        let pll_freq = PllClock::Pll96MHz;
-
-        if cpu_clock_speed.mhz() <= xtal_freq.mhz() {
-            apb_freq = ApbClock::ApbFreqOther(cpu_clock_speed.mhz());
-            clocks_ll::esp32h2_rtc_update_to_xtal(xtal_freq, 1);
-            clocks_ll::esp32h2_rtc_apb_freq_update(apb_freq);
-        } else {
-            apb_freq = ApbClock::ApbFreq32MHz;
-            clocks_ll::esp32h2_rtc_bbpll_enable();
-            clocks_ll::esp32h2_rtc_bbpll_configure(xtal_freq, pll_freq);
-            clocks_ll::esp32h2_rtc_freq_to_pll_mhz(cpu_clock_speed);
-            clocks_ll::esp32h2_rtc_apb_freq_update(apb_freq);
-        }
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: apb_freq.frequency(),
-                xtal_clock: xtal_freq.frequency(),
-                pll_48m_clock: HertzU32::MHz(48),
-                crypto_clock: HertzU32::MHz(96),
-                pll_96m_clock: HertzU32::MHz(96),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock96MHz)
-    }
-}
-
-#[cfg(esp32s2)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-            },
-        }
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        clocks_ll::set_cpu_clock(cpu_clock_speed);
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock240MHz)
-    }
-}
-
-#[cfg(esp32s3)]
-impl<'d> ClockControl<'d> {
-    /// Use what is considered the default settings after boot.
-    pub fn boot_defaults(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-    ) -> ClockControl<'d> {
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: HertzU32::MHz(80),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-                crypto_pwm_clock: HertzU32::MHz(160),
-            },
-        }
-    }
-
-    /// Configure the CPU clock speed.
-    pub fn configure(
-        clock_control: impl Peripheral<P = SystemClockControl> + 'd,
-        cpu_clock_speed: CpuClock,
-    ) -> ClockControl<'d> {
-        clocks_ll::set_cpu_clock(cpu_clock_speed);
-
-        ClockControl {
-            _private: clock_control.into_ref(),
-            desired_rates: RawClocks {
-                cpu_clock: cpu_clock_speed.frequency(),
-                apb_clock: HertzU32::MHz(80),
-                xtal_clock: HertzU32::MHz(40),
-                crypto_pwm_clock: HertzU32::MHz(160),
-            },
-        }
-    }
-
-    /// Use the highest possible frequency for a particular chip
-    pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
-        Self::configure(clock_control, CpuClock::Clock240MHz)
-    }
-}

esp-hal-common/src/delay.rs

@@ -1,122 +0,0 @@
-//! # Delay driver
-//!
-//! ## Overview
-//! The Delay driver provides blocking delay functionalities using the
-//! `SYSTIMER` peripheral for RISC-V devices and the built-in Xtensa timer for
-//! Xtensa devices. This module implements the blocking [DelayMs] and [DelayUs]
-//! traits from [embedded-hal].
-//!
-//! The delays are implemented in a "best-effort" way, meaning that the CPU will
-//! block for at least the amount of time specified, but accuracy can be
-//! affected by many factors, including interrupt usage.
-//!
-//! ## Example
-//! ```no_run
-//! let mut clocks = ClockControl::boot_defaults(system.clock_control).freeze();
-//! let mut delay = Delay::new(&clocks);
-//!
-//! delay.delay_ms(1000 as u32);
-//! ```
-//!
-//! [DelayMs]: embedded_hal::blocking::delay::DelayMs
-//! [DelayUs]: embedded_hal::blocking::delay::DelayUs
-//! [embedded-hal]: https://docs.rs/embedded-hal/latest/embedded_hal/
-
-use fugit::HertzU64;
-
-/// Delay driver
-///
-/// Uses the `SYSTIMER` peripheral internally for RISC-V devices, and the
-/// built-in Xtensa timer for Xtensa devices.
-#[derive(Clone, Copy)]
-pub struct Delay {
-    freq: HertzU64,
-}
-
-impl<T> embedded_hal::blocking::delay::DelayMs<T> for Delay
-where
-    T: Into<u32>,
-{
-    fn delay_ms(&mut self, ms: T) {
-        for _ in 0..ms.into() {
-            self.delay_micros(1000u32);
-        }
-    }
-}
-
-impl<T> embedded_hal::blocking::delay::DelayUs<T> for Delay
-where
-    T: Into<u32>,
-{
-    fn delay_us(&mut self, us: T) {
-        self.delay_micros(us.into());
-    }
-}
-
-#[cfg(feature = "eh1")]
-impl embedded_hal_1::delay::DelayNs for Delay {
-    fn delay_ns(&mut self, ns: u32) {
-        self.delay_nanos(ns);
-    }
-}
-
-#[cfg(riscv)]
-mod delay {
-    use super::*;
-    use crate::{clock::Clocks, systimer::SystemTimer};
-
-    impl Delay {
-        /// Create a new `Delay` instance
-        pub fn new(clocks: &Clocks) -> Self {
-            // The counters and comparators are driven using `XTAL_CLK`.
-            // The average clock frequency is fXTAL_CLK/2.5, which is 16 MHz.
-            // The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle.
-            Self {
-                freq: HertzU64::MHz(clocks.xtal_clock.to_MHz() as u64 * 10 / 25),
-            }
-        }
-
-        /// Delay for the specified number of microseconds
-        pub fn delay_micros(&self, us: u32) {
-            let t0 = SystemTimer::now();
-            let clocks = us as u64 * (self.freq / HertzU64::MHz(1));
-
-            while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {}
-        }
-
-        /// Delay for the specified number of nanoseconds
-        pub fn delay_nanos(&self, ns: u32) {
-            let t0 = SystemTimer::now();
-            let clocks = ns as u64 * (self.freq / HertzU64::MHz(1)) / 1000;
-
-            while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {}
-        }
-    }
-}
-
-#[cfg(xtensa)]
-mod delay {
-    use super::*;
-    use crate::clock::Clocks;
-
-    impl Delay {
-        /// Create a new `Delay` instance
-        pub fn new(clocks: &Clocks) -> Self {
-            Self {
-                freq: clocks.cpu_clock.into(),
-            }
-        }
-
-        /// Delay for the specified number of microseconds
-        pub fn delay_micros(&self, us: u32) {
-            let clocks = us as u64 * (self.freq / HertzU64::MHz(1));
-            xtensa_lx::timer::delay(clocks as u32);
-        }
-
-        /// Delay for the specified number of nanoseconds
-        pub fn delay_nanos(&self, ns: u32) {
-            let clocks = ns as u64 * (self.freq / HertzU64::MHz(1)) / 1000;
-            xtensa_lx::timer::delay(clocks as u32);
-        }
-    }
-}

esp-hal-common/src/dma/gdma.rs

@@ -1,692 +0,0 @@
-//! # Direct Memory Access
-//!
-//! ## Overview
-//!
-//! The GDMA (General DMA) module is a part of the DMA (Direct Memory Access)
-//! driver for ESP chips. Of the Espressif chip range, every chip except of
-//! `ESP32` and `ESP32-S2` uses the `GDMA` type of direct memory access.
-//!
-//! DMA is a hardware feature that allows data transfer between memory and
-//! peripherals without involving the CPU, resulting in efficient data movement
-//! and reduced CPU overhead. The `GDMA` module provides multiple DMA channels,
-//! each capable of managing data transfer for various peripherals.
-//!
-//! This module implements DMA channels, such as `channel0`, `channel1` and so
-//! on. Each channel struct implements the `ChannelTypes` trait, which provides
-//! associated types for peripheral configuration.
-//!
-//! GDMA peripheral can be initializes using the `new` function, which requires
-//! a DMA peripheral instance and a clock control reference.
-//!
-//! ```no_run
-//! let dma = Gdma::new(peripherals.DMA);
-//! ```
-//!
-//! <em>PS: Note that the number of DMA channels is chip-specific.</em>
-
-use crate::{
-    dma::*,
-    peripheral::PeripheralRef,
-    system::{Peripheral, PeripheralClockControl},
-};
-
-#[cold]
-fn on_tx_descriptor_not_divisible_by_3() {
-    panic!("The number of tx descriptors must be a multiple of 3");
-}
-
-#[cold]
-fn on_rx_descriptor_not_divisible_by_3() {
-    panic!("The number of rx descriptors must be a multiple of 3");
-}
-
-macro_rules! impl_channel {
-    ($num: literal) => {
-        paste::paste! {
-            #[non_exhaustive]
-            pub struct [<Channel $num>] {}
-
-            impl ChannelTypes for [<Channel $num>] {
-                type P = [<SuitablePeripheral $num>];
-                type Tx<'a> = ChannelTx<'a, [<Channel $num TxImpl>], [<Channel $num>]>;
-                type Rx<'a> = ChannelRx<'a, [<Channel $num RxImpl>], [<Channel $num>]>;
-            }
-
-            impl RegisterAccess for [<Channel $num>] {
-                fn init_channel() {
-                    // nothing special to be done here
-                }
-
-                fn set_out_burstmode(burst_mode: bool) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.out_conf0_ch($num).modify(|_,w| {
-                        w.out_data_burst_en().bit(burst_mode)
-                            .outdscr_burst_en().bit(burst_mode)
-                    });
-                }
-
-                fn set_out_priority(priority: DmaPriority) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.out_pri_ch($num).write(|w| {
-                        w.tx_pri().variant(priority as u8)
-                    });
-                }
-
-                fn clear_out_interrupts() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    dma.int_clr_ch($num).write(|w| {
-                        w.out_eof()
-                            .set_bit()
-                            .out_dscr_err()
-                            .set_bit()
-                            .out_done()
-                            .set_bit()
-                            .out_total_eof()
-                            .set_bit()
-                            .outfifo_ovf()
-                            .set_bit()
-                            .outfifo_udf()
-                            .set_bit()
-                    });
-
-                    #[cfg(any(esp32c6, esp32h2))]
-                    dma.out_int_clr_ch($num).write(|w| {
-                        w.out_eof()
-                            .set_bit()
-                            .out_dscr_err()
-                            .set_bit()
-                            .out_done()
-                            .set_bit()
-                            .out_total_eof()
-                            .set_bit()
-                            .outfifo_ovf()
-                            .set_bit()
-                            .outfifo_udf()
-                            .set_bit()
-                    });
-
-                    #[cfg(esp32s3)]
-                    dma.out_int_clr_ch($num).write(|w| {
-                        w.out_eof()
-                            .set_bit()
-                            .out_dscr_err()
-                            .set_bit()
-                            .out_done()
-                            .set_bit()
-                            .out_total_eof()
-                            .set_bit()
-                            .outfifo_ovf_l1()
-                            .set_bit()
-                            .outfifo_ovf_l3()
-                            .set_bit()
-                            .outfifo_udf_l1()
-                            .set_bit()
-                            .outfifo_udf_l3()
-                            .set_bit()
-                    });
-                }
-
-                fn reset_out() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.out_conf0_ch($num).modify(|_, w| w.out_rst().set_bit());
-                    dma.out_conf0_ch($num).modify(|_, w| w.out_rst().clear_bit());
-                }
-
-                fn set_out_descriptors(address: u32) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.out_link_ch($num).modify(|_, w| unsafe { w.outlink_addr().bits(address) });
-                }
-
-                fn has_out_descriptor_error() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().out_dscr_err().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.out_int_raw_ch($num).read().out_dscr_err().bit();
-
-                    ret
-                }
-
-                fn set_out_peripheral(peripheral: u8) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.out_peri_sel_ch($num).modify(|_, w| w.peri_out_sel().variant(peripheral));
-                }
-
-                fn start_out() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.out_link_ch($num).modify(|_, w| w.outlink_start().set_bit());
-                }
-
-                fn clear_ch_out_done() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    dma.int_clr_ch($num).write(|w| w.out_done().set_bit());
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    dma.out_int_clr_ch($num).write(|w| w.out_done().set_bit());
-                }
-
-                fn is_ch_out_done_set() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().out_done().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.out_int_raw_ch($num).read().out_done().bit();
-
-                    ret
-                }
-
-                fn listen_ch_out_done() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.out_int_ena_ch($num).modify(|_, w| w.out_done().set_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.out_done().set_bit())
-                        }
-                    }
-                }
-
-                fn unlisten_ch_out_done() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.out_int_ena_ch($num).modify(|_, w| w.out_done().clear_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.out_done().clear_bit())
-                        }
-                    }
-                }
-
-                fn is_listening_ch_out_done() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.out_int_ena_ch($num).read().out_done().bit()
-                        } else {
-                            dma.int_ena_ch($num).read().out_done().bit()
-                        }
-                    }
-                }
-
-                fn is_out_done() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().out_total_eof().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.out_int_raw_ch($num).read().out_total_eof().bit();
-
-                    ret
-                }
-
-                fn last_out_dscr_address() -> usize {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    dma.out_eof_des_addr_ch($num).read().out_eof_des_addr().bits() as usize
-                }
-
-                fn is_out_eof_interrupt_set() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().out_eof().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.out_int_raw_ch($num).read().out_eof().bit();
-
-                    ret
-                }
-
-                fn reset_out_eof_interrupt() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    dma.int_clr_ch($num).write(|w| {
-                        w.out_eof()
-                            .set_bit()
-                    });
-
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    dma.out_int_clr_ch($num).write(|w| {
-                        w.out_eof()
-                            .set_bit()
-                    });
-                }
-
-                fn set_in_burstmode(burst_mode: bool) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.in_conf0_ch($num).modify(|_,w| {
-                        w.in_data_burst_en().bit(burst_mode).indscr_burst_en().bit(burst_mode)
-                    });
-                }
-
-                fn set_in_priority(priority: DmaPriority) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.in_pri_ch($num).write(|w| {
-                        w.rx_pri().variant(priority as u8)
-                    });
-                }
-
-                fn clear_in_interrupts() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    dma.int_clr_ch($num).write(|w| {
-                        w.in_suc_eof()
-                            .set_bit()
-                            .in_err_eof()
-                            .set_bit()
-                            .in_dscr_err()
-                            .set_bit()
-                            .in_dscr_empty()
-                            .set_bit()
-                            .in_done()
-                            .set_bit()
-                            .infifo_ovf()
-                            .set_bit()
-                            .infifo_udf()
-                            .set_bit()
-                    });
-
-                    #[cfg(any(esp32c6, esp32h2))]
-                    dma.in_int_clr_ch($num).write(|w| {
-                        w.in_suc_eof()
-                            .set_bit()
-                            .in_err_eof()
-                            .set_bit()
-                            .in_dscr_err()
-                            .set_bit()
-                            .in_dscr_empty()
-                            .set_bit()
-                            .in_done()
-                            .set_bit()
-                            .infifo_ovf()
-                            .set_bit()
-                            .infifo_udf()
-                            .set_bit()
-                    });
-
-                    #[cfg(esp32s3)]
-                    dma.in_int_clr_ch($num).write(|w| {
-                        w.in_suc_eof()
-                            .set_bit()
-                            .in_err_eof()
-                            .set_bit()
-                            .in_dscr_err()
-                            .set_bit()
-                            .in_dscr_empty()
-                            .set_bit()
-                            .in_done()
-                            .set_bit()
-                            .infifo_ovf_l1()
-                            .set_bit()
-                            .infifo_ovf_l3()
-                            .set_bit()
-                            .infifo_udf_l1()
-                            .set_bit()
-                            .infifo_udf_l3()
-                            .set_bit()
-                    });
-                }
-
-                fn reset_in() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.in_conf0_ch($num).modify(|_, w| w.in_rst().set_bit());
-                    dma.in_conf0_ch($num).modify(|_, w| w.in_rst().clear_bit());
-                }
-
-                fn set_in_descriptors(address: u32) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.in_link_ch($num).modify(|_, w| unsafe { w.inlink_addr().bits(address) });
-                }
-
-                fn has_in_descriptor_error() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().in_dscr_err().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.in_int_raw_ch($num).read().in_dscr_err().bit();
-
-                    ret
-                }
-
-                fn has_in_descriptor_error_dscr_empty() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().in_dscr_empty().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.in_int_raw_ch($num).read().in_dscr_empty().bit();
-
-                    ret
-                }
-
-                fn has_in_descriptor_error_err_eof() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().in_err_eof().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.in_int_raw_ch($num).read().in_err_eof().bit();
-
-                    ret
-                }
-
-                fn set_in_peripheral(peripheral: u8) {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.in_peri_sel_ch($num).modify(|_, w| w.peri_in_sel().variant(peripheral));
-                }
-
-                fn start_in() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    dma.in_link_ch($num).modify(|_, w| w.inlink_start().set_bit());
-                }
-
-                fn is_in_done() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().in_suc_eof().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.in_int_raw_ch($num).read().in_suc_eof().bit();
-
-                    ret
-                }
-
-                fn last_in_dscr_address() -> usize {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    dma.in_dscr_bf0_ch($num).read().inlink_dscr_bf0().bits() as usize
-                }
-
-                fn is_listening_in_eof() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.in_int_ena_ch($num).read().in_suc_eof().bit_is_set()
-                        } else {
-                            dma.int_ena_ch($num).read().in_suc_eof().bit_is_set()
-                        }
-                    }
-                }
-
-                fn is_listening_out_eof() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.out_int_ena_ch($num).read().out_total_eof().bit_is_set()
-                        } else {
-                            dma.int_ena_ch($num).read().out_total_eof().bit_is_set()
-                        }
-                    }
-                }
-
-                fn listen_in_eof() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.in_int_ena_ch($num).modify(|_, w| w.in_suc_eof().set_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.in_suc_eof().set_bit())
-                        }
-                    }
-                }
-
-                fn listen_out_eof() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.out_int_ena_ch($num).modify(|_, w| w.out_total_eof().set_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.out_total_eof().set_bit())
-                        }
-                    }
-                }
-
-                fn unlisten_in_eof() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.in_int_ena_ch($num).modify(|_, w| w.in_suc_eof().clear_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.in_suc_eof().clear_bit())
-                        }
-                    }
-                }
-
-                fn unlisten_out_eof() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.out_int_ena_ch($num).modify(|_, w| w.out_total_eof().clear_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.out_total_eof().clear_bit())
-                        }
-                    }
-                }
-
-                fn listen_ch_in_done(){
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.in_int_ena_ch($num).modify(|_, w| w.in_done().set_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.in_done().set_bit())
-                        }
-                    }
-                }
-
-                fn clear_ch_in_done(){
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    dma.int_clr_ch($num).write(|w| w.in_done().set_bit());
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    dma.in_int_clr_ch($num).write(|w| w.in_done().set_bit());
-                }
-
-                fn is_ch_in_done_set() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-
-                    #[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
-                    let ret = dma.int_raw_ch($num).read().in_done().bit();
-                    #[cfg(any(esp32c6, esp32h2, esp32s3))]
-                    let ret = dma.in_int_raw_ch($num).read().in_done().bit();
-
-                    ret
-                }
-
-                fn unlisten_ch_in_done() {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.in_int_ena_ch($num).modify(|_, w| w.in_done().clear_bit())
-                        } else {
-                            dma.int_ena_ch($num).modify(|_, w| w.in_done().clear_bit())
-                        }
-                    }
-                }
-
-                fn is_listening_ch_in_done() -> bool {
-                    let dma = unsafe { &*crate::peripherals::DMA::PTR };
-                    cfg_if::cfg_if! {
-                        if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
-                            dma.in_int_ena_ch($num).read().in_done().bit()
-                        } else {
-                            dma.int_ena_ch($num).read().in_done().bit()
-                        }
-                    }
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<Channel $num TxImpl>] {}
-
-            impl<'a> TxChannel<[<Channel $num>]> for [<Channel $num TxImpl>] {
-                #[cfg(feature = "async")]
-                fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
-                    static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
-                    &WAKER
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<Channel $num RxImpl>] {}
-
-            impl<'a> RxChannel<[<Channel $num>]> for [<Channel $num RxImpl>] {
-                #[cfg(feature = "async")]
-                fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
-                    static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
-                    &WAKER
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<ChannelCreator $num>] {}
-
-            impl [<ChannelCreator $num>] {
-                /// Configure the channel for use
-                ///
-                /// Descriptors should be sized as `((CHUNK_SIZE + 4091) / 4092) * 3`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 3 descriptors. The number of
-                /// descriptors must be a multiple of 3.
-                pub fn configure<'a>(
-                    self,
-                    burst_mode: bool,
-                    tx_descriptors: &'a mut [u32],
-                    rx_descriptors: &'a mut [u32],
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<Channel $num>]> {
-                    if tx_descriptors.len() % 3 != 0 {
-                        on_tx_descriptor_not_divisible_by_3();
-                    }
-
-                    if rx_descriptors.len() % 3 != 0 {
-                        on_rx_descriptor_not_divisible_by_3();
-                    }
-
-                    let mut tx_impl = [<Channel $num TxImpl>] {};
-                    tx_impl.init(burst_mode, priority);
-
-                    let tx_channel = ChannelTx {
-                        descriptors: tx_descriptors,
-                        burst_mode,
-                        tx_impl: tx_impl,
-                        write_offset: 0,
-                        write_descr_ptr: core::ptr::null(),
-                        available: 0,
-                        last_seen_handled_descriptor_ptr: core::ptr::null(),
-                        buffer_start: core::ptr::null(),
-                        buffer_len: 0,
-                        _phantom: PhantomData::default(),
-                    };
-
-                    let mut rx_impl = [<Channel $num RxImpl>] {};
-                    rx_impl.init(burst_mode, priority);
-
-                    let rx_channel = ChannelRx {
-                        descriptors: rx_descriptors,
-                        burst_mode,
-                        rx_impl: rx_impl,
-                        read_descr_ptr: core::ptr::null(),
-                        available: 0,
-                        last_seen_handled_descriptor_ptr: core::ptr::null(),
-                        read_buffer_start: core::ptr::null(),
-                        _phantom: PhantomData::default(),
-                    };
-
-                    Channel {
-                        tx: tx_channel,
-                        rx: rx_channel,
-                    }
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<SuitablePeripheral $num>] {}
-            impl PeripheralMarker for [<SuitablePeripheral $num>] {}
-
-            // with GDMA every channel can be used for any peripheral
-            impl SpiPeripheral for [<SuitablePeripheral $num>] {}
-            impl Spi2Peripheral for [<SuitablePeripheral $num>] {}
-            #[cfg(esp32s3)]
-            impl Spi3Peripheral for [<SuitablePeripheral $num>] {}
-            impl I2sPeripheral for [<SuitablePeripheral $num>] {}
-            impl I2s0Peripheral for [<SuitablePeripheral $num>] {}
-            impl I2s1Peripheral for [<SuitablePeripheral $num>] {}
-            #[cfg(parl_io)]
-            impl ParlIoPeripheral for [<SuitablePeripheral $num>] {}
-            #[cfg(aes)]
-            impl AesPeripheral for [<SuitablePeripheral $num>] {}
-        }
-    };
-}
-
-impl_channel!(0);
-#[cfg(not(esp32c2))]
-impl_channel!(1);
-#[cfg(not(esp32c2))]
-impl_channel!(2);
-#[cfg(esp32s3)]
-impl_channel!(3);
-#[cfg(esp32s3)]
-impl_channel!(4);
-
-/// GDMA Peripheral
-///
-/// This offers the available DMA channels.
-pub struct Gdma<'d> {
-    _inner: PeripheralRef<'d, crate::peripherals::DMA>,
-    pub channel0: ChannelCreator0,
-    #[cfg(not(esp32c2))]
-    pub channel1: ChannelCreator1,
-    #[cfg(not(esp32c2))]
-    pub channel2: ChannelCreator2,
-    #[cfg(esp32s3)]
-    pub channel3: ChannelCreator3,
-    #[cfg(esp32s3)]
-    pub channel4: ChannelCreator4,
-}
-
-impl<'d> Gdma<'d> {
-    /// Create a DMA instance.
-    pub fn new(
-        dma: impl crate::peripheral::Peripheral<P = crate::peripherals::DMA> + 'd,
-    ) -> Gdma<'d> {
-        crate::into_ref!(dma);
-
-        PeripheralClockControl::enable(Peripheral::Gdma);
-        dma.misc_conf().modify(|_, w| w.ahbm_rst_inter().set_bit());
-        dma.misc_conf()
-            .modify(|_, w| w.ahbm_rst_inter().clear_bit());
-        dma.misc_conf().modify(|_, w| w.clk_en().set_bit());
-
-        Gdma {
-            _inner: dma,
-            channel0: ChannelCreator0 {},
-            #[cfg(not(esp32c2))]
-            channel1: ChannelCreator1 {},
-            #[cfg(not(esp32c2))]
-            channel2: ChannelCreator2 {},
-            #[cfg(esp32s3)]
-            channel3: ChannelCreator3 {},
-            #[cfg(esp32s3)]
-            channel4: ChannelCreator4 {},
-        }
-    }
-}

esp-hal-common/src/dma/pdma.rs

@@ -1,742 +0,0 @@
-//! # Direct Memory Access
-//!
-//! ## Overview
-//!
-//! The `pdma` module is part of the DMA (Direct Memory Access) driver of
-//! `ESP32` and `ESP32-S2`.
-//!
-//! This module provides efficient direct data transfer capabilities between
-//! peripherals and memory without involving the CPU. It enables bidirectional
-//! data transfers through DMA channels, making it particularly useful for
-//! high-speed data transfers, such as [SPI] and [I2S] communication.
-//!
-//! [SPI]: ../spi/index.html
-//! [I2S]: ../i2s/index.html
-
-use crate::{
-    dma::*,
-    peripheral::PeripheralRef,
-    system::{Peripheral, PeripheralClockControl},
-};
-
-#[cold]
-fn on_tx_descriptor_not_divisible_by_3() {
-    panic!("The number of tx descriptors must be a multiple of 3");
-}
-
-#[cold]
-fn on_rx_descriptor_not_divisible_by_3() {
-    panic!("The number of rx descriptors must be a multiple of 3");
-}
-
-macro_rules! ImplSpiChannel {
-    ($num: literal) => {
-        paste::paste! {
-            #[non_exhaustive]
-            pub struct [<Spi $num DmaChannel>] {}
-
-            impl ChannelTypes for [<Spi $num DmaChannel>] {
-                type P = [<Spi $num DmaSuitablePeripheral>];
-                type Tx<'a> = ChannelTx<'a,[<Spi $num DmaChannelTxImpl>], [<Spi $num DmaChannel>]>;
-                type Rx<'a> = ChannelRx<'a,[<Spi $num DmaChannelRxImpl>], [<Spi $num DmaChannel>]>;
-            }
-
-            impl RegisterAccess for [<Spi $num DmaChannel>] {
-                fn init_channel() {
-                    // (only) on ESP32 we need to configure DPORT for the SPI DMA channels
-                    #[cfg(esp32)]
-                    {
-                        let dport = unsafe { &*crate::peripherals::DPORT::PTR };
-
-                        match $num {
-                            2 => {
-                                dport
-                                .spi_dma_chan_sel()
-                                .modify(|_, w| w.spi2_dma_chan_sel().variant(1));
-                            },
-                            3 => {
-                                dport
-                                .spi_dma_chan_sel()
-                                .modify(|_, w| w.spi3_dma_chan_sel().variant(2));
-                            },
-                            _ => panic!("Only SPI2 and SPI3 supported"),
-                        }
-                    }
-                }
-
-                fn set_out_burstmode(burst_mode: bool) {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_conf()
-                        .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
-                }
-
-                fn set_out_priority(_priority: DmaPriority) {}
-
-                fn clear_out_interrupts() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_clr().write(|w| {
-                        w.out_done_int_clr()
-                            .set_bit()
-                            .out_eof_int_clr()
-                            .set_bit()
-                            .out_total_eof_int_clr()
-                            .set_bit()
-                            .outlink_dscr_error_int_clr()
-                            .set_bit()
-                    });
-                }
-
-                fn reset_out() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_conf().modify(|_, w| w.out_rst().set_bit());
-                    spi.dma_conf().modify(|_, w| w.out_rst().clear_bit());
-                }
-
-                fn set_out_descriptors(address: u32) {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_out_link()
-                        .modify(|_, w| unsafe { w.outlink_addr().bits(address) });
-                }
-
-                fn has_out_descriptor_error() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().outlink_dscr_error_int_raw().bit()
-                }
-
-                fn set_out_peripheral(_peripheral: u8) {
-                    // no-op
-                }
-
-                fn start_out() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_out_link().modify(|_, w| w.outlink_start().set_bit());
-                }
-
-                fn clear_ch_out_done() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_clr().write(|w| w.out_done_int_clr().set_bit());
-                }
-
-                fn is_ch_out_done_set() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().out_done_int_raw().bit()
-                }
-
-                fn listen_ch_out_done() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.out_done_int_ena().set_bit());
-                }
-
-                fn unlisten_ch_out_done() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.out_done_int_ena().clear_bit());
-                }
-
-                fn is_listening_ch_out_done() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().read().out_done_int_ena().bit()
-                }
-
-                fn is_out_done() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    // FIXME this should be out_total_eof_int_raw? but on esp32 this interrupt doesn't seem to fire
-                    spi.dma_int_raw().read().out_eof_int_raw().bit()
-                }
-
-                fn last_out_dscr_address() -> usize {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.out_eof_des_addr().read().dma_out_eof_des_addr().bits() as usize
-                }
-
-                fn is_out_eof_interrupt_set() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().out_eof_int_raw().bit()
-                }
-
-                fn reset_out_eof_interrupt() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_clr().write(|w| {
-                        w.out_eof_int_clr()
-                            .set_bit()
-                    });
-                }
-
-                fn set_in_burstmode(burst_mode: bool) {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_conf()
-                        .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
-                }
-
-                fn set_in_priority(_priority: DmaPriority) {}
-
-                fn clear_in_interrupts() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_clr().write(|w| {
-                        w.in_done_int_clr()
-                            .set_bit()
-                            .in_err_eof_int_clr()
-                            .set_bit()
-                            .in_suc_eof_int_clr()
-                            .set_bit()
-                            .inlink_dscr_error_int_clr()
-                            .set_bit()
-                    });
-                }
-
-                fn reset_in() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_conf().modify(|_, w| w.in_rst().set_bit());
-                    spi.dma_conf().modify(|_, w| w.in_rst().clear_bit());
-                }
-
-                fn set_in_descriptors(address: u32) {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_in_link()
-                        .modify(|_, w| unsafe { w.inlink_addr().bits(address) });
-                }
-
-                fn has_in_descriptor_error() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().inlink_dscr_error_int_raw().bit()
-                }
-
-                fn has_in_descriptor_error_dscr_empty() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().inlink_dscr_empty_int_raw().bit()
-                }
-
-                fn has_in_descriptor_error_err_eof() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().in_err_eof_int_raw().bit()
-                }
-
-                fn set_in_peripheral(_peripheral: u8) {
-                    // no-op
-                }
-
-                fn start_in() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_in_link().modify(|_, w| w.inlink_start().set_bit());
-                }
-
-                fn is_in_done() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().in_done_int_raw().bit()
-                }
-
-                fn last_in_dscr_address() -> usize {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.inlink_dscr_bf0().read().dma_inlink_dscr_bf0().bits() as usize
-                }
-
-                fn is_listening_in_eof() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().read().in_suc_eof_int_ena().bit_is_set()
-                }
-
-                fn is_listening_out_eof() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().read().out_total_eof_int_ena().bit_is_set()
-                }
-
-                fn listen_in_eof() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.in_suc_eof_int_ena().set_bit());
-                }
-
-                fn listen_out_eof() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.out_total_eof_int_ena().set_bit());
-                }
-
-                fn unlisten_in_eof() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.in_suc_eof_int_ena().clear_bit());
-                }
-
-                fn unlisten_out_eof() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.out_total_eof_int_ena().clear_bit());
-                }
-
-                fn listen_ch_in_done(){
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.in_done_int_ena().set_bit());
-                }
-
-                fn clear_ch_in_done(){
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_clr().write(|w| w.in_done_int_clr().set_bit());
-                }
-
-                fn is_ch_in_done_set() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_raw().read().in_done_int_raw().bit()
-                }
-
-                fn unlisten_ch_in_done() {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().modify(|_, w| w.in_done_int_ena().clear_bit());
-                }
-
-                fn is_listening_ch_in_done() -> bool {
-                    let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
-                    spi.dma_int_ena().read().in_done_int_ena().bit()
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<Spi $num DmaChannelTxImpl>] {}
-
-            impl<'a> TxChannel<[<Spi $num DmaChannel>]> for [<Spi $num DmaChannelTxImpl>] {
-                #[cfg(feature = "async")]
-                fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
-                    static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
-                    &WAKER
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<Spi $num DmaChannelRxImpl>] {}
-
-            impl<'a> RxChannel<[<Spi $num DmaChannel>]> for [<Spi $num DmaChannelRxImpl>] {
-                #[cfg(feature = "async")]
-                fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
-                    static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
-                    &WAKER
-                }
-            }
-
-            #[non_exhaustive]
-            pub struct [<Spi $num DmaChannelCreator>] {}
-
-            impl [<Spi $num DmaChannelCreator>] {
-                /// Configure the channel for use
-                ///
-                /// Descriptors should be sized as `((CHUNK_SIZE + 4091) / 4092) * 3`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 3 descriptors. The number of
-                /// descriptors must be a multiple of 3.
-                pub fn configure<'a>(
-                    self,
-                    burst_mode: bool,
-                    tx_descriptors: &'a mut [u32],
-                    rx_descriptors: &'a mut [u32],
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<Spi $num DmaChannel>]> {
-                    if tx_descriptors.len() % 3 != 0 {
-                        on_tx_descriptor_not_divisible_by_3();
-                    }
-
-                    if rx_descriptors.len() % 3 != 0 {
-                        on_rx_descriptor_not_divisible_by_3();
-                    }
-
-                    let mut tx_impl = [<Spi $num DmaChannelTxImpl>] {};
-                    tx_impl.init(burst_mode, priority);
-
-                    let tx_channel = ChannelTx {
-                        descriptors: tx_descriptors,
-                        burst_mode,
-                        tx_impl: tx_impl,
-                        write_offset: 0,
-                        write_descr_ptr: core::ptr::null(),
-                        available: 0,
-                        last_seen_handled_descriptor_ptr: core::ptr::null(),
-                        buffer_start: core::ptr::null(),
-                        buffer_len: 0,
-                        _phantom: PhantomData::default(),
-                    };
-
-                    let mut rx_impl = [<Spi $num DmaChannelRxImpl>] {};
-                    rx_impl.init(burst_mode, priority);
-
-                    let rx_channel = ChannelRx {
-                        descriptors: rx_descriptors,
-                        burst_mode,
-                        rx_impl: rx_impl,
-                        read_descr_ptr: core::ptr::null(),
-                        available: 0,
-                        last_seen_handled_descriptor_ptr: core::ptr::null(),
-                        read_buffer_start: core::ptr::null(),
-                        _phantom: PhantomData::default(),
-                    };
-
-                    Channel {
-                        tx: tx_channel,
-                        rx: rx_channel,
-                    }
-                }
-            }
-        }
-    };
-}
-
-macro_rules! ImplI2sChannel {
-    ($num: literal, $peripheral: literal) => {
-        paste::paste! {
-            pub struct [<I2s $num DmaChannel>] {}
-
-            impl ChannelTypes for [<I2s $num DmaChannel>] {
-                type P = [<I2s $num DmaSuitablePeripheral>];
-                type Tx<'a> = ChannelTx<'a,[<I2s $num DmaChannelTxImpl>], [<I2s $num DmaChannel>]>;
-                type Rx<'a> = ChannelRx<'a,[<I2s $num DmaChannelRxImpl>], [<I2s $num DmaChannel>]>;
-            }
-
-            impl RegisterAccess for [<I2s $num DmaChannel>] {
-                fn init_channel() {
-                    // nothing to do
-                }
-
-                fn set_out_burstmode(burst_mode: bool) {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.lc_conf()
-                        .modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
-                }
-
-                fn set_out_priority(_priority: DmaPriority) {}
-
-                fn clear_out_interrupts() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_clr().write(|w| {
-                        w.out_done_int_clr()
-                            .set_bit()
-                            .out_eof_int_clr()
-                            .set_bit()
-                            .out_total_eof_int_clr()
-                            .set_bit()
-                            .out_dscr_err_int_clr()
-                            .set_bit()
-                    });
-                }
-
-                fn reset_out() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.lc_conf().modify(|_, w| w.out_rst().set_bit());
-                    reg_block.lc_conf().modify(|_, w| w.out_rst().clear_bit());
-                }
-
-                fn set_out_descriptors(address: u32) {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.out_link()
-                        .modify(|_, w| unsafe { w.outlink_addr().bits(address) });
-                }
-
-                fn has_out_descriptor_error() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().out_dscr_err_int_raw().bit()
-                }
-
-                fn set_out_peripheral(_peripheral: u8) {
-                    // no-op
-                }
-
-                fn start_out() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.out_link().modify(|_, w| w.outlink_start().set_bit());
-                }
-
-                fn clear_ch_out_done() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_clr().write(|w| w.out_done_int_clr().set_bit());
-                }
-
-                fn is_ch_out_done_set() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().out_done_int_raw().bit()
-                }
-
-                fn listen_ch_out_done() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_, w| w.out_done_int_ena().set_bit());
-                }
-
-                fn unlisten_ch_out_done() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_, w| w.out_done_int_ena().clear_bit());
-                }
-
-                fn is_listening_ch_out_done() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().read().out_done_int_ena().bit()
-                }
-
-                fn is_out_done() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().out_eof_int_raw().bit()
-                }
-
-                fn last_out_dscr_address() -> usize {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.out_eof_des_addr().read().out_eof_des_addr().bits() as usize
-                }
-
-                fn is_out_eof_interrupt_set() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().out_eof_int_raw().bit()
-                }
-
-                fn reset_out_eof_interrupt() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_clr().write(|w| {
-                        w.out_eof_int_clr()
-                            .set_bit()
-                    });
-                }
-
-                fn set_in_burstmode(burst_mode: bool) {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.lc_conf()
-                        .modify(|_, w| w.indscr_burst_en().bit(burst_mode));
-                }
-
-                fn set_in_priority(_priority: DmaPriority) {}
-
-                fn clear_in_interrupts() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_clr().write(|w| {
-                        w.in_done_int_clr()
-                            .set_bit()
-                            .in_err_eof_int_clr()
-                            .set_bit()
-                            .in_suc_eof_int_clr()
-                            .set_bit()
-                            .in_dscr_err_int_clr()
-                            .set_bit()
-                    });
-                }
-
-                fn reset_in() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.lc_conf().modify(|_, w| w.in_rst().set_bit());
-                    reg_block.lc_conf().modify(|_, w| w.in_rst().clear_bit());
-                }
-
-                fn set_in_descriptors(address: u32) {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.in_link()
-                        .modify(|_, w| unsafe { w.inlink_addr().bits(address) });
-                }
-
-                fn has_in_descriptor_error() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().in_dscr_err_int_raw().bit()
-                }
-
-                fn has_in_descriptor_error_dscr_empty() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().in_dscr_empty_int_raw().bit()
-                }
-
-                fn has_in_descriptor_error_err_eof() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().in_err_eof_int_raw().bit()
-                }
-
-                fn set_in_peripheral(_peripheral: u8) {
-                    // no-op
-                }
-
-                fn start_in() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.in_link().modify(|_, w| w.inlink_start().set_bit());
-                }
-
-                fn is_in_done() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().in_done_int_raw().bit()
-                }
-
-                fn last_in_dscr_address() -> usize {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.inlink_dscr_bf0().read().inlink_dscr_bf0().bits() as usize
-                }
-
-                fn is_listening_in_eof() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().read().in_suc_eof_int_ena().bit()
-                }
-
-                fn is_listening_out_eof() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().read().out_eof_int_ena().bit()
-                }
-
-                fn listen_in_eof() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_,w| w.in_suc_eof_int_ena().set_bit() );
-                }
-
-                fn listen_out_eof() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_,w| w.out_eof_int_ena().set_bit() );
-                }
-
-                fn unlisten_in_eof() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_,w| w.in_suc_eof_int_ena().clear_bit() );
-                }
-
-                fn unlisten_out_eof() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_,w| w.out_eof_int_ena().clear_bit() );
-                }
-
-                fn listen_ch_in_done(){
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_, w| w.in_done_int_ena().set_bit());
-                }
-
-                fn clear_ch_in_done(){
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_clr().write(|w| w.in_done_int_clr().set_bit());
-                }
-
-                fn is_ch_in_done_set() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_raw().read().in_done_int_raw().bit()
-                }
-
-                fn unlisten_ch_in_done() {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().modify(|_, w| w.in_done_int_ena().clear_bit());
-                }
-
-                fn is_listening_ch_in_done() -> bool {
-                    let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
-                    reg_block.int_ena().read().in_done_int_ena().bit()
-                }
-            }
-
-            pub struct [<I2s $num DmaChannelTxImpl>] {}
-
-            impl<'a> TxChannel<[<I2s $num DmaChannel>]> for [<I2s $num DmaChannelTxImpl>] {
-                #[cfg(feature = "async")]
-                fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
-                    static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
-                    &WAKER
-                }
-            }
-
-            pub struct [<I2s $num DmaChannelRxImpl>] {}
-
-            impl<'a> RxChannel<[<I2s $num DmaChannel>]> for [<I2s $num DmaChannelRxImpl>] {
-                #[cfg(feature = "async")]
-                fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
-                    static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
-                    &WAKER
-                }
-            }
-
-            pub struct [<I2s $num DmaChannelCreator>] {}
-
-            impl [<I2s $num DmaChannelCreator>] {
-                /// Configure the channel for use
-                ///
-                /// Descriptors should be sized as `((CHUNK_SIZE + 4091) / 4092) * 3`. I.e., to
-                /// transfer buffers of size `1..=4092`, you need 3 descriptors.
-                pub fn configure<'a>(
-                    self,
-                    burst_mode: bool,
-                    tx_descriptors: &'a mut [u32],
-                    rx_descriptors: &'a mut [u32],
-                    priority: DmaPriority,
-                ) -> Channel<'a, [<I2s $num DmaChannel>]> {
-                    let mut tx_impl = [<I2s $num DmaChannelTxImpl>] {};
-                    tx_impl.init(burst_mode, priority);
-
-                    let tx_channel = ChannelTx {
-                        descriptors: tx_descriptors,
-                        burst_mode,
-                        tx_impl: tx_impl,
-                        write_offset: 0,
-                        write_descr_ptr: core::ptr::null(),
-                        available: 0,
-                        last_seen_handled_descriptor_ptr: core::ptr::null(),
-                        buffer_start: core::ptr::null(),
-                        buffer_len: 0,
-                        _phantom: PhantomData::default(),
-                    };
-
-                    let mut rx_impl = [<I2s $num DmaChannelRxImpl>] {};
-                    rx_impl.init(burst_mode, priority);
-
-                    let rx_channel = ChannelRx {
-                        descriptors: rx_descriptors,
-                        burst_mode,
-                        rx_impl: rx_impl,
-                        read_descr_ptr: core::ptr::null(),
-                        available: 0,
-                        last_seen_handled_descriptor_ptr: core::ptr::null(),
-                        read_buffer_start: core::ptr::null(),
-                        _phantom: PhantomData::default(),
-                    };
-
-                    Channel {
-                        tx: tx_channel,
-                        rx: rx_channel,
-                    }
-                }
-            }
-        }
-    };
-}
-
-#[non_exhaustive]
-pub struct Spi2DmaSuitablePeripheral {}
-impl PeripheralMarker for Spi2DmaSuitablePeripheral {}
-impl SpiPeripheral for Spi2DmaSuitablePeripheral {}
-impl Spi2Peripheral for Spi2DmaSuitablePeripheral {}
-
-#[non_exhaustive]
-pub struct Spi3DmaSuitablePeripheral {}
-impl PeripheralMarker for Spi3DmaSuitablePeripheral {}
-impl SpiPeripheral for Spi3DmaSuitablePeripheral {}
-impl Spi3Peripheral for Spi3DmaSuitablePeripheral {}
-
-ImplSpiChannel!(2);
-ImplSpiChannel!(3);
-
-#[non_exhaustive]
-pub struct I2s0DmaSuitablePeripheral {}
-impl PeripheralMarker for I2s0DmaSuitablePeripheral {}
-impl I2sPeripheral for I2s0DmaSuitablePeripheral {}
-impl I2s0Peripheral for I2s0DmaSuitablePeripheral {}
-
-ImplI2sChannel!(0, "I2S0");
-
-#[non_exhaustive]
-pub struct I2s1DmaSuitablePeripheral {}
-impl PeripheralMarker for I2s1DmaSuitablePeripheral {}
-impl I2sPeripheral for I2s1DmaSuitablePeripheral {}
-impl I2s1Peripheral for I2s1DmaSuitablePeripheral {}
-
-#[cfg(esp32)]
-ImplI2sChannel!(1, "I2S1");
-
-/// DMA Peripheral
-///
-/// This offers the available DMA channels.
-pub struct Dma<'d> {
-    _inner: PeripheralRef<'d, crate::system::Dma>,
-    pub spi2channel: Spi2DmaChannelCreator,
-    pub spi3channel: Spi3DmaChannelCreator,
-    pub i2s0channel: I2s0DmaChannelCreator,
-    #[cfg(esp32)]
-    pub i2s1channel: I2s1DmaChannelCreator,
-}
-
-impl<'d> Dma<'d> {
-    /// Create a DMA instance.
-    pub fn new(dma: impl crate::peripheral::Peripheral<P = crate::system::Dma> + 'd) -> Dma<'d> {
-        PeripheralClockControl::enable(Peripheral::Dma);
-
-        Dma {
-            _inner: dma.into_ref(),
-            spi2channel: Spi2DmaChannelCreator {},
-            spi3channel: Spi3DmaChannelCreator {},
-            i2s0channel: I2s0DmaChannelCreator {},
-            #[cfg(esp32)]
-            i2s1channel: I2s1DmaChannelCreator {},
-        }
-    }
-}

esp-hal-common/src/embassy/executor/interrupt.rs

@@ -1,178 +0,0 @@
-//! Interrupt-mode executor.
-use core::{cell::UnsafeCell, marker::PhantomData, mem::MaybeUninit};
-
-use embassy_executor::{raw, SendSpawner};
-#[cfg(any(esp32c6, esp32h2))]
-use peripherals::INTPRI as SystemPeripheral;
-#[cfg(not(any(esp32c6, esp32h2)))]
-use peripherals::SYSTEM as SystemPeripheral;
-use portable_atomic::{AtomicUsize, Ordering};
-
-use crate::{get_core, interrupt, peripherals};
-
-static FROM_CPU_IRQ_USED: AtomicUsize = AtomicUsize::new(0);
-
-pub trait SwPendableInterrupt {
-    fn enable(priority: interrupt::Priority);
-    fn number() -> usize;
-    fn pend();
-    fn clear();
-}
-
-macro_rules! from_cpu {
-    ($irq:literal) => {
-        paste::paste! {
-            pub struct [<FromCpu $irq>];
-
-            impl [<FromCpu $irq>] {
-                fn set_bit(value: bool) {
-                    let system = unsafe { &*SystemPeripheral::PTR };
-
-                    system
-                        .[<cpu_intr_from_cpu_ $irq>]()
-                        .write(|w| w.[<cpu_intr_from_cpu_ $irq>]().bit(value));
-                }
-            }
-
-            impl SwPendableInterrupt for [<FromCpu $irq>] {
-                fn enable(priority: interrupt::Priority) {
-                    let mask = 1 << $irq;
-                    // We don't allow using the same interrupt for multiple executors.
-                    if FROM_CPU_IRQ_USED.fetch_or(mask, Ordering::SeqCst) & mask != 0 {
-                        panic!("FROM_CPU_{} is already used by a different executor.", $irq);
-                    }
-
-                    // unsafe block because of direct-vectoring on riscv
-                    #[allow(unused_unsafe)]
-                    unsafe {
-                        unwrap!(interrupt::enable(peripherals::Interrupt::[<FROM_CPU_INTR $irq>], priority));
-                    }
-                }
-
-                fn number() -> usize {
-                    $irq
-                }
-
-                fn pend() {
-                    Self::set_bit(true);
-                }
-
-                fn clear() {
-                    Self::set_bit(false);
-                }
-            }
-        }
-    };
-}
-
-// from_cpu!(0); // reserve 0 for thread mode & multi-core
-from_cpu!(1);
-from_cpu!(2);
-from_cpu!(3);
-
-/// Interrupt mode executor.
-///
-/// This executor runs tasks in interrupt mode. The interrupt handler is set up
-/// to poll tasks, and when a task is woken the interrupt is pended from
-/// software.
-///
-/// # Interrupt requirements
-///
-/// You must write the interrupt handler yourself, and make it call
-/// [`Self::on_interrupt()`]
-///
-/// ```rust,ignore
-/// #[interrupt]
-/// fn FROM_CPU_INTR1() {
-///     unsafe { INT_EXECUTOR.on_interrupt() }
-/// }
-/// ```
-pub struct InterruptExecutor<SWI>
-where
-    SWI: SwPendableInterrupt,
-{
-    core: AtomicUsize,
-    executor: UnsafeCell<MaybeUninit<raw::Executor>>,
-    _interrupt: PhantomData<SWI>,
-}
-
-unsafe impl<SWI: SwPendableInterrupt> Send for InterruptExecutor<SWI> {}
-unsafe impl<SWI: SwPendableInterrupt> Sync for InterruptExecutor<SWI> {}
-
-impl<SWI> InterruptExecutor<SWI>
-where
-    SWI: SwPendableInterrupt,
-{
-    /// Create a new `InterruptExecutor`.
-    #[inline]
-    pub const fn new() -> Self {
-        Self {
-            core: AtomicUsize::new(usize::MAX),
-            executor: UnsafeCell::new(MaybeUninit::uninit()),
-            _interrupt: PhantomData,
-        }
-    }
-
-    /// Executor interrupt callback.
-    ///
-    /// # Safety
-    ///
-    /// You MUST call this from the interrupt handler, and from nowhere else.
-    // TODO: it would be pretty sweet if we could register our own interrupt handler
-    // when vectoring is enabled. The user shouldn't need to provide the handler for
-    // us.
-    pub unsafe fn on_interrupt(&'static self) {
-        SWI::clear();
-        let executor = unsafe { (*self.executor.get()).assume_init_ref() };
-        executor.poll();
-    }
-
-    /// Start the executor at the given priority level.
-    ///
-    /// This initializes the executor, enables the interrupt, and returns.
-    /// The executor keeps running in the background through the interrupt.
-    ///
-    /// This returns a [`SendSpawner`] you can use to spawn tasks on it. A
-    /// [`SendSpawner`] is returned instead of a [`Spawner`] because the
-    /// executor effectively runs in a different "thread" (the interrupt),
-    /// so spawning tasks on it is effectively sending them.
-    ///
-    /// To obtain a [`Spawner`] for this executor, use
-    /// [`Spawner::for_current_executor()`] from a task running in it.
-    ///
-    /// # Interrupt requirements
-    ///
-    /// You must write the interrupt handler yourself, and make it call
-    /// [`Self::on_interrupt()`]
-    ///
-    /// This method already enables (unmasks) the interrupt, you must NOT do it
-    /// yourself.
-    ///
-    /// [`Spawner`]: embassy_executor::Spawner
-    /// [`Spawner::for_current_executor()`]: embassy_executor::Spawner::for_current_executor()
-    pub fn start(&'static self, priority: interrupt::Priority) -> SendSpawner {
-        if self
-            .core
-            .compare_exchange(
-                usize::MAX,
-                get_core() as usize,
-                Ordering::Acquire,
-                Ordering::Relaxed,
-            )
-            .is_err()
-        {
-            panic!("InterruptExecutor::start() called multiple times on the same executor.");
-        }
-
-        unsafe {
-            (*self.executor.get())
-                .as_mut_ptr()
-                .write(raw::Executor::new(SWI::number() as *mut ()))
-        }
-
-        SWI::enable(priority);
-
-        let executor = unsafe { (*self.executor.get()).assume_init_ref() };
-        executor.spawner().make_send()
-    }
-}

esp-hal-common/src/embassy/executor/mod.rs

@@ -1,35 +0,0 @@
-#[cfg(feature = "embassy-executor-thread")]
-pub mod thread;
-
-#[cfg(feature = "embassy-executor-thread")]
-pub use thread::*;
-
-#[cfg(feature = "embassy-executor-interrupt")]
-pub mod interrupt;
-
-#[cfg(feature = "embassy-executor-interrupt")]
-pub use interrupt::*;
-
-#[cfg(any(
-    feature = "embassy-executor-thread",
-    feature = "embassy-executor-interrupt",
-))]
-#[export_name = "__pender"]
-fn __pender(context: *mut ()) {
-    let context = (context as usize).to_le_bytes();
-
-    cfg_if::cfg_if! {
-        if #[cfg(feature = "embassy-executor-interrupt")] {
-            match context[0] {
-                #[cfg(feature = "embassy-executor-thread")]
-                0 => thread::pend_thread_mode(context[1] as usize),
-                1 => FromCpu1::pend(),
-                2 => FromCpu2::pend(),
-                3 => FromCpu3::pend(),
-                _ => {}
-            }
-        } else {
-            pend_thread_mode(context[1] as usize);
-        }
-    }
-}

esp-hal-common/src/embassy/executor/thread.rs

@@ -1,159 +0,0 @@
-//! Multicore-aware thread-mode embassy executor.
-use core::marker::PhantomData;
-
-use embassy_executor::{raw, Spawner};
-use portable_atomic::{AtomicBool, Ordering};
-
-use crate::{get_core, prelude::interrupt};
-#[cfg(multi_core)]
-use crate::{
-    interrupt,
-    peripherals::{self, SYSTEM},
-};
-
-/// global atomic used to keep track of whether there is work to do since sev()
-/// is not available on either Xtensa or RISC-V
-#[cfg(not(multi_core))]
-static SIGNAL_WORK_THREAD_MODE: [AtomicBool; 1] = [AtomicBool::new(false)];
-#[cfg(multi_core)]
-static SIGNAL_WORK_THREAD_MODE: [AtomicBool; 2] = [AtomicBool::new(false), AtomicBool::new(false)];
-
-#[interrupt]
-fn FROM_CPU_INTR0() {
-    #[cfg(multi_core)]
-    {
-        // This interrupt is fired when the thread-mode executor's core needs to be
-        // woken. It doesn't matter which core handles this interrupt first, the
-        // point is just to wake up the core that is currently executing
-        // `waiti`.
-        let system = unsafe { &*SYSTEM::PTR };
-        system
-            .cpu_intr_from_cpu_0()
-            .write(|w| w.cpu_intr_from_cpu_0().bit(false));
-    }
-}
-
-pub(crate) fn pend_thread_mode(core: usize) {
-    // Signal that there is work to be done.
-    SIGNAL_WORK_THREAD_MODE[core].store(true, Ordering::SeqCst);
-
-    // If we are pending a task on the current core, we're done. Otherwise, we
-    // need to make sure the other core wakes up.
-    #[cfg(multi_core)]
-    if core != crate::get_core() as usize {
-        // We need to clear the interrupt from software. We don't actually
-        // need it to trigger and run the interrupt handler, we just need to
-        // kick waiti to return.
-
-        let system = unsafe { &*SYSTEM::PTR };
-        system
-            .cpu_intr_from_cpu_0()
-            .write(|w| w.cpu_intr_from_cpu_0().bit(true));
-    }
-}
-
-/// Multi-core Xtensa Executor
-pub struct Executor {
-    inner: raw::Executor,
-    not_send: PhantomData<*mut ()>,
-}
-
-impl Executor {
-    /// Create a new Executor.
-    pub fn new() -> Self {
-        #[cfg(multi_core)]
-        unwrap!(interrupt::enable(
-            peripherals::Interrupt::FROM_CPU_INTR0,
-            interrupt::Priority::Priority1,
-        ));
-
-        Self {
-            inner: raw::Executor::new(usize::from_le_bytes([0, get_core() as u8, 0, 0]) as *mut ()),
-            not_send: PhantomData,
-        }
-    }
-
-    /// Run the executor.
-    ///
-    /// The `init` closure is called with a [`Spawner`] that spawns tasks on
-    /// this executor. Use it to spawn the initial task(s). After `init`
-    /// returns, the executor starts running the tasks.
-    ///
-    /// To spawn more tasks later, you may keep copies of the [`Spawner`] (it is
-    /// `Copy`), for example by passing it as an argument to the initial
-    /// tasks.
-    ///
-    /// This function requires `&'static mut self`. This means you have to store
-    /// the Executor instance in a place where it'll live forever and grants
-    /// you mutable access. There's a few ways to do this:
-    ///
-    /// - a [StaticCell](https://docs.rs/static_cell/latest/static_cell/) (safe)
-    /// - a `static mut` (unsafe)
-    /// - a local variable in a function you know never returns (like `fn main()
-    ///   -> !`), upgrading its lifetime with `transmute`. (unsafe)
-    ///
-    /// This function never returns.
-    pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
-        init(self.inner.spawner());
-
-        let cpu = get_core() as usize;
-
-        loop {
-            unsafe {
-                self.inner.poll();
-
-                Self::wait_impl(cpu);
-            }
-        }
-    }
-
-    #[cfg(xtensa)]
-    pub fn wait_impl(cpu: usize) {
-        // Manual critical section implementation that only masks interrupts handlers.
-        // We must not acquire the cross-core on dual-core systems because that would
-        // prevent the other core from doing useful work while this core is sleeping.
-        let token: critical_section::RawRestoreState;
-        unsafe { core::arch::asm!("rsil {0}, 5", out(reg) token) };
-
-        // we do not care about race conditions between the load and store operations,
-        // interrupts will only set this value to true.
-        if SIGNAL_WORK_THREAD_MODE[cpu].load(Ordering::SeqCst) {
-            SIGNAL_WORK_THREAD_MODE[cpu].store(false, Ordering::SeqCst);
-
-            // if there is work to do, exit critical section and loop back to polling
-            unsafe {
-                core::arch::asm!(
-                    "wsr.ps {0}",
-                    "rsync",
-                    in(reg) token
-                );
-            }
-        } else {
-            // waiti sets the PS.INTLEVEL when slipping into sleep
-            // because critical sections in Xtensa are implemented via increasing
-            // PS.INTLEVEL the critical section ends here
-            // take care not add code after `waiti` if it needs to be inside the CS
-            unsafe { core::arch::asm!("waiti 0") }; // critical section ends
-                                                    // here
-        }
-    }
-
-    #[cfg(riscv)]
-    pub fn wait_impl(cpu: usize) {
-        // we do not care about race conditions between the load and store operations,
-        // interrupts will only set this value to true.
-        critical_section::with(|_| {
-            // if there is work to do, loop back to polling
-            // TODO can we relax this?
-            if SIGNAL_WORK_THREAD_MODE[cpu].load(Ordering::SeqCst) {
-                SIGNAL_WORK_THREAD_MODE[cpu].store(false, Ordering::SeqCst);
-            }
-            // if not, wait for interrupt
-            else {
-                unsafe { core::arch::asm!("wfi") };
-            }
-        });
-        // if an interrupt occurred while waiting, it will be serviced
-        // here
-    }
-}

esp-hal-common/src/embassy/mod.rs

@@ -1,218 +0,0 @@
-//! # Embassy driver
-//!
-//! ## Overview
-//! The `embassy` driver for ESP chips is an essential part of the Embassy
-//! embedded async/await runtime and is used by applications to perform
-//! time-based operations and schedule asynchronous tasks. It provides a
-//! high-level API for handling timers and alarms, abstracting the underlying
-//! hardware details, and allowing users to focus on application logic rather
-//! than low-level timer management.
-//!
-//! Here are important details about the module:
-//!   * `time_driver` module (`time_driver_systimer` or `time_driver_timg`,
-//!     depends on enabled feature)
-//!     - This module contains the implementations of the timer drivers for
-//!       different ESP chips.<br> It includes the `EmbassyTimer` struct, which
-//!       is responsible for handling alarms and timer events.
-//!     - `EmbassyTimer` struct represents timer driver for ESP chips. It
-//!       contains `alarms` - an array of `AlarmState` structs, which describe
-//!       the state of alarms associated with the timer driver.
-//!   * `AlarmState` struct
-//!     - This struct represents the state of an alarm. It contains information
-//!       about the alarm's timestamp, a callback function to be executed when
-//!       the alarm triggers, and a context pointer for passing user-defined
-//!       data to the callback.
-//!   * `executor` module
-//!     - This module contains the implementations of a multi-core safe
-//!       thread-mode and an interrupt-mode executor for Xtensa-based ESP chips.
-//!
-//! ## Example
-//! The following example demonstrates how to use the `embassy` driver to
-//! schedule asynchronous tasks.<br> In this example, we use the `embassy`
-//! driver to wait for a GPIO 9 pin state to change.
-//!
-//! ```no_run
-//! #[cfg(feature = "embassy-time-systick")]
-//! embassy::init(
-//!     &clocks,
-//!     esp32c6_hal::systimer::SystemTimer::new(peripherals.SYSTIMER),
-//! );
-//!
-//! #[cfg(feature = "embassy-time-timg0")]
-//! embassy::init(&clocks, timer_group0.timer0);
-//!
-//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
-//! // GPIO 9 as input
-//! let input = io.pins.gpio9.into_pull_down_input();
-//!
-//! // Async requires the GPIO interrupt to wake futures
-//! esp32c6_hal::interrupt::enable(
-//!     esp32c6_hal::peripherals::Interrupt::GPIO,
-//!     esp32c6_hal::interrupt::Priority::Priority1,
-//! )
-//! .unwrap();
-//!
-//! let executor = make_static!(Executor::new());
-//! executor.run(|spawner| {
-//!     spawner.spawn(ping(input)).ok();
-//! });
-//! ```
-//!
-//! Where `ping` defined as:
-//! ```no_run
-//! async fn ping(mut pin: Gpio9<Input<PullDown>>) {
-//!     loop {
-//!         esp_println::println!("Waiting...");
-//!         pin.wait_for_rising_edge().await.unwrap();
-//!         esp_println::println!("Ping!");
-//!         Timer::after(Duration::from_millis(100)).await;
-//!     }
-//! }
-//! ```
-//! For more embassy-related examples check out the [examples repo](https://github.com/esp-rs/esp-hal/tree/main/esp32-hal/examples)
-//! for a corresponding board.
-
-#[cfg(any(
-    feature = "embassy-executor-interrupt",
-    feature = "embassy-executor-thread"
-))]
-pub mod executor;
-
-use core::cell::Cell;
-
-use embassy_time::driver::{AlarmHandle, Driver};
-
-use crate::{interrupt::Priority, peripherals::Interrupt};
-
-#[cfg_attr(
-    all(systimer, feature = "embassy-time-systick"),
-    path = "time_driver_systimer.rs"
-)]
-#[cfg_attr(
-    all(timg0, feature = "embassy-time-timg0"),
-    path = "time_driver_timg.rs"
-)]
-mod time_driver;
-
-use time_driver::EmbassyTimer;
-
-use crate::clock::Clocks;
-
-/// Initialise embassy, including setting up interrupts for the DMA and async
-/// enabled peripherals.
-pub fn init(clocks: &Clocks, td: time_driver::TimerType) {
-    #[cfg(any(esp32s3, esp32c6, esp32h2))]
-    crate::interrupt::enable(Interrupt::DMA_IN_CH0, Priority::max()).unwrap();
-    #[cfg(any(esp32s3, esp32c6, esp32h2))]
-    crate::interrupt::enable(Interrupt::DMA_OUT_CH0, Priority::max()).unwrap();
-    #[cfg(any(esp32s3, esp32c6, esp32h2))]
-    crate::interrupt::enable(Interrupt::DMA_IN_CH1, Priority::max()).unwrap();
-    #[cfg(any(esp32s3, esp32c6, esp32h2))]
-    crate::interrupt::enable(Interrupt::DMA_OUT_CH1, Priority::max()).unwrap();
-    #[cfg(any(esp32s3, esp32c6, esp32h2))]
-    crate::interrupt::enable(Interrupt::DMA_IN_CH2, Priority::max()).unwrap();
-    #[cfg(any(esp32s3, esp32c6, esp32h2))]
-    crate::interrupt::enable(Interrupt::DMA_OUT_CH2, Priority::max()).unwrap();
-
-    #[cfg(esp32s3)]
-    crate::interrupt::enable(Interrupt::DMA_IN_CH3, Priority::max()).unwrap();
-    #[cfg(esp32s3)]
-    crate::interrupt::enable(Interrupt::DMA_OUT_CH3, Priority::max()).unwrap();
-
-    #[cfg(any(esp32c3, esp32c2))]
-    crate::interrupt::enable(Interrupt::DMA_CH0, Priority::max()).unwrap();
-    #[cfg(esp32c3)]
-    crate::interrupt::enable(Interrupt::DMA_CH1, Priority::max()).unwrap();
-    #[cfg(esp32c3)]
-    crate::interrupt::enable(Interrupt::DMA_CH2, Priority::max()).unwrap();
-
-    #[cfg(any(esp32))]
-    crate::interrupt::enable(Interrupt::SPI1_DMA, Priority::max()).unwrap();
-    #[cfg(any(esp32, esp32s2))]
-    crate::interrupt::enable(Interrupt::SPI2_DMA, Priority::max()).unwrap();
-    #[cfg(any(esp32, esp32s2))]
-    crate::interrupt::enable(Interrupt::SPI3_DMA, Priority::max()).unwrap();
-    #[cfg(esp32s2)]
-    crate::interrupt::enable(Interrupt::SPI4_DMA, Priority::max()).unwrap();
-
-    #[cfg(i2s0)]
-    crate::interrupt::enable(Interrupt::I2S0, Priority::min()).unwrap();
-    #[cfg(i2s1)]
-    crate::interrupt::enable(Interrupt::I2S1, Priority::min()).unwrap();
-
-    #[cfg(rmt)]
-    crate::interrupt::enable(Interrupt::RMT, Priority::min()).unwrap();
-
-    #[cfg(usb_device)]
-    crate::interrupt::enable(Interrupt::USB_DEVICE, Priority::min()).unwrap();
-
-    #[cfg(all(parl_io, not(esp32h2)))]
-    crate::interrupt::enable(Interrupt::PARL_IO, Priority::min()).unwrap();
-    #[cfg(all(parl_io, esp32h2))]
-    crate::interrupt::enable(Interrupt::PARL_IO_RX, Priority::min()).unwrap();
-    #[cfg(all(parl_io, esp32h2))]
-    crate::interrupt::enable(Interrupt::PARL_IO_TX, Priority::min()).unwrap();
-
-    #[cfg(uart0)]
-    crate::interrupt::enable(Interrupt::UART0, Priority::min()).unwrap();
-    #[cfg(uart1)]
-    crate::interrupt::enable(Interrupt::UART1, Priority::min()).unwrap();
-
-    crate::interrupt::enable(Interrupt::I2C_EXT0, Priority::min()).unwrap();
-    crate::interrupt::enable(Interrupt::GPIO, Priority::min()).unwrap();
-
-    EmbassyTimer::init(clocks, td)
-}
-
-pub struct AlarmState {
-    pub callback: Cell<Option<(fn(*mut ()), *mut ())>>,
-    pub allocated: Cell<bool>,
-}
-
-unsafe impl Send for AlarmState {}
-
-impl AlarmState {
-    pub const fn new() -> Self {
-        Self {
-            callback: Cell::new(None),
-            allocated: Cell::new(false),
-        }
-    }
-}
-
-impl Driver for EmbassyTimer {
-    fn now(&self) -> u64 {
-        EmbassyTimer::now()
-    }
-
-    unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {
-        critical_section::with(|cs| {
-            for (i, alarm) in self.alarms.borrow(cs).iter().enumerate() {
-                if !alarm.allocated.get() {
-                    // set alarm so it is not overwritten
-                    alarm.allocated.set(true);
-                    self.on_alarm_allocated(i);
-                    return Some(AlarmHandle::new(i as u8));
-                }
-            }
-            None
-        })
-    }
-
-    fn set_alarm_callback(
-        &self,
-        alarm: embassy_time::driver::AlarmHandle,
-        callback: fn(*mut ()),
-        ctx: *mut (),
-    ) {
-        let n = alarm.id() as usize;
-        critical_section::with(|cs| {
-            let alarm = &self.alarms.borrow(cs)[n];
-            alarm.callback.set(Some((callback, ctx)));
-        })
-    }
-
-    fn set_alarm(&self, alarm: embassy_time::driver::AlarmHandle, timestamp: u64) -> bool {
-        self.set_alarm(alarm, timestamp)
-    }
-}

esp-hal-common/src/embassy/time_driver_systimer.rs

@@ -1,127 +0,0 @@
-use critical_section::{CriticalSection, Mutex};
-
-use super::AlarmState;
-use crate::{
-    clock::Clocks,
-    peripherals,
-    systimer::{Alarm, SystemTimer, Target},
-};
-
-pub const ALARM_COUNT: usize = 3;
-
-pub type TimerType = SystemTimer<'static>;
-
-pub struct EmbassyTimer {
-    pub(crate) alarms: Mutex<[AlarmState; ALARM_COUNT]>,
-    pub(crate) alarm0: Alarm<Target, 0>,
-    pub(crate) alarm1: Alarm<Target, 1>,
-    pub(crate) alarm2: Alarm<Target, 2>,
-}
-
-const ALARM_STATE_NONE: AlarmState = AlarmState::new();
-
-embassy_time::time_driver_impl!(static DRIVER: EmbassyTimer = EmbassyTimer {
-    alarms: Mutex::new([ALARM_STATE_NONE; ALARM_COUNT]),
-    alarm0: unsafe { Alarm::<_, 0>::conjure() },
-    alarm1: unsafe { Alarm::<_, 1>::conjure() },
-    alarm2: unsafe { Alarm::<_, 2>::conjure() },
-});
-
-impl EmbassyTimer {
-    pub(crate) fn now() -> u64 {
-        SystemTimer::now()
-    }
-
-    fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
-        let alarm = &self.alarms.borrow(cs)[n];
-
-        if let Some((f, ctx)) = alarm.callback.get() {
-            f(ctx);
-        }
-    }
-
-    pub(super) fn on_alarm_allocated(&self, n: usize) {
-        match n {
-            0 => self.alarm0.enable_interrupt(true),
-            1 => self.alarm1.enable_interrupt(true),
-            2 => self.alarm2.enable_interrupt(true),
-            _ => {}
-        }
-    }
-
-    fn on_interrupt(&self, id: usize) {
-        critical_section::with(|cs| {
-            self.clear_interrupt(id);
-            self.trigger_alarm(id, cs);
-        })
-    }
-
-    pub fn init(_clocks: &Clocks, _systimer: TimerType) {
-        use crate::{interrupt, interrupt::Priority, macros::interrupt};
-
-        unwrap!(interrupt::enable(
-            peripherals::Interrupt::SYSTIMER_TARGET0,
-            Priority::max()
-        ));
-        unwrap!(interrupt::enable(
-            peripherals::Interrupt::SYSTIMER_TARGET1,
-            Priority::max()
-        ));
-        unwrap!(interrupt::enable(
-            peripherals::Interrupt::SYSTIMER_TARGET2,
-            Priority::max()
-        ));
-
-        #[interrupt]
-        fn SYSTIMER_TARGET0() {
-            DRIVER.on_interrupt(0);
-        }
-        #[interrupt]
-        fn SYSTIMER_TARGET1() {
-            DRIVER.on_interrupt(1);
-        }
-        #[interrupt]
-        fn SYSTIMER_TARGET2() {
-            DRIVER.on_interrupt(2);
-        }
-    }
-
-    pub(crate) fn set_alarm(
-        &self,
-        alarm: embassy_time::driver::AlarmHandle,
-        timestamp: u64,
-    ) -> bool {
-        critical_section::with(|_cs| {
-            let n = alarm.id() as usize;
-
-            // The hardware fires the alarm even if timestamp is lower than the current
-            // time. In this case the interrupt handler will pend a wakeup when we exit the
-            // critical section.
-            self.arm(n, timestamp);
-        });
-
-        // In theory, the above comment is true. However, in practice, we seem to be
-        // missing interrupt for very short timeouts, so let's make sure and catch
-        // timestamps that already passed. Returning `false` means embassy will
-        // run one more poll loop.
-        Self::now() < timestamp
-    }
-
-    fn clear_interrupt(&self, id: usize) {
-        match id {
-            0 => self.alarm0.clear_interrupt(),
-            1 => self.alarm1.clear_interrupt(),
-            2 => self.alarm2.clear_interrupt(),
-            _ => {}
-        }
-    }
-
-    fn arm(&self, id: usize, timestamp: u64) {
-        match id {
-            0 => self.alarm0.set_target(timestamp),
-            1 => self.alarm1.set_target(timestamp),
-            2 => self.alarm2.set_target(timestamp),
-            _ => {}
-        }
-    }
-}

esp-hal-common/src/embassy/time_driver_timg.rs

@@ -1,117 +0,0 @@
-use critical_section::{CriticalSection, Mutex};
-use peripherals::TIMG0;
-
-use super::AlarmState;
-#[cfg(any(esp32, esp32s2, esp32s3))]
-use crate::timer::Timer1;
-use crate::{
-    clock::Clocks,
-    peripherals,
-    prelude::*,
-    timer::{Instance, Timer, Timer0},
-};
-
-#[cfg(not(any(esp32, esp32s2, esp32s3)))]
-pub const ALARM_COUNT: usize = 1;
-#[cfg(any(esp32, esp32s2, esp32s3))]
-pub const ALARM_COUNT: usize = 2;
-
-pub type TimerType = Timer<Timer0<TIMG0>>;
-
-pub struct EmbassyTimer {
-    pub(crate) alarms: Mutex<[AlarmState; ALARM_COUNT]>,
-}
-
-const ALARM_STATE_NONE: AlarmState = AlarmState::new();
-
-embassy_time::time_driver_impl!(static DRIVER: EmbassyTimer = EmbassyTimer {
-    alarms: Mutex::new([ALARM_STATE_NONE; ALARM_COUNT]),
-});
-
-impl EmbassyTimer {
-    pub(crate) fn now() -> u64 {
-        unsafe { Timer0::<TIMG0>::steal() }.now()
-    }
-
-    fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
-        let alarm = &self.alarms.borrow(cs)[n];
-
-        if let Some((f, ctx)) = alarm.callback.get() {
-            f(ctx);
-        }
-    }
-
-    pub(super) fn on_alarm_allocated(&self, _n: usize) {}
-
-    fn on_interrupt<Timer: Instance>(&self, id: u8, mut timer: Timer) {
-        critical_section::with(|cs| {
-            timer.clear_interrupt();
-            self.trigger_alarm(id as usize, cs);
-        });
-    }
-
-    pub fn init(clocks: &Clocks, mut timer: TimerType) {
-        use crate::{interrupt, interrupt::Priority};
-
-        // set divider to get a 1mhz clock. APB (80mhz) / 80 = 1mhz...
-        // TODO: assert APB clock is the source and its at the correct speed for the
-        // divider
-        timer.set_divider(clocks.apb_clock.to_MHz() as u16);
-
-        timer.set_counter_active(true);
-
-        unwrap!(interrupt::enable(
-            peripherals::Interrupt::TG0_T0_LEVEL,
-            Priority::max()
-        ));
-        #[cfg(any(esp32, esp32s2, esp32s3))]
-        unwrap!(interrupt::enable(
-            peripherals::Interrupt::TG0_T1_LEVEL,
-            Priority::max()
-        ));
-
-        #[interrupt]
-        fn TG0_T0_LEVEL() {
-            let timer = unsafe { Timer0::<TIMG0>::steal() };
-            DRIVER.on_interrupt(0, timer);
-        }
-
-        #[cfg(any(esp32, esp32s2, esp32s3))]
-        #[interrupt]
-        fn TG0_T1_LEVEL() {
-            let timer = unsafe { Timer1::<TIMG0>::steal() };
-            DRIVER.on_interrupt(1, timer);
-        }
-    }
-
-    pub(crate) fn set_alarm(
-        &self,
-        _alarm: embassy_time::driver::AlarmHandle,
-        timestamp: u64,
-    ) -> bool {
-        critical_section::with(|_cs| {
-            // The hardware fires the alarm even if timestamp is lower than the current
-            // time. In this case the interrupt handler will pend a wakeup when we exit the
-            // critical section.
-            #[cfg(any(esp32, esp32s2, esp32s3))]
-            if _alarm.id() == 1 {
-                let mut tg = unsafe { Timer1::<TIMG0>::steal() };
-                Self::arm(&mut tg, timestamp);
-                return;
-            }
-
-            let mut tg = unsafe { Timer0::<TIMG0>::steal() };
-            Self::arm(&mut tg, timestamp);
-        });
-
-        true
-    }
-
-    fn arm<Timer: Instance>(tg: &mut Timer, timestamp: u64) {
-        tg.load_alarm_value(timestamp);
-        tg.listen();
-        tg.set_counter_decrementing(false);
-        tg.set_auto_reload(false);
-        tg.set_alarm_active(true);
-    }
-}

esp-hal-common/src/etm.rs

@@ -1,282 +0,0 @@
-//! # Event Task Matrix (ETM)
-//!
-//! ## Overview
-//!
-//! Normally, if a peripheral X needs to notify peripheral Y of a particular
-//! event, this could only be done via a CPU interrupt from peripheral X, where
-//! the CPU notifies peripheral Y on behalf of peripheral X. However, in
-//! time-critical applications, the latency introduced by CPU interrupts is
-//! non-negligible.
-//!
-//! With the help of the Event Task Matrix (ETM) module, some peripherals can
-//! directly notify other peripherals of events through pre-set connections
-//! without the intervention of CPU interrupts. This allows precise and low
-//! latency synchronization between peripherals, and lessens the CPU’s workload
-//! as the CPU no longer needs to handle these events.
-//!
-//! The ETM module has multiple programmable channels, they are used to connect
-//! a particular Event to a particular Task. When an event is activated, the ETM
-//! channel will trigger the corresponding task automatically.
-//!
-//! More information: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c6/api-reference/peripherals/etm.html
-//!
-//! ## Example
-//! ```no_run
-//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
-//! let mut led = io.pins.gpio1.into_push_pull_output();
-//! let button = io.pins.gpio9.into_pull_down_input();
-//!
-//! // setup ETM
-//! let gpio_ext = GpioEtmChannels::new(peripherals.GPIO_SD);
-//! let led_task = gpio_ext.channel0_task.toggle(&mut led);
-//! let button_event = gpio_ext.channel0_event.falling_edge(button);
-//!
-//! let etm = Etm::new(peripherals.SOC_ETM);
-//! let channel0 = etm.channel0;
-//!
-//! // make sure the configured channel doesn't get dropped - dropping it will
-//! // disable the channel
-//! let _configured_channel = channel0.setup(&button_event, &led_task);
-//!
-//! // the LED is controlled by the button without involving the CPU
-//! loop {}
-//! ```
-
-use crate::{
-    peripheral::{Peripheral, PeripheralRef},
-    system::PeripheralClockControl,
-};
-
-/// Unconfigured EtmChannel.
-#[non_exhaustive]
-pub struct EtmChannel<const C: u8> {}
-
-macro_rules! impl_etm_channel {
-    ($channel: literal, $bank: literal) => {
-        paste::paste! {
-            impl EtmChannel<$channel> {
-                /// Setup the channel
-                ///
-                /// Enabled the channel and configures the assigned event and task.
-                pub fn setup<'a, E, T>(self, event: &'a E, task: &'a T) -> EtmConfiguredChannel<'a, E,T,$channel>
-                where
-                    E: EtmEvent,
-                    T: EtmTask,
-                {
-                    let etm = unsafe { crate::peripherals::SOC_ETM::steal() };
-
-                    etm.[< ch $channel _evt_id >]().modify(|_, w| w.[< ch $channel _evt_id >]().variant(event.id()));
-                    etm.[< ch $channel _task_id >]().modify(|_, w| w.[< ch $channel _task_id >]().variant(task.id()));
-                    etm.[< ch_ena_ad $bank _set >]().write(|w| w.[< ch_set $channel >]().set_bit());
-
-                    EtmConfiguredChannel {
-                        _event: event,
-                        _task: task,
-                    }
-                }
-            }
-        }
-    };
-}
-
-impl_etm_channel!(0, 0);
-impl_etm_channel!(1, 0);
-impl_etm_channel!(2, 0);
-impl_etm_channel!(3, 0);
-impl_etm_channel!(4, 0);
-impl_etm_channel!(5, 0);
-impl_etm_channel!(6, 0);
-impl_etm_channel!(7, 0);
-impl_etm_channel!(8, 0);
-impl_etm_channel!(9, 0);
-impl_etm_channel!(10, 0);
-impl_etm_channel!(11, 0);
-impl_etm_channel!(12, 0);
-impl_etm_channel!(13, 0);
-impl_etm_channel!(14, 0);
-impl_etm_channel!(15, 0);
-impl_etm_channel!(16, 0);
-impl_etm_channel!(17, 0);
-impl_etm_channel!(18, 0);
-impl_etm_channel!(19, 0);
-impl_etm_channel!(20, 0);
-impl_etm_channel!(21, 0);
-impl_etm_channel!(22, 0);
-impl_etm_channel!(23, 0);
-impl_etm_channel!(24, 0);
-impl_etm_channel!(25, 0);
-impl_etm_channel!(26, 0);
-impl_etm_channel!(27, 0);
-impl_etm_channel!(28, 0);
-impl_etm_channel!(29, 0);
-impl_etm_channel!(30, 0);
-impl_etm_channel!(31, 0);
-impl_etm_channel!(32, 1);
-impl_etm_channel!(33, 1);
-impl_etm_channel!(34, 1);
-impl_etm_channel!(35, 1);
-impl_etm_channel!(36, 1);
-impl_etm_channel!(37, 1);
-impl_etm_channel!(38, 1);
-impl_etm_channel!(39, 1);
-impl_etm_channel!(40, 1);
-impl_etm_channel!(41, 1);
-impl_etm_channel!(42, 1);
-impl_etm_channel!(43, 1);
-impl_etm_channel!(44, 1);
-impl_etm_channel!(45, 1);
-impl_etm_channel!(46, 1);
-impl_etm_channel!(47, 1);
-impl_etm_channel!(48, 1);
-impl_etm_channel!(49, 1);
-
-macro_rules! impl_disable_helper {
-    ($(($channel:literal, $bank:literal)),+) => {
-        paste::paste! {
-            fn disable_channel(channel: u8) {
-                let etm = unsafe { crate::peripherals::SOC_ETM::steal() };
-                match channel {
-                    $(
-                        $channel => {etm.[< ch_ena_ad $bank _clr>]().write(|w| w.[< ch_clr $channel >]().set_bit());},
-                    )+
-                    _ => panic!("Unknown channel {}", channel),
-                }
-
-            }
-        }
-    };
-}
-
-impl_disable_helper!(
-    (0, 0),
-    (1, 0),
-    (2, 0),
-    (3, 0),
-    (4, 0),
-    (5, 0),
-    (6, 0),
-    (7, 0),
-    (8, 0),
-    (9, 0),
-    (10, 0),
-    (11, 0),
-    (12, 0),
-    (13, 0),
-    (14, 0),
-    (15, 0),
-    (16, 0),
-    (17, 0),
-    (18, 0),
-    (19, 0),
-    (20, 0),
-    (21, 0),
-    (22, 0),
-    (23, 0),
-    (24, 0),
-    (25, 0),
-    (26, 0),
-    (27, 0),
-    (28, 0),
-    (29, 0),
-    (30, 0),
-    (31, 0),
-    (32, 1),
-    (33, 1),
-    (34, 1),
-    (35, 1),
-    (36, 1),
-    (37, 1),
-    (38, 1),
-    (39, 1),
-    (40, 1),
-    (41, 1),
-    (42, 1),
-    (43, 1),
-    (44, 1),
-    (45, 1),
-    (46, 1),
-    (47, 1),
-    (48, 1),
-    (49, 1)
-);
-
-/// A readily configured channel
-///
-/// The channel is enabled and event and task are configured.
-#[non_exhaustive]
-pub struct EtmConfiguredChannel<'a, E, T, const C: u8>
-where
-    E: EtmEvent,
-    T: EtmTask,
-{
-    _event: &'a E,
-    _task: &'a T,
-}
-
-impl<'a, E, T, const C: u8> Drop for EtmConfiguredChannel<'a, E, T, C>
-where
-    E: EtmEvent,
-    T: EtmTask,
-{
-    fn drop(&mut self) {
-        debug!("drop {}", C);
-        disable_channel(C);
-    }
-}
-
-macro_rules! create_etm_struct {
-    ($($num:literal),+) => {
-        paste::paste! {
-            /// ETM Instance
-            ///
-            /// Provides access to all the [EtmChannel]
-            pub struct Etm<'d> {
-                _peripheral: PeripheralRef<'d, crate::peripherals::SOC_ETM>,
-                $(pub [< channel $num >]: EtmChannel<$num>,)+
-            }
-        }
-    };
-}
-
-macro_rules! create_etm_constructor {
-    ($($num:literal),+) => {
-        paste::paste! {
-            impl<'d> Etm<'d> {
-                pub fn new(peripheral: impl Peripheral<P = crate::peripherals::SOC_ETM> + 'd) -> Self {
-                    crate::into_ref!(peripheral);
-
-                    PeripheralClockControl::enable(crate::system::Peripheral::Etm);
-
-                    Self {
-                        _peripheral: peripheral,
-                        $([< channel $num >]: EtmChannel {},)+
-                    }
-                }
-            }
-        }
-    };
-}
-
-create_etm_struct!(
-    0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
-    26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49
-);
-
-create_etm_constructor!(
-    0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
-    26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49
-);
-
-#[doc(hidden)]
-pub trait EtmEvent: private::Sealed {
-    fn id(&self) -> u8;
-}
-
-#[doc(hidden)]
-pub trait EtmTask: private::Sealed {
-    fn id(&self) -> u8;
-}
-
-pub(crate) mod private {
-    pub trait Sealed {}
-}

esp-hal-common/src/interrupt/mod.rs

@@ -1,63 +0,0 @@
-//! # Interrupt support
-//!
-//! ## Overview
-//! The `interrupt` driver is a crucial module for ESP chips. Its primary
-//! purpose is to manage and handle interrupts, which are asynchronous events
-//! requiring immediate attention from the CPU. Interrupts are essential in
-//! various applications, such as real-time tasks, I/O communications, and
-//! handling external events like hardware signals.
-//!
-//! The core functionality of the `interrupt` driver revolves around the
-//! management of interrupts. When an interrupt occurs, it temporarily stops the
-//! ongoing CPU operations, saves its current state, and starts executing the
-//! corresponding interrupt service routine (ISR). The interrupt service routine
-//! is a user-defined function that performs the necessary actions to handle the
-//! specific interrupt. Once the ISR is executed, the driver restores the saved
-//! CPU state and resumes normal program execution.
-//!
-//! In scenarios where multiple interrupts may occur simultaneously, the
-//! interrupt driver determines the `priority` of each interrupt. This
-//! prioritization ensures that critical or high-priority tasks are handled
-//! first. It helps prevent delays in time-sensitive applications and allows the
-//! system to allocate resources efficiently. This functionality is provided and
-//! implemented by the `priority` enum.
-//!
-//!
-//! ## Example
-//! ```no_run
-//! #[entry]
-//! fn main() -> ! {
-//!     ...
-//!     critical_section::with(|cs| SWINT.borrow_ref_mut(cs).replace(sw_int));
-//!
-//!     interrupt::enable(
-//!         peripherals::Interrupt::FROM_CPU_INTR0,
-//!         interrupt::Priority::Priority1,
-//!     )
-//!     .unwrap();
-//!
-//!     loop {}
-//! }
-//!
-//! #[interrupt]
-//! fn FROM_CPU_INTR0() {
-//!     esp_println::println!("SW interrupt0");
-//!     critical_section::with(|cs| {
-//!         SWINT
-//!             .borrow_ref_mut(cs)
-//!             .as_mut()
-//!             .unwrap()
-//!             .reset(SoftwareInterrupt::SoftwareInterrupt0);
-//!     });
-//! }
-//! ```
-
-#[cfg(riscv)]
-pub use riscv::*;
-#[cfg(xtensa)]
-pub use xtensa::*;
-
-#[cfg(riscv)]
-mod riscv;
-#[cfg(xtensa)]
-mod xtensa;

esp-hal-common/src/interrupt/riscv.rs

@@ -1,801 +0,0 @@
-//! Interrupt handling - RISC-V
-//!
-//! When the `vectored` feature is enabled, CPU interrupts 1 through 15 are
-//! reserved for each of the possible interrupt priorities.
-//!
-//! On chips with a PLIC CPU interrupts 1,2,5,6,9 .. 19 are used.
-//!
-//! ```rust
-//! interrupt1() => Priority::Priority1
-//! interrupt2() => Priority::Priority2
-//! ...
-//! interrupt15() => Priority::Priority15
-//! ```
-
-use esp_riscv_rt::riscv::register::{mcause, mtvec};
-pub use esp_riscv_rt::TrapFrame;
-
-#[cfg(not(plic))]
-pub use self::classic::*;
-#[cfg(plic)]
-pub use self::plic::*;
-use crate::{
-    peripherals::{self, Interrupt},
-    Cpu,
-};
-
-/// Interrupt kind
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InterruptKind {
-    /// Level interrupt
-    Level,
-    /// Edge interrupt
-    Edge,
-}
-
-/// Enumeration of available CPU interrupts.
-/// It is possible to create a handler for each of the interrupts. (e.g.
-/// `interrupt3`)
-#[repr(u32)]
-#[derive(Debug, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum CpuInterrupt {
-    Interrupt1 = 1,
-    Interrupt2,
-    Interrupt3,
-    Interrupt4,
-    Interrupt5,
-    Interrupt6,
-    Interrupt7,
-    Interrupt8,
-    Interrupt9,
-    Interrupt10,
-    Interrupt11,
-    Interrupt12,
-    Interrupt13,
-    Interrupt14,
-    Interrupt15,
-    Interrupt16,
-    Interrupt17,
-    Interrupt18,
-    Interrupt19,
-    Interrupt20,
-    Interrupt21,
-    Interrupt22,
-    Interrupt23,
-    Interrupt24,
-    Interrupt25,
-    Interrupt26,
-    Interrupt27,
-    Interrupt28,
-    Interrupt29,
-    Interrupt30,
-    Interrupt31,
-}
-
-/// Interrupt priority levels.
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[repr(u8)]
-pub enum Priority {
-    None = 0,
-    Priority1,
-    Priority2,
-    Priority3,
-    Priority4,
-    Priority5,
-    Priority6,
-    Priority7,
-    Priority8,
-    Priority9,
-    Priority10,
-    Priority11,
-    Priority12,
-    Priority13,
-    Priority14,
-    Priority15,
-}
-
-impl Priority {
-    pub fn max() -> Priority {
-        Priority::Priority15
-    }
-
-    pub fn min() -> Priority {
-        Priority::Priority1
-    }
-}
-
-#[cfg(feature = "vectored")]
-pub use vectored::*;
-
-#[cfg(feature = "vectored")]
-mod vectored {
-    use procmacros::ram;
-
-    use super::*;
-
-    // Setup interrupts ready for vectoring
-    #[doc(hidden)]
-    pub(crate) unsafe fn init_vectoring() {
-        for (prio, num) in PRIORITY_TO_INTERRUPT.iter().enumerate() {
-            set_kind(
-                crate::get_core(),
-                core::mem::transmute(*num as u32),
-                InterruptKind::Level,
-            );
-            set_priority(
-                crate::get_core(),
-                core::mem::transmute(*num as u32),
-                core::mem::transmute((prio as u8) + 1),
-            );
-            enable_cpu_interrupt(core::mem::transmute(*num as u32));
-        }
-    }
-
-    /// Get the interrupts configured for the core
-    #[inline]
-    fn get_configured_interrupts(_core: Cpu, mut status: u128) -> [u128; 16] {
-        unsafe {
-            let mut prios = [0u128; 16];
-
-            while status != 0 {
-                let interrupt_nr = status.trailing_zeros() as u16;
-                // safety: cast is safe because of repr(u16)
-                let cpu_interrupt: CpuInterrupt =
-                    get_assigned_cpu_interrupt(core::mem::transmute(interrupt_nr as u16));
-                let prio = get_priority(cpu_interrupt);
-
-                prios[prio as usize] |= 1 << (interrupt_nr as usize);
-                status &= !(1u128 << interrupt_nr);
-            }
-
-            prios
-        }
-    }
-
-    /// Interrupt Error
-    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
-    #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-    pub enum Error {
-        InvalidInterruptPriority,
-    }
-
-    /// Enables a interrupt at a given priority
-    ///
-    /// Note that interrupts still need to be enabled globally for interrupts
-    /// to be serviced.
-    #[cfg(not(feature = "direct-vectoring"))]
-    pub fn enable(interrupt: Interrupt, level: Priority) -> Result<(), Error> {
-        if matches!(level, Priority::None) {
-            return Err(Error::InvalidInterruptPriority);
-        }
-        unsafe {
-            let cpu_interrupt =
-                core::mem::transmute(PRIORITY_TO_INTERRUPT[(level as usize) - 1] as u32);
-            map(crate::get_core(), interrupt, cpu_interrupt);
-            enable_cpu_interrupt(cpu_interrupt);
-        }
-        Ok(())
-    }
-
-    /// Enables an interrupt at a given priority, maps it to the given CPU
-    /// interrupt and assigns the given priority.
-    ///
-    /// This can be side-effectful since no guarantees can be made about the
-    /// CPU interrupt not already being in use.
-    ///
-    /// Note that interrupts still need to be enabled globally for interrupts
-    /// to be serviced.
-    #[cfg(feature = "direct-vectoring")]
-    pub unsafe fn enable(
-        interrupt: Interrupt,
-        level: Priority,
-        cpu_interrupt: CpuInterrupt,
-    ) -> Result<(), Error> {
-        if matches!(level, Priority::None) {
-            return Err(Error::InvalidInterruptPriority);
-        }
-        unsafe {
-            map(crate::get_core(), interrupt, cpu_interrupt);
-            set_priority(crate::get_core(), cpu_interrupt, level);
-            enable_cpu_interrupt(cpu_interrupt);
-        }
-        Ok(())
-    }
-
-    #[ram]
-    unsafe fn handle_interrupts(cpu_intr: CpuInterrupt, context: &mut TrapFrame) {
-        let status = get_status(crate::get_core());
-
-        // this has no effect on level interrupts, but the interrupt may be an edge one
-        // so we clear it anyway
-        clear(crate::get_core(), cpu_intr);
-
-        let configured_interrupts = get_configured_interrupts(crate::get_core(), status);
-        let mut interrupt_mask =
-            status & configured_interrupts[INTERRUPT_TO_PRIORITY[cpu_intr as usize - 1]];
-        while interrupt_mask != 0 {
-            let interrupt_nr = interrupt_mask.trailing_zeros();
-            // Interrupt::try_from can fail if interrupt already de-asserted:
-            // silently ignore
-            if let Ok(interrupt) = peripherals::Interrupt::try_from(interrupt_nr as u8) {
-                handle_interrupt(interrupt, context)
-            }
-            interrupt_mask &= !(1u128 << interrupt_nr);
-        }
-    }
-
-    #[ram]
-    unsafe fn handle_interrupt(interrupt: Interrupt, save_frame: &mut TrapFrame) {
-        extern "C" {
-            // defined in each hal
-            fn EspDefaultHandler(interrupt: Interrupt);
-        }
-        let handler = peripherals::__EXTERNAL_INTERRUPTS[interrupt as usize]._handler;
-        if handler as *const _ == EspDefaultHandler as *const unsafe extern "C" fn() {
-            EspDefaultHandler(interrupt);
-        } else {
-            let handler: fn(&mut TrapFrame) = core::mem::transmute(handler);
-            handler(save_frame);
-        }
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt1(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt1, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt2(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt2, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt3(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt3, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt4(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt4, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt5(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt5, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt6(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt6, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt7(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt7, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt8(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt8, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt9(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt9, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt10(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt10, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt11(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt11, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt12(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt12, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt13(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt13, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt14(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt14, context)
-    }
-
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt15(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt15, context)
-    }
-
-    #[cfg(plic)]
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt16(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt16, context)
-    }
-
-    #[cfg(plic)]
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt17(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt17, context)
-    }
-
-    #[cfg(plic)]
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt18(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt18, context)
-    }
-
-    #[cfg(plic)]
-    #[no_mangle]
-    #[ram]
-    pub unsafe fn interrupt19(context: &mut TrapFrame) {
-        handle_interrupts(CpuInterrupt::Interrupt19, context)
-    }
-}
-
-/// # Safety
-///
-/// This function is called from an assembly trap handler.
-#[doc(hidden)]
-#[link_section = ".trap.rust"]
-#[export_name = "_start_trap_rust_hal"]
-pub unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) {
-    // User code shouldn't usually take the mutable TrapFrame or the TrapFrame in
-    // general. However this makes things like preemtive multitasking easier in
-    // future
-    extern "C" {
-        fn interrupt1(frame: &mut TrapFrame);
-        fn interrupt2(frame: &mut TrapFrame);
-        fn interrupt3(frame: &mut TrapFrame);
-        fn interrupt4(frame: &mut TrapFrame);
-        fn interrupt5(frame: &mut TrapFrame);
-        fn interrupt6(frame: &mut TrapFrame);
-        fn interrupt7(frame: &mut TrapFrame);
-        fn interrupt8(frame: &mut TrapFrame);
-        fn interrupt9(frame: &mut TrapFrame);
-        fn interrupt10(frame: &mut TrapFrame);
-        fn interrupt11(frame: &mut TrapFrame);
-        fn interrupt12(frame: &mut TrapFrame);
-        fn interrupt13(frame: &mut TrapFrame);
-        fn interrupt14(frame: &mut TrapFrame);
-        fn interrupt15(frame: &mut TrapFrame);
-        fn interrupt16(frame: &mut TrapFrame);
-        fn interrupt17(frame: &mut TrapFrame);
-        fn interrupt18(frame: &mut TrapFrame);
-        fn interrupt19(frame: &mut TrapFrame);
-        fn interrupt20(frame: &mut TrapFrame);
-        fn interrupt21(frame: &mut TrapFrame);
-        fn interrupt22(frame: &mut TrapFrame);
-        fn interrupt23(frame: &mut TrapFrame);
-        fn interrupt24(frame: &mut TrapFrame);
-        fn interrupt25(frame: &mut TrapFrame);
-        fn interrupt26(frame: &mut TrapFrame);
-        fn interrupt27(frame: &mut TrapFrame);
-        fn interrupt28(frame: &mut TrapFrame);
-        fn interrupt29(frame: &mut TrapFrame);
-        fn interrupt30(frame: &mut TrapFrame);
-        fn interrupt31(frame: &mut TrapFrame);
-
-        // Defined in `esp-riscv-rt`
-        pub fn DefaultHandler();
-    }
-
-    let cause = mcause::read();
-    if cause.is_exception() {
-        extern "C" {
-            fn ExceptionHandler(tf: *mut TrapFrame);
-        }
-        ExceptionHandler(trap_frame);
-    } else {
-        #[cfg(feature = "interrupt-preemption")]
-        let interrupt_priority = _handle_priority();
-
-        let code = mcause::read().code();
-        match code {
-            1 => interrupt1(trap_frame.as_mut().unwrap()),
-            2 => interrupt2(trap_frame.as_mut().unwrap()),
-            3 => interrupt3(trap_frame.as_mut().unwrap()),
-            4 => interrupt4(trap_frame.as_mut().unwrap()),
-            5 => interrupt5(trap_frame.as_mut().unwrap()),
-            6 => interrupt6(trap_frame.as_mut().unwrap()),
-            7 => interrupt7(trap_frame.as_mut().unwrap()),
-            8 => interrupt8(trap_frame.as_mut().unwrap()),
-            9 => interrupt9(trap_frame.as_mut().unwrap()),
-            10 => interrupt10(trap_frame.as_mut().unwrap()),
-            11 => interrupt11(trap_frame.as_mut().unwrap()),
-            12 => interrupt12(trap_frame.as_mut().unwrap()),
-            13 => interrupt13(trap_frame.as_mut().unwrap()),
-            14 => interrupt14(trap_frame.as_mut().unwrap()),
-            15 => interrupt15(trap_frame.as_mut().unwrap()),
-            16 => interrupt16(trap_frame.as_mut().unwrap()),
-            17 => interrupt17(trap_frame.as_mut().unwrap()),
-            18 => interrupt18(trap_frame.as_mut().unwrap()),
-            19 => interrupt19(trap_frame.as_mut().unwrap()),
-            20 => interrupt20(trap_frame.as_mut().unwrap()),
-            21 => interrupt21(trap_frame.as_mut().unwrap()),
-            22 => interrupt22(trap_frame.as_mut().unwrap()),
-            23 => interrupt23(trap_frame.as_mut().unwrap()),
-            24 => interrupt24(trap_frame.as_mut().unwrap()),
-            25 => interrupt25(trap_frame.as_mut().unwrap()),
-            26 => interrupt26(trap_frame.as_mut().unwrap()),
-            27 => interrupt27(trap_frame.as_mut().unwrap()),
-            28 => interrupt28(trap_frame.as_mut().unwrap()),
-            29 => interrupt29(trap_frame.as_mut().unwrap()),
-            30 => interrupt30(trap_frame.as_mut().unwrap()),
-            31 => interrupt31(trap_frame.as_mut().unwrap()),
-            _ => DefaultHandler(),
-        };
-
-        #[cfg(feature = "interrupt-preemption")]
-        _restore_priority(interrupt_priority);
-    }
-}
-
-#[doc(hidden)]
-#[no_mangle]
-pub fn _setup_interrupts() {
-    extern "C" {
-        static _vector_table: *const u32;
-    }
-
-    unsafe {
-        // disable all known interrupts
-        // at least after the 2nd stage bootloader there are some interrupts enabled
-        // (e.g. UART)
-        for peripheral_interrupt in 0..255 {
-            crate::soc::peripherals::Interrupt::try_from(peripheral_interrupt)
-                .map(|intr| {
-                    #[cfg(multi_core)]
-                    disable(Cpu::AppCpu, intr);
-                    disable(Cpu::ProCpu, intr);
-                })
-                .ok();
-        }
-
-        let vec_table = &_vector_table as *const _ as usize;
-        mtvec::write(vec_table, mtvec::TrapMode::Vectored);
-
-        #[cfg(feature = "vectored")]
-        crate::interrupt::init_vectoring();
-    };
-
-    #[cfg(plic)]
-    unsafe {
-        core::arch::asm!("csrw mie, {0}", in(reg) u32::MAX);
-    }
-}
-
-/// Disable the given peripheral interrupt.
-pub fn disable(_core: Cpu, interrupt: Interrupt) {
-    unsafe {
-        let interrupt_number = interrupt as isize;
-        let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
-
-        // set to 0 to disable the peripheral interrupt
-        intr_map_base.offset(interrupt_number).write_volatile(0);
-    }
-}
-
-/// Get status of peripheral interrupts
-#[inline]
-pub fn get_status(_core: Cpu) -> u128 {
-    #[cfg(large_intr_status)]
-    unsafe {
-        ((*crate::peripherals::INTERRUPT_CORE0::PTR)
-            .intr_status_reg_0()
-            .read()
-            .bits() as u128)
-            | ((*crate::peripherals::INTERRUPT_CORE0::PTR)
-                .intr_status_reg_1()
-                .read()
-                .bits() as u128)
-                << 32
-            | ((*crate::peripherals::INTERRUPT_CORE0::PTR)
-                .int_status_reg_2()
-                .read()
-                .bits() as u128)
-                << 64
-    }
-
-    #[cfg(not(large_intr_status))]
-    unsafe {
-        ((*crate::peripherals::INTERRUPT_CORE0::PTR)
-            .intr_status_reg_0()
-            .read()
-            .bits() as u128)
-            | ((*crate::peripherals::INTERRUPT_CORE0::PTR)
-                .intr_status_reg_1()
-                .read()
-                .bits() as u128)
-                << 32
-    }
-}
-
-/// Assign a peripheral interrupt to an CPU interrupt.
-///
-/// Great care must be taken when using the `vectored` feature (enabled by
-/// default). Avoid interrupts 1 - 15 when interrupt vectoring is enabled.
-pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) {
-    let interrupt_number = interrupt as isize;
-    let cpu_interrupt_number = which as isize;
-    let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
-    intr_map_base
-        .offset(interrupt_number)
-        .write_volatile(cpu_interrupt_number as u32);
-}
-
-/// Get cpu interrupt assigned to peripheral interrupt
-#[inline]
-unsafe fn get_assigned_cpu_interrupt(interrupt: Interrupt) -> CpuInterrupt {
-    let interrupt_number = interrupt as isize;
-    let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
-
-    let cpu_intr = intr_map_base.offset(interrupt_number).read_volatile();
-
-    core::mem::transmute(cpu_intr)
-}
-
-#[cfg(not(plic))]
-mod classic {
-    use super::{CpuInterrupt, InterruptKind, Priority};
-    use crate::Cpu;
-
-    pub(super) const PRIORITY_TO_INTERRUPT: [usize; 15] =
-        [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
-
-    pub(super) const INTERRUPT_TO_PRIORITY: [usize; 15] =
-        [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
-
-    /// Enable a CPU interrupt
-    pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
-        let cpu_interrupt_number = which as isize;
-        let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        intr.cpu_int_enable()
-            .modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits()));
-    }
-
-    /// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
-    ///
-    /// This is safe to call when the `vectored` feature is enabled. The
-    /// vectored interrupt handler will take care of clearing edge interrupt
-    /// bits.
-    pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
-        unsafe {
-            let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-            let cpu_interrupt_number = which as isize;
-
-            let interrupt_type = match kind {
-                InterruptKind::Level => 0,
-                InterruptKind::Edge => 1,
-            };
-            intr.cpu_int_type().modify(|r, w| {
-                w.bits(
-                    r.bits() & !(1 << cpu_interrupt_number)
-                        | (interrupt_type << cpu_interrupt_number),
-                )
-            });
-        }
-    }
-
-    /// Set the priority level of an CPU interrupt
-    ///
-    /// Great care must be taken when using the `vectored` feature (enabled by
-    /// default). Avoid changing the priority of interrupts 1 - 15 when
-    /// interrupt vectoring is enabled.
-    pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
-        let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        let cpu_interrupt_number = which as isize;
-        let intr_prio_base = intr.cpu_int_pri_0().as_ptr();
-
-        intr_prio_base
-            .offset(cpu_interrupt_number)
-            .write_volatile(priority as u32);
-    }
-
-    /// Clear a CPU interrupt
-    #[inline]
-    pub fn clear(_core: Cpu, which: CpuInterrupt) {
-        unsafe {
-            let cpu_interrupt_number = which as isize;
-            let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-            intr.cpu_int_clear()
-                .write(|w| w.bits(1 << cpu_interrupt_number));
-        }
-    }
-
-    /// Get interrupt priority
-    #[inline]
-    pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
-        let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        let intr_prio_base = intr.cpu_int_pri_0().as_ptr();
-
-        let prio = intr_prio_base
-            .offset(cpu_interrupt as isize)
-            .read_volatile();
-        core::mem::transmute(prio as u8)
-    }
-    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
-    #[no_mangle]
-    #[link_section = ".trap"]
-    pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
-        use super::mcause;
-        use crate::riscv;
-        let interrupt_id: usize = mcause::read().code(); // MSB is whether its exception or interrupt.
-        let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        let interrupt_priority = intr
-            .cpu_int_pri_0()
-            .as_ptr()
-            .offset(interrupt_id as isize)
-            .read_volatile();
-
-        let prev_interrupt_priority = intr.cpu_int_thresh().read().bits();
-        if interrupt_priority < 15 {
-            // leave interrupts disabled if interrupt is of max priority.
-            intr.cpu_int_thresh()
-                .write(|w| w.bits(interrupt_priority + 1)); // set the prio threshold to 1 more than current interrupt prio
-            unsafe {
-                riscv::interrupt::enable();
-            }
-        }
-        prev_interrupt_priority
-    }
-    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
-    #[no_mangle]
-    #[link_section = ".trap"]
-    pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
-        use crate::riscv;
-        unsafe {
-            riscv::interrupt::disable();
-        }
-        let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR;
-        intr.cpu_int_thresh().write(|w| w.bits(stored_prio));
-    }
-}
-
-#[cfg(plic)]
-mod plic {
-    use super::{CpuInterrupt, InterruptKind, Priority};
-    use crate::Cpu;
-
-    // don't use interrupts reserved for CLIC (0,3,4,7)
-    // for some reason also CPU interrupt 8 doesn't work by default since it's
-    // disabled after reset - so don't use that, too
-    pub(super) const PRIORITY_TO_INTERRUPT: [usize; 15] =
-        [1, 2, 5, 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19];
-
-    pub(super) const INTERRUPT_TO_PRIORITY: [usize; 19] = [
-        1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
-    ];
-
-    const DR_REG_PLIC_MX_BASE: u32 = 0x20001000;
-    const PLIC_MXINT_ENABLE_REG: u32 = DR_REG_PLIC_MX_BASE + 0x0;
-    const PLIC_MXINT_TYPE_REG: u32 = DR_REG_PLIC_MX_BASE + 0x4;
-    const PLIC_MXINT_CLEAR_REG: u32 = DR_REG_PLIC_MX_BASE + 0x8;
-    const PLIC_MXINT0_PRI_REG: u32 = DR_REG_PLIC_MX_BASE + 0x10;
-    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
-    const PLIC_MXINT_THRESH_REG: u32 = DR_REG_PLIC_MX_BASE + 0x90;
-    /// Enable a CPU interrupt
-    pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
-        let cpu_interrupt_number = which as isize;
-        let mxint_enable = PLIC_MXINT_ENABLE_REG as *mut u32;
-        unsafe {
-            mxint_enable.write_volatile(mxint_enable.read_volatile() | 1 << cpu_interrupt_number);
-        }
-    }
-
-    /// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
-    ///
-    /// This is safe to call when the `vectored` feature is enabled. The
-    /// vectored interrupt handler will take care of clearing edge interrupt
-    /// bits.
-    pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
-        unsafe {
-            let intr = PLIC_MXINT_TYPE_REG as *mut u32;
-            let cpu_interrupt_number = which as isize;
-
-            let interrupt_type = match kind {
-                InterruptKind::Level => 0,
-                InterruptKind::Edge => 1,
-            };
-            intr.write_volatile(
-                intr.read_volatile() & !(1 << cpu_interrupt_number)
-                    | (interrupt_type << cpu_interrupt_number),
-            );
-        }
-    }
-
-    /// Set the priority level of an CPU interrupt
-    ///
-    /// Great care must be taken when using the `vectored` feature (enabled by
-    /// default). Avoid changing the priority of interrupts 1 - 15 when
-    /// interrupt vectoring is enabled.
-    pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
-        let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
-
-        let cpu_interrupt_number = which as isize;
-        plic_mxint_pri_ptr
-            .offset(cpu_interrupt_number)
-            .write_volatile(priority as u32);
-    }
-
-    /// Clear a CPU interrupt
-    #[inline]
-    pub fn clear(_core: Cpu, which: CpuInterrupt) {
-        unsafe {
-            let cpu_interrupt_number = which as isize;
-            let intr = PLIC_MXINT_CLEAR_REG as *mut u32;
-            intr.write_volatile(1 << cpu_interrupt_number);
-        }
-    }
-
-    /// Get interrupt priority
-    #[inline]
-    pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority {
-        let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
-
-        let cpu_interrupt_number = cpu_interrupt as isize;
-        let prio = plic_mxint_pri_ptr
-            .offset(cpu_interrupt_number)
-            .read_volatile();
-        core::mem::transmute(prio as u8)
-    }
-    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
-    #[no_mangle]
-    #[link_section = ".trap"]
-    pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
-        use super::mcause;
-        use crate::riscv;
-        let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32;
-        let interrupt_id: isize = mcause::read().code().try_into().unwrap(); // MSB is whether its exception or interrupt.
-        let interrupt_priority = plic_mxint_pri_ptr.offset(interrupt_id).read_volatile();
-
-        let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32;
-        let prev_interrupt_priority = thresh_reg.read_volatile() & 0x000000FF;
-        // this is a u8 according to esp-idf, so mask everything else.
-        if interrupt_priority < 15 {
-            // leave interrupts disabled if interrupt is of max priority.
-            thresh_reg.write_volatile(interrupt_priority + 1);
-            unsafe {
-                riscv::interrupt::enable();
-            }
-        }
-        prev_interrupt_priority
-    }
-    #[cfg(any(feature = "interrupt-preemption", feature = "direct-vectoring"))]
-    #[no_mangle]
-    #[link_section = ".trap"]
-    pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
-        use crate::riscv;
-        unsafe {
-            riscv::interrupt::disable();
-        }
-        let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32;
-        thresh_reg.write_volatile(stored_prio);
-    }
-}

esp-hal-common/src/interrupt/xtensa.rs

@@ -1,570 +0,0 @@
-use xtensa_lx::interrupt::{self, InterruptNumber};
-use xtensa_lx_rt::exception::Context;
-
-use crate::{
-    peripherals::{self, Interrupt},
-    Cpu,
-};
-
-/// Enumeration of available CPU interrupts
-///
-/// It's possible to create one handler per priority level. (e.g
-/// `level1_interrupt`)
-#[allow(unused)]
-#[derive(Debug, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[repr(u32)]
-pub enum CpuInterrupt {
-    Interrupt0LevelPriority1 = 0,
-    Interrupt1LevelPriority1,
-    Interrupt2LevelPriority1,
-    Interrupt3LevelPriority1,
-    Interrupt4LevelPriority1,
-    Interrupt5LevelPriority1,
-    Interrupt6Timer0Priority1,
-    Interrupt7SoftwarePriority1,
-    Interrupt8LevelPriority1,
-    Interrupt9LevelPriority1,
-    Interrupt10EdgePriority1,
-    Interrupt11ProfilingPriority3,
-    Interrupt12LevelPriority1,
-    Interrupt13LevelPriority1,
-    Interrupt14NmiPriority7,
-    Interrupt15Timer1Priority3,
-    Interrupt16Timer2Priority5,
-    Interrupt17LevelPriority1,
-    Interrupt18LevelPriority1,
-    Interrupt19LevelPriority2,
-    Interrupt20LevelPriority2,
-    Interrupt21LevelPriority2,
-    Interrupt22EdgePriority3,
-    Interrupt23LevelPriority3,
-    Interrupt24LevelPriority4,
-    Interrupt25LevelPriority4,
-    Interrupt26LevelPriority5,
-    Interrupt27LevelPriority3,
-    Interrupt28EdgePriority4,
-    Interrupt29SoftwarePriority3,
-    Interrupt30EdgePriority4,
-    Interrupt31EdgePriority5,
-}
-
-/// Assign a peripheral interrupt to an CPU interrupt
-///
-/// Great care **must** be taken when using this function with interrupt
-/// vectoring (enabled by default). Avoid the following CPU interrupts:
-/// - Interrupt1LevelPriority1
-/// - Interrupt19LevelPriority2
-/// - Interrupt23LevelPriority3
-/// - Interrupt10EdgePriority1
-/// - Interrupt22EdgePriority3
-/// As they are preallocated for interrupt vectoring.
-///
-/// Note: this only maps the interrupt to the CPU interrupt. The CPU interrupt
-/// still needs to be enabled afterwards
-pub unsafe fn map(core: Cpu, interrupt: Interrupt, which: CpuInterrupt) {
-    let interrupt_number = interrupt as isize;
-    let cpu_interrupt_number = which as isize;
-    let intr_map_base = match core {
-        Cpu::ProCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map().as_ptr(),
-        #[cfg(multi_core)]
-        Cpu::AppCpu => (*core1_interrupt_peripheral()).app_mac_intr_map().as_ptr(),
-    };
-    intr_map_base
-        .offset(interrupt_number)
-        .write_volatile(cpu_interrupt_number as u32);
-}
-
-/// Disable the given peripheral interrupt
-pub fn disable(core: Cpu, interrupt: Interrupt) {
-    unsafe {
-        let interrupt_number = interrupt as isize;
-        let intr_map_base = match core {
-            Cpu::ProCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map().as_ptr(),
-            #[cfg(multi_core)]
-            Cpu::AppCpu => (*core1_interrupt_peripheral()).app_mac_intr_map().as_ptr(),
-        };
-        // To disable an interrupt, map it to a CPU peripheral interrupt
-        intr_map_base
-            .offset(interrupt_number)
-            .write_volatile(CpuInterrupt::Interrupt16Timer2Priority5 as _);
-    }
-}
-
-/// Clear the given CPU interrupt
-pub fn clear(_core: Cpu, which: CpuInterrupt) {
-    unsafe {
-        xtensa_lx::interrupt::clear(1 << which as u32);
-    }
-}
-
-/// Get status of peripheral interrupts
-pub fn get_status(core: Cpu) -> u128 {
-    unsafe {
-        #[allow(unused_mut)]
-        let mut status = match core {
-            Cpu::ProCpu => {
-                ((*core0_interrupt_peripheral())
-                    .pro_intr_status_0()
-                    .read()
-                    .bits() as u128)
-                    | ((*core0_interrupt_peripheral())
-                        .pro_intr_status_1()
-                        .read()
-                        .bits() as u128)
-                        << 32
-                    | ((*core0_interrupt_peripheral())
-                        .pro_intr_status_2()
-                        .read()
-                        .bits() as u128)
-                        << 64
-            }
-            #[cfg(multi_core)]
-            Cpu::AppCpu => {
-                ((*core1_interrupt_peripheral())
-                    .app_intr_status_0()
-                    .read()
-                    .bits() as u128)
-                    | ((*core1_interrupt_peripheral())
-                        .app_intr_status_1()
-                        .read()
-                        .bits() as u128)
-                        << 32
-                    | ((*core1_interrupt_peripheral())
-                        .app_intr_status_2()
-                        .read()
-                        .bits() as u128)
-                        << 64
-            }
-        };
-
-        #[cfg(feature = "esp32s3")]
-        match core {
-            Cpu::ProCpu => {
-                status |= ((*core0_interrupt_peripheral())
-                    .pro_intr_status_3()
-                    .read()
-                    .bits() as u128)
-                    << 96;
-            }
-            #[cfg(multi_core)]
-            Cpu::AppCpu => {
-                status |= ((*core1_interrupt_peripheral())
-                    .app_intr_status_3()
-                    .read()
-                    .bits() as u128)
-                    << 96;
-            }
-        }
-
-        status
-    }
-}
-
-#[cfg(esp32)]
-unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::dport::RegisterBlock {
-    crate::peripherals::DPORT::PTR
-}
-
-#[cfg(esp32)]
-unsafe fn core1_interrupt_peripheral() -> *const crate::peripherals::dport::RegisterBlock {
-    crate::peripherals::DPORT::PTR
-}
-
-#[cfg(any(esp32s2, esp32s3))]
-unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::interrupt_core0::RegisterBlock
-{
-    crate::peripherals::INTERRUPT_CORE0::PTR
-}
-
-#[cfg(esp32s3)]
-unsafe fn core1_interrupt_peripheral() -> *const crate::peripherals::interrupt_core1::RegisterBlock
-{
-    crate::peripherals::INTERRUPT_CORE1::PTR
-}
-
-#[cfg(feature = "vectored")]
-pub use vectored::*;
-
-#[cfg(feature = "vectored")]
-mod vectored {
-    use procmacros::ram;
-
-    use super::*;
-    use crate::get_core;
-
-    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
-    #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-    pub enum Error {
-        InvalidInterrupt,
-    }
-
-    /// Interrupt priority levels.
-    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
-    #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-    #[repr(u8)]
-    pub enum Priority {
-        None = 0,
-        Priority1,
-        Priority2,
-        Priority3,
-    }
-
-    impl Priority {
-        pub fn max() -> Priority {
-            Priority::Priority3
-        }
-
-        pub fn min() -> Priority {
-            Priority::Priority1
-        }
-    }
-
-    impl CpuInterrupt {
-        #[inline]
-        fn level(&self) -> Priority {
-            match self {
-                CpuInterrupt::Interrupt0LevelPriority1
-                | CpuInterrupt::Interrupt1LevelPriority1
-                | CpuInterrupt::Interrupt2LevelPriority1
-                | CpuInterrupt::Interrupt3LevelPriority1
-                | CpuInterrupt::Interrupt4LevelPriority1
-                | CpuInterrupt::Interrupt5LevelPriority1
-                | CpuInterrupt::Interrupt6Timer0Priority1
-                | CpuInterrupt::Interrupt7SoftwarePriority1
-                | CpuInterrupt::Interrupt8LevelPriority1
-                | CpuInterrupt::Interrupt9LevelPriority1
-                | CpuInterrupt::Interrupt10EdgePriority1
-                | CpuInterrupt::Interrupt12LevelPriority1
-                | CpuInterrupt::Interrupt13LevelPriority1
-                | CpuInterrupt::Interrupt17LevelPriority1
-                | CpuInterrupt::Interrupt18LevelPriority1 => Priority::Priority1,
-
-                CpuInterrupt::Interrupt19LevelPriority2
-                | CpuInterrupt::Interrupt20LevelPriority2
-                | CpuInterrupt::Interrupt21LevelPriority2 => Priority::Priority2,
-
-                CpuInterrupt::Interrupt11ProfilingPriority3
-                | CpuInterrupt::Interrupt15Timer1Priority3
-                | CpuInterrupt::Interrupt22EdgePriority3
-                | CpuInterrupt::Interrupt27LevelPriority3
-                | CpuInterrupt::Interrupt29SoftwarePriority3
-                | CpuInterrupt::Interrupt23LevelPriority3 => Priority::Priority3,
-
-                // we direct these to None because we do not support interrupts at this level
-                // through Rust
-                CpuInterrupt::Interrupt24LevelPriority4
-                | CpuInterrupt::Interrupt25LevelPriority4
-                | CpuInterrupt::Interrupt28EdgePriority4
-                | CpuInterrupt::Interrupt30EdgePriority4
-                | CpuInterrupt::Interrupt31EdgePriority5
-                | CpuInterrupt::Interrupt16Timer2Priority5
-                | CpuInterrupt::Interrupt26LevelPriority5
-                | CpuInterrupt::Interrupt14NmiPriority7 => Priority::None,
-            }
-        }
-    }
-
-    /// Get the interrupts configured for the core
-    #[inline]
-    fn get_configured_interrupts(core: Cpu, mut status: u128) -> [u128; 8] {
-        unsafe {
-            let intr_map_base = match core {
-                Cpu::ProCpu => (*core0_interrupt_peripheral()).pro_mac_intr_map().as_ptr(),
-                #[cfg(multi_core)]
-                Cpu::AppCpu => (*core1_interrupt_peripheral()).app_mac_intr_map().as_ptr(),
-            };
-
-            let mut levels = [0u128; 8];
-
-            while status != 0 {
-                let interrupt_nr = status.trailing_zeros();
-                let i = interrupt_nr as isize;
-                let cpu_interrupt = intr_map_base.offset(i).read_volatile();
-                // safety: cast is safe because of repr(u32)
-                let cpu_interrupt: CpuInterrupt = core::mem::transmute(cpu_interrupt);
-                let level = cpu_interrupt.level() as u8 as usize;
-
-                levels[level] |= 1 << i;
-                status &= !(1u128 << interrupt_nr);
-            }
-
-            levels
-        }
-    }
-
-    /// Enable the given peripheral interrupt
-    pub fn enable(interrupt: Interrupt, level: Priority) -> Result<(), Error> {
-        let cpu_interrupt =
-            interrupt_level_to_cpu_interrupt(level, chip_specific::interrupt_is_edge(interrupt))?;
-
-        unsafe {
-            map(get_core(), interrupt, cpu_interrupt);
-
-            xtensa_lx::interrupt::enable_mask(
-                xtensa_lx::interrupt::get_mask() | 1 << cpu_interrupt as u32,
-            );
-        }
-        Ok(())
-    }
-
-    fn interrupt_level_to_cpu_interrupt(
-        level: Priority,
-        is_edge: bool,
-    ) -> Result<CpuInterrupt, Error> {
-        Ok(if is_edge {
-            match level {
-                Priority::None => return Err(Error::InvalidInterrupt),
-                Priority::Priority1 => CpuInterrupt::Interrupt10EdgePriority1,
-                Priority::Priority2 => return Err(Error::InvalidInterrupt),
-                Priority::Priority3 => CpuInterrupt::Interrupt22EdgePriority3,
-            }
-        } else {
-            match level {
-                Priority::None => return Err(Error::InvalidInterrupt),
-                Priority::Priority1 => CpuInterrupt::Interrupt1LevelPriority1,
-                Priority::Priority2 => CpuInterrupt::Interrupt19LevelPriority2,
-                Priority::Priority3 => CpuInterrupt::Interrupt23LevelPriority3,
-            }
-        })
-    }
-
-    // TODO use CpuInterrupt::LevelX.mask() // TODO make it const
-    const CPU_INTERRUPT_LEVELS: [u32; 8] = [
-        0b_0000_0000_0000_0000_0000_0000_0000_0000, // Dummy level 0
-        0b_0000_0000_0000_0110_0011_0111_1111_1111, // Level_1
-        0b_0000_0000_0011_1000_0000_0000_0000_0000, // Level 2
-        0b_0010_1000_1100_0000_1000_1000_0000_0000, // Level 3
-        0b_0101_0011_0000_0000_0000_0000_0000_0000, // Level 4
-        0b_1000_0100_0000_0001_0000_0000_0000_0000, // Level 5
-        0b_0000_0000_0000_0000_0000_0000_0000_0000, // Level 6
-        0b_0000_0000_0000_0000_0100_0000_0000_0000, // Level 7
-    ];
-    const CPU_INTERRUPT_INTERNAL: u32 = 0b_0010_0000_0000_0001_1000_1000_1100_0000;
-    const CPU_INTERRUPT_EDGE: u32 = 0b_0111_0000_0100_0000_0000_1100_1000_0000;
-
-    #[inline]
-    fn cpu_interrupt_nr_to_cpu_interrupt_handler(
-        number: u32,
-    ) -> Option<unsafe extern "C" fn(u32, save_frame: &mut Context)> {
-        use xtensa_lx_rt::*;
-        // we're fortunate that all esp variants use the same CPU interrupt layout
-        Some(match number {
-            6 => Timer0,
-            7 => Software0,
-            11 => Profiling,
-            14 => NMI,
-            15 => Timer1,
-            16 => Timer2,
-            29 => Software1,
-            _ => return None,
-        })
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_1_interrupt(level: u32, save_frame: &mut Context) {
-        handle_interrupts(level, save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_2_interrupt(level: u32, save_frame: &mut Context) {
-        handle_interrupts(level, save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_3_interrupt(level: u32, save_frame: &mut Context) {
-        handle_interrupts(level, save_frame)
-    }
-
-    #[ram]
-    unsafe fn handle_interrupts(level: u32, save_frame: &mut Context) {
-        let cpu_interrupt_mask =
-            interrupt::get() & interrupt::get_mask() & CPU_INTERRUPT_LEVELS[level as usize];
-
-        if cpu_interrupt_mask & CPU_INTERRUPT_INTERNAL != 0 {
-            let cpu_interrupt_mask = cpu_interrupt_mask & CPU_INTERRUPT_INTERNAL;
-            let cpu_interrupt_nr = cpu_interrupt_mask.trailing_zeros();
-
-            if (cpu_interrupt_mask & CPU_INTERRUPT_EDGE) != 0 {
-                interrupt::clear(1 << cpu_interrupt_nr);
-            }
-            if let Some(handler) = cpu_interrupt_nr_to_cpu_interrupt_handler(cpu_interrupt_nr) {
-                handler(level, save_frame);
-            }
-        } else {
-            if (cpu_interrupt_mask & CPU_INTERRUPT_EDGE) != 0 {
-                let cpu_interrupt_mask = cpu_interrupt_mask & CPU_INTERRUPT_EDGE;
-                let cpu_interrupt_nr = cpu_interrupt_mask.trailing_zeros();
-                interrupt::clear(1 << cpu_interrupt_nr);
-
-                // for edge interrupts cannot rely on the interrupt status
-                // register, therefore call all registered
-                // handlers for current level
-                let interrupt_levels =
-                    get_configured_interrupts(crate::get_core(), chip_specific::INTERRUPT_EDGE);
-                let interrupt_mask = interrupt_levels[level as usize];
-                let mut interrupt_mask = interrupt_mask & chip_specific::INTERRUPT_EDGE;
-                loop {
-                    let interrupt_nr = interrupt_mask.trailing_zeros();
-                    if let Ok(interrupt) = peripherals::Interrupt::try_from(interrupt_nr as u16) {
-                        handle_interrupt(level, interrupt, save_frame)
-                    } else {
-                        break;
-                    }
-                    interrupt_mask &= !(1u128 << interrupt_nr);
-                }
-            } else {
-                // finally check periperal sources and fire of handlers from pac
-                // peripheral mapped interrupts are cleared by the peripheral
-                let status = get_status(crate::get_core());
-                let interrupt_levels = get_configured_interrupts(crate::get_core(), status);
-                let interrupt_mask = status & interrupt_levels[level as usize];
-                let interrupt_nr = interrupt_mask.trailing_zeros();
-
-                // Interrupt::try_from can fail if interrupt already de-asserted:
-                // silently ignore
-                if let Ok(interrupt) = peripherals::Interrupt::try_from(interrupt_nr as u16) {
-                    handle_interrupt(level, interrupt, save_frame);
-                }
-            }
-        }
-    }
-
-    #[ram]
-    unsafe fn handle_interrupt(level: u32, interrupt: Interrupt, save_frame: &mut Context) {
-        extern "C" {
-            // defined in each hal
-            fn EspDefaultHandler(level: u32, interrupt: Interrupt);
-        }
-
-        let handler = peripherals::__INTERRUPTS[interrupt.number() as usize]._handler;
-        if handler as *const _ == EspDefaultHandler as *const unsafe extern "C" fn() {
-            EspDefaultHandler(level, interrupt);
-        } else {
-            let handler: fn(&mut Context) = core::mem::transmute(handler);
-            handler(save_frame);
-        }
-    }
-
-    #[cfg(esp32)]
-    mod chip_specific {
-        use super::*;
-        pub const INTERRUPT_EDGE: u128 =
-    0b_0000_0000_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0000_0000_0011_1111_1100_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0000_0000_0000;
-        #[inline]
-        pub fn interrupt_is_edge(interrupt: Interrupt) -> bool {
-            use peripherals::Interrupt::*;
-            [
-                TG0_T0_EDGE,
-                TG0_T1_EDGE,
-                TG0_WDT_EDGE,
-                TG0_LACT_EDGE,
-                TG1_T0_EDGE,
-                TG1_T1_EDGE,
-                TG1_WDT_EDGE,
-                TG1_LACT_EDGE,
-            ]
-            .contains(&interrupt)
-        }
-    }
-
-    #[cfg(esp32s2)]
-    mod chip_specific {
-        use super::*;
-        pub const INTERRUPT_EDGE: u128 =
-    0b_0000_0000_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0011_1011_1111_1100_0000_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0000_0000_0000;
-        #[inline]
-        pub fn interrupt_is_edge(interrupt: Interrupt) -> bool {
-            use peripherals::Interrupt::*;
-            [
-                TG0_T0_EDGE,
-                TG0_T1_EDGE,
-                TG0_WDT_EDGE,
-                TG0_LACT_EDGE,
-                TG1_T0_EDGE,
-                TG1_T1_EDGE,
-                TG1_WDT_EDGE,
-                TG1_LACT_EDGE,
-                SYSTIMER_TARGET0,
-                SYSTIMER_TARGET1,
-                SYSTIMER_TARGET2,
-            ]
-            .contains(&interrupt)
-        }
-    }
-
-    #[cfg(esp32s3)]
-    mod chip_specific {
-        use super::*;
-        pub const INTERRUPT_EDGE: u128 = 0;
-        #[inline]
-        pub fn interrupt_is_edge(_interrupt: Interrupt) -> bool {
-            false
-        }
-    }
-}
-
-mod raw {
-    use super::*;
-
-    extern "C" {
-        #[cfg(not(feature = "vectored"))]
-        fn level1_interrupt(save_frame: &mut Context);
-        #[cfg(not(feature = "vectored"))]
-        fn level2_interrupt(save_frame: &mut Context);
-        #[cfg(not(feature = "vectored"))]
-        fn level3_interrupt(save_frame: &mut Context);
-        fn level4_interrupt(save_frame: &mut Context);
-        fn level5_interrupt(save_frame: &mut Context);
-        fn level6_interrupt(save_frame: &mut Context);
-        fn level7_interrupt(save_frame: &mut Context);
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    #[cfg(not(feature = "vectored"))]
-    unsafe fn __level_1_interrupt(_level: u32, save_frame: &mut Context) {
-        level1_interrupt(save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    #[cfg(not(feature = "vectored"))]
-    unsafe fn __level_2_interrupt(_level: u32, save_frame: &mut Context) {
-        level2_interrupt(save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    #[cfg(not(feature = "vectored"))]
-    unsafe fn __level_3_interrupt(_level: u32, save_frame: &mut Context) {
-        level3_interrupt(save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_4_interrupt(_level: u32, save_frame: &mut Context) {
-        level4_interrupt(save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_5_interrupt(_level: u32, save_frame: &mut Context) {
-        level5_interrupt(save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_6_interrupt(_level: u32, save_frame: &mut Context) {
-        level6_interrupt(save_frame)
-    }
-
-    #[no_mangle]
-    #[link_section = ".rwtext"]
-    unsafe fn __level_7_interrupt(_level: u32, save_frame: &mut Context) {
-        level7_interrupt(save_frame)
-    }
-}

esp-hal-common/src/ledc/mod.rs

@@ -1,171 +0,0 @@
-//! # LEDC (LED PWM Controller) peripheral control
-//!
-//! Currently only supports fixed-frequency output. Interrupts are not currently
-//! implemented. High Speed channels are available for the ESP32 only, while Low
-//! Speed channels are available for all supported chips.
-//!
-//! # LowSpeed Example:
-//!
-//! The following will configure the Low Speed Channel0 to 24kHz output with
-//! 10% duty using the ABPClock
-//!
-//! ```no_run
-//! let mut ledc = LEDC::new(peripherals.LEDC, &clock_control);
-//! ledc.set_global_slow_clock(LSGlobalClkSource::APBClk);
-//!
-//! let mut lstimer0 = ledc.get_timer::<LowSpeed>(timer::Number::Timer0);
-//! lstimer0
-//!     .configure(timer::config::Config {
-//!         duty: timer::config::Duty::Duty5Bit,
-//!         clock_source: timer::LSClockSource::APBClk,
-//!         frequency: 24u32.kHz(),
-//!     })
-//!     .unwrap();
-//!
-//! let mut channel0 = ledc.get_channel(channel::Number::Channel0, led);
-//! channel0
-//!     .configure(channel::config::Config {
-//!         timer: &lstimer0,
-//!         duty: 10,
-//!     })
-//!     .unwrap();
-//! ```
-//!
-//! # HighSpeed Example (ESP32 only):
-//!
-//! The following will configure the High Speed Channel0 to 24kHz output with
-//! 10% duty using the ABPClock
-//!
-//! ```no_run
-//! let ledc = LEDC::new(peripherals.LEDC, &clock_control);
-//!
-//! let mut hstimer0 = ledc.get_timer::<HighSpeed>(timer::Number::Timer0);
-//! hstimer0
-//!     .configure(timer::config::Config {
-//!         duty: timer::config::Duty::Duty5Bit,
-//!         clock_source: timer::HSClockSource::APBClk,
-//!         frequency: 24u32.kHz(),
-//!     })
-//!     .unwrap();
-//!
-//! let mut channel0 = ledc.get_channel(channel::Number::Channel0, led);
-//! channel0
-//!     .configure(channel::config::Config {
-//!         timer: &hstimer0,
-//!         duty: 10,
-//!     })
-//!     .unwrap();
-//! ```
-//!
-//! # TODO
-//!
-//! - Source clock selection
-//! - Interrupts
-
-use self::{
-    channel::Channel,
-    timer::{Timer, TimerSpeed},
-};
-use crate::{
-    clock::Clocks,
-    gpio::OutputPin,
-    peripheral::{Peripheral, PeripheralRef},
-    system::{Peripheral as PeripheralEnable, PeripheralClockControl},
-};
-
-pub mod channel;
-pub mod timer;
-
-/// Global slow clock source
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-pub enum LSGlobalClkSource {
-    APBClk,
-}
-
-/// LEDC (LED PWM Controller)
-pub struct LEDC<'d> {
-    _instance: PeripheralRef<'d, crate::peripherals::LEDC>,
-    ledc: &'d crate::peripherals::ledc::RegisterBlock,
-    clock_control_config: &'d Clocks<'d>,
-}
-
-#[cfg(esp32)]
-/// Used to specify HighSpeed Timer/Channel
-pub struct HighSpeed {}
-
-/// Used to specify LowSpeed Timer/Channel
-pub struct LowSpeed {}
-
-pub trait Speed {}
-
-#[cfg(esp32)]
-impl Speed for HighSpeed {}
-
-impl Speed for LowSpeed {}
-
-impl<'d> LEDC<'d> {
-    /// Return a new LEDC
-    pub fn new(
-        _instance: impl Peripheral<P = crate::peripherals::LEDC> + 'd,
-        clock_control_config: &'d Clocks,
-    ) -> Self {
-        crate::into_ref!(_instance);
-        PeripheralClockControl::enable(PeripheralEnable::Ledc);
-
-        let ledc = unsafe { &*crate::peripherals::LEDC::ptr() };
-        LEDC {
-            _instance,
-            ledc,
-            clock_control_config,
-        }
-    }
-
-    /// Set global slow clock source
-    #[cfg(esp32)]
-    pub fn set_global_slow_clock(&mut self, _clock_source: LSGlobalClkSource) {
-        self.ledc.conf().write(|w| w.apb_clk_sel().set_bit());
-        self.ledc
-            .lstimer0_conf()
-            .modify(|_, w| w.para_up().set_bit());
-    }
-
-    #[cfg(not(esp32))]
-    /// Set global slow clock source
-    pub fn set_global_slow_clock(&mut self, clock_source: LSGlobalClkSource) {
-        #[cfg(any(esp32c6, esp32h2))]
-        let pcr = unsafe { &*crate::peripherals::PCR::ptr() };
-
-        #[cfg(any(esp32c6, esp32h2))]
-        pcr.ledc_sclk_conf().write(|w| w.ledc_sclk_en().set_bit());
-
-        match clock_source {
-            LSGlobalClkSource::APBClk => {
-                #[cfg(not(any(esp32c6, esp32h2)))]
-                self.ledc
-                    .conf()
-                    .write(|w| unsafe { w.apb_clk_sel().bits(1) });
-                #[cfg(esp32c6)]
-                pcr.ledc_sclk_conf()
-                    .write(|w| unsafe { w.ledc_sclk_sel().bits(1) });
-                #[cfg(esp32h2)]
-                pcr.ledc_sclk_conf()
-                    .write(|w| unsafe { w.ledc_sclk_sel().bits(0) });
-            }
-        }
-        self.ledc.timer0_conf().modify(|_, w| w.para_up().set_bit());
-    }
-
-    /// Return a new timer
-    pub fn get_timer<S: TimerSpeed>(&self, number: timer::Number) -> Timer<S> {
-        Timer::new(self.ledc, self.clock_control_config, number)
-    }
-
-    /// Return a new channel
-    pub fn get_channel<S: TimerSpeed, O: OutputPin>(
-        &self,
-        number: channel::Number,
-        output_pin: impl Peripheral<P = O> + 'd,
-    ) -> Channel<S, O> {
-        Channel::new(number, output_pin)
-    }
-}

esp-hal-common/src/ledc/timer.rs

@@ -1,476 +0,0 @@
-//! # LEDC timer
-//!
-//! ## Overview
-//! The `LEDC Timer` module is a part of the `LED Controller (LEDC)` driver
-//! designed for ESP microcontrollers. It provides a high-level interface to
-//! configure and control individual timers of the `LEDC` peripheral.
-//!
-//! The module allows precise and flexible control over timer configurations,
-//! duty cycles and frequencies, making it ideal for Pulse-Width Modulation
-//! (PWM) applications and LED lighting control.
-
-use fugit::HertzU32;
-
-#[cfg(esp32)]
-use super::HighSpeed;
-use super::{LowSpeed, Speed};
-use crate::{clock::Clocks, peripherals::ledc};
-
-const LEDC_TIMER_DIV_NUM_MAX: u64 = 0x3FFFF;
-
-/// Timer errors
-#[derive(Debug, Clone, Copy, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Error {
-    /// Invalid Divisor
-    Divisor,
-}
-
-#[cfg(esp32)]
-/// Clock source for HS Timers
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum HSClockSource {
-    APBClk,
-    // TODO RefTick,
-}
-
-/// Clock source for LS Timers
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum LSClockSource {
-    APBClk,
-    // TODO SLOWClk
-}
-
-/// Timer number
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Number {
-    Timer0,
-    Timer1,
-    Timer2,
-    Timer3,
-}
-
-/// Timer configuration
-pub mod config {
-    use fugit::HertzU32;
-
-    /// Number of bits reserved for duty cycle adjustment
-    #[derive(PartialEq, Eq, Copy, Clone, Debug)]
-    #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-    pub enum Duty {
-        Duty1Bit = 1,
-        Duty2Bit,
-        Duty3Bit,
-        Duty4Bit,
-        Duty5Bit,
-        Duty6Bit,
-        Duty7Bit,
-        Duty8Bit,
-        Duty9Bit,
-        Duty10Bit,
-        Duty11Bit,
-        Duty12Bit,
-        Duty13Bit,
-        Duty14Bit,
-        #[cfg(esp32)]
-        Duty15Bit,
-        #[cfg(esp32)]
-        Duty16Bit,
-        #[cfg(esp32)]
-        Duty17Bit,
-        #[cfg(esp32)]
-        Duty18Bit,
-        #[cfg(esp32)]
-        Duty19Bit,
-        #[cfg(esp32)]
-        Duty20Bit,
-    }
-
-    /// Timer configuration
-    #[derive(Copy, Clone)]
-    pub struct Config<CS> {
-        pub duty: Duty,
-        pub clock_source: CS,
-        pub frequency: HertzU32,
-    }
-}
-
-/// Trait defining the type of timer source
-pub trait TimerSpeed: Speed {
-    type ClockSourceType;
-}
-
-/// Timer source type for LowSpeed timers
-impl TimerSpeed for LowSpeed {
-    type ClockSourceType = LSClockSource;
-}
-
-#[cfg(esp32)]
-/// Timer source type for HighSpeed timers
-impl TimerSpeed for HighSpeed {
-    type ClockSourceType = HSClockSource;
-}
-
-/// Interface for Timers
-pub trait TimerIFace<S: TimerSpeed> {
-    /// Return the frequency of the timer
-    fn get_freq(&self) -> Option<HertzU32>;
-
-    /// Configure the timer
-    fn configure(&mut self, config: config::Config<S::ClockSourceType>) -> Result<(), Error>;
-
-    /// Check if the timer has been configured
-    fn is_configured(&self) -> bool;
-
-    /// Return the duty resolution of the timer
-    fn get_duty(&self) -> Option<config::Duty>;
-
-    /// Return the timer number
-    fn get_number(&self) -> Number;
-
-    /// Return the timer frequency, or 0 if not configured
-    fn get_frequency(&self) -> u32;
-}
-
-/// Interface for HW configuration of timer
-pub trait TimerHW<S: TimerSpeed> {
-    /// Get the current source timer frequency from the HW
-    fn get_freq_hw(&self) -> Option<HertzU32>;
-
-    /// Configure the HW for the timer
-    fn configure_hw(&self, divisor: u32);
-
-    /// Update the timer in HW
-    fn update_hw(&self);
-}
-
-/// Timer struct
-pub struct Timer<'a, S: TimerSpeed> {
-    ledc: &'a crate::peripherals::ledc::RegisterBlock,
-    clock_control_config: &'a Clocks<'a>,
-    number: Number,
-    duty: Option<config::Duty>,
-    frequency: u32,
-    configured: bool,
-    use_ref_tick: bool,
-    clock_source: Option<S::ClockSourceType>,
-}
-
-impl<'a, S: TimerSpeed> TimerIFace<S> for Timer<'a, S>
-where
-    Timer<'a, S>: TimerHW<S>,
-{
-    /// Return the frequency of the timer
-    fn get_freq(&self) -> Option<HertzU32> {
-        self.get_freq_hw()
-    }
-
-    /// Configure the timer
-    fn configure(&mut self, config: config::Config<S::ClockSourceType>) -> Result<(), Error> {
-        self.duty = Some(config.duty);
-        self.clock_source = Some(config.clock_source);
-
-        // TODO: we should return some error here if `unwrap()` fails
-        let src_freq: u32 = self.get_freq().unwrap().to_Hz();
-        let precision = 1 << config.duty as u32;
-        let frequency: u32 = config.frequency.raw();
-        self.frequency = frequency;
-
-        let mut divisor = ((src_freq as u64) << 8) / frequency as u64 / precision as u64;
-
-        if divisor > LEDC_TIMER_DIV_NUM_MAX {
-            // APB_CLK results in divisor which too high. Try using REF_TICK as clock
-            // source.
-            self.use_ref_tick = true;
-            divisor = ((1_000_000 as u64) << 8) / frequency as u64 / precision as u64;
-        }
-
-        if divisor >= LEDC_TIMER_DIV_NUM_MAX || divisor < 256 {
-            return Err(Error::Divisor);
-        }
-
-        self.configure_hw(divisor as u32);
-        self.update_hw();
-
-        self.configured = true;
-
-        Ok(())
-    }
-
-    /// Check if the timer has been configured
-    fn is_configured(&self) -> bool {
-        self.configured
-    }
-
-    /// Return the duty resolution of the timer
-    fn get_duty(&self) -> Option<config::Duty> {
-        self.duty
-    }
-
-    /// Return the timer number
-    fn get_number(&self) -> Number {
-        self.number
-    }
-
-    /// Return the timer frequency
-    fn get_frequency(&self) -> u32 {
-        self.frequency
-    }
-}
-
-impl<'a, S: TimerSpeed> Timer<'a, S> {
-    /// Create a new intance of a timer
-    pub fn new(
-        ledc: &'a ledc::RegisterBlock,
-        clock_control_config: &'a Clocks,
-        number: Number,
-    ) -> Self {
-        Timer {
-            ledc,
-            clock_control_config,
-            number,
-            duty: None,
-            frequency: 0u32,
-            configured: false,
-            use_ref_tick: false,
-            clock_source: None,
-        }
-    }
-}
-
-/// Timer HW implementation for LowSpeed timers
-impl<'a> TimerHW<LowSpeed> for Timer<'a, LowSpeed> {
-    /// Get the current source timer frequency from the HW
-    fn get_freq_hw(&self) -> Option<fugit::HertzU32> {
-        self.clock_source.map(|cs| match cs {
-            LSClockSource::APBClk => self.clock_control_config.apb_clock,
-        })
-    }
-
-    #[cfg(esp32)]
-    /// Configure the HW for the timer
-    fn configure_hw(&self, divisor: u32) {
-        let duty = unwrap!(self.duty) as u8;
-        let use_apb = !self.use_ref_tick;
-
-        match self.number {
-            Number::Timer0 => self.ledc.lstimer0_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_apb)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer1 => self.ledc.lstimer1_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_apb)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer2 => self.ledc.lstimer2_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_apb)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer3 => self.ledc.lstimer3_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_apb)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-        };
-    }
-
-    #[cfg(not(esp32))]
-    /// Configure the HW for the timer
-    fn configure_hw(&self, divisor: u32) {
-        let duty = unwrap!(self.duty) as u8;
-        let use_ref_tick = self.use_ref_tick;
-
-        match self.number {
-            Number::Timer0 => self.ledc.timer0_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_ref_tick)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .clk_div()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer1 => self.ledc.timer1_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_ref_tick)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .clk_div()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer2 => self.ledc.timer2_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_ref_tick)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .clk_div()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer3 => self.ledc.timer3_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(use_ref_tick)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .clk_div()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-        };
-    }
-
-    #[cfg(esp32)]
-    /// Update the timer in HW
-    fn update_hw(&self) {
-        match self.number {
-            Number::Timer0 => self
-                .ledc
-                .lstimer0_conf()
-                .modify(|_, w| w.para_up().set_bit()),
-            Number::Timer1 => self
-                .ledc
-                .lstimer1_conf()
-                .modify(|_, w| w.para_up().set_bit()),
-            Number::Timer2 => self
-                .ledc
-                .lstimer2_conf()
-                .modify(|_, w| w.para_up().set_bit()),
-            Number::Timer3 => self
-                .ledc
-                .lstimer3_conf()
-                .modify(|_, w| w.para_up().set_bit()),
-        };
-    }
-
-    #[cfg(not(esp32))]
-    /// Update the timer in HW
-    fn update_hw(&self) {
-        match self.number {
-            Number::Timer0 => self.ledc.timer0_conf().modify(|_, w| w.para_up().set_bit()),
-            Number::Timer1 => self.ledc.timer1_conf().modify(|_, w| w.para_up().set_bit()),
-            Number::Timer2 => self.ledc.timer2_conf().modify(|_, w| w.para_up().set_bit()),
-            Number::Timer3 => self.ledc.timer3_conf().modify(|_, w| w.para_up().set_bit()),
-        };
-    }
-}
-
-#[cfg(esp32)]
-/// Timer HW implementation for HighSpeed timers
-impl<'a> TimerHW<HighSpeed> for Timer<'a, HighSpeed> {
-    /// Get the current source timer frequency from the HW
-    fn get_freq_hw(&self) -> Option<HertzU32> {
-        self.clock_source.map(|cs| match cs {
-            // TODO RefTick HSClockSource::RefTick => self.clock_control_config.apb_clock,
-            HSClockSource::APBClk => self.clock_control_config.apb_clock,
-        })
-    }
-
-    /// Configure the HW for the timer
-    fn configure_hw(&self, divisor: u32) {
-        let duty = unwrap!(self.duty) as u8;
-        let sel_hstimer = self.clock_source == Some(HSClockSource::APBClk);
-
-        match self.number {
-            Number::Timer0 => self.ledc.hstimer0_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(sel_hstimer)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer1 => self.ledc.hstimer1_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(sel_hstimer)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer2 => self.ledc.hstimer2_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(sel_hstimer)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-            Number::Timer3 => self.ledc.hstimer3_conf().modify(|_, w| unsafe {
-                w.tick_sel()
-                    .bit(sel_hstimer)
-                    .rst()
-                    .clear_bit()
-                    .pause()
-                    .clear_bit()
-                    .div_num()
-                    .bits(divisor)
-                    .duty_res()
-                    .bits(duty)
-            }),
-        };
-    }
-
-    /// Update the timer in HW
-    fn update_hw(&self) {
-        // Nothing to do for HS timers
-    }
-}

esp-hal-common/src/lib.rs

@@ -1,447 +0,0 @@
-//! `no_std` HAL implementations for the peripherals which are common among
-//! Espressif devices. Implements a number of the traits defined by
-//! [embedded-hal].
-//!
-//! This crate should not be used directly; you should use one of the
-//! device-specific HAL crates instead:
-//!
-//! - [esp32-hal]
-//! - [esp32c2-hal]
-//! - [esp32c3-hal]
-//! - [esp32c6-hal]
-//! - [esp32h2-hal]
-//! - [esp32s2-hal]
-//! - [esp32s3-hal]
-//!
-//! [embedded-hal]: https://docs.rs/embedded-hal/latest/embedded_hal/
-//! [esp32-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32-hal
-//! [esp32c2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c2-hal
-//! [esp32c3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c3-hal
-//! [esp32c6-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c6-hal
-//! [esp32h2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32h2-hal
-//! [esp32s2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s2-hal
-//! [esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal
-
-#![no_std]
-#![cfg_attr(xtensa, feature(asm_experimental_arch))]
-#![cfg_attr(
-    feature = "async",
-    allow(incomplete_features, stable_features, unknown_lints, async_fn_in_trait),
-    feature(async_fn_in_trait),
-    feature(impl_trait_projections)
-)]
-#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
-
-// MUST be the first module
-mod fmt;
-
-#[cfg(riscv)]
-pub use esp_riscv_rt::{self, entry, riscv};
-pub use procmacros as macros;
-#[cfg(xtensa)]
-pub use xtensa_lx;
-#[cfg(xtensa)]
-pub use xtensa_lx_rt::{self, entry};
-
-#[cfg(adc)]
-pub use self::analog::adc;
-#[cfg(dac)]
-pub use self::analog::dac;
-#[cfg(any(xtensa, all(riscv, systimer)))]
-pub use self::delay::Delay;
-#[cfg(gdma)]
-pub use self::dma::gdma;
-#[cfg(pdma)]
-pub use self::dma::pdma;
-#[cfg(gpio)]
-pub use self::gpio::IO;
-#[cfg(rmt)]
-pub use self::rmt::Rmt;
-#[cfg(rng)]
-pub use self::rng::Rng;
-#[cfg(any(lp_clkrst, rtc_cntl))]
-pub use self::rtc_cntl::{Rtc, Rwdt};
-#[cfg(any(esp32, esp32s3))]
-pub use self::soc::cpu_control;
-#[cfg(efuse)]
-pub use self::soc::efuse;
-#[cfg(lp_core)]
-pub use self::soc::lp_core;
-pub use self::soc::peripherals;
-#[cfg(psram)]
-pub use self::soc::psram;
-#[cfg(ulp_riscv_core)]
-pub use self::soc::ulp_core;
-#[cfg(any(timg0, timg1))]
-pub use self::timer::Timer;
-#[cfg(any(uart0, uart1, uart2))]
-pub use self::uart::{Uart, UartRx, UartTx};
-#[cfg(usb_device)]
-pub use self::usb_serial_jtag::UsbSerialJtag;
-
-#[cfg(aes)]
-pub mod aes;
-#[cfg(any(adc, dac))]
-pub mod analog;
-#[cfg(assist_debug)]
-pub mod assist_debug;
-pub mod clock;
-#[cfg(any(xtensa, all(riscv, systimer)))]
-pub mod delay;
-#[cfg(any(gdma, pdma))]
-pub mod dma;
-#[cfg(ecc)]
-pub mod ecc;
-#[cfg(feature = "embassy")]
-pub mod embassy;
-#[cfg(soc_etm)]
-pub mod etm;
-#[cfg(gpio)]
-pub mod gpio;
-#[cfg(hmac)]
-pub mod hmac;
-#[cfg(any(i2c0, i2c1))]
-pub mod i2c;
-#[cfg(any(i2s0, i2s1))]
-pub mod i2s;
-#[cfg(any(dport, interrupt_core0, interrupt_core1))]
-pub mod interrupt;
-#[cfg(ledc)]
-pub mod ledc;
-#[cfg(any(mcpwm0, mcpwm1))]
-pub mod mcpwm;
-#[cfg(usb0)]
-pub mod otg_fs;
-#[cfg(parl_io)]
-pub mod parl_io;
-#[cfg(pcnt)]
-pub mod pcnt;
-pub mod peripheral;
-pub mod prelude;
-#[cfg(any(hmac, sha))]
-mod reg_access;
-pub mod reset;
-#[cfg(rmt)]
-pub mod rmt;
-#[cfg(rng)]
-pub mod rng;
-pub mod rom;
-#[cfg(rsa)]
-pub mod rsa;
-#[cfg(any(lp_clkrst, rtc_cntl))]
-pub mod rtc_cntl;
-#[cfg(sha)]
-pub mod sha;
-#[cfg(any(spi0, spi1, spi2, spi3))]
-pub mod spi;
-#[cfg(any(dport, pcr, system))]
-pub mod system;
-#[cfg(systimer)]
-pub mod systimer;
-#[cfg(any(timg0, timg1))]
-pub mod timer;
-#[cfg(trace)]
-pub mod trace;
-#[cfg(any(twai0, twai1))]
-pub mod twai;
-#[cfg(any(uart0, uart1, uart2))]
-pub mod uart;
-#[cfg(usb_device)]
-pub mod usb_serial_jtag;
-
-/// State of the CPU saved when entering exception or interrupt
-pub mod trapframe {
-    #[cfg(riscv)]
-    pub use esp_riscv_rt::TrapFrame;
-    #[cfg(xtensa)]
-    pub use xtensa_lx_rt::exception::Context as TrapFrame;
-}
-
-// The `soc` module contains chip-specific implementation details and should not
-// be directly exposed.
-mod soc;
-
-#[cfg(xtensa)]
-#[no_mangle]
-extern "C" fn EspDefaultHandler(_level: u32, _interrupt: peripherals::Interrupt) {
-    #[cfg(not(feature = "defmt"))]
-    panic!("Unhandled level {} interrupt: {:?}", _level, _interrupt);
-
-    #[cfg(feature = "defmt")]
-    panic!(
-        "Unhandled level {} interrupt: {:?}",
-        _level,
-        defmt::Debug2Format(&_interrupt)
-    );
-}
-
-#[cfg(riscv)]
-#[no_mangle]
-extern "C" fn EspDefaultHandler(_interrupt: peripherals::Interrupt) {
-    #[cfg(not(feature = "defmt"))]
-    panic!("Unhandled interrupt: {:?}", _interrupt);
-
-    #[cfg(feature = "defmt")]
-    panic!(
-        "Unhandled interrupt: {:?}",
-        defmt::Debug2Format(&_interrupt)
-    );
-}
-
-/// Available CPU cores
-///
-/// The actual number of available cores depends on the target.
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Cpu {
-    /// The first core
-    ProCpu = 0,
-    /// The second core
-    #[cfg(multi_core)]
-    AppCpu,
-}
-
-#[cfg(all(xtensa, multi_core))]
-fn get_raw_core() -> u32 {
-    xtensa_lx::get_processor_id() & 0x2000
-}
-
-/// Which core the application is currently executing on
-#[cfg(all(xtensa, multi_core))]
-pub fn get_core() -> Cpu {
-    match get_raw_core() {
-        0 => Cpu::ProCpu,
-        _ => Cpu::AppCpu,
-    }
-}
-
-/// Which core the application is currently executing on
-#[cfg(not(all(xtensa, multi_core)))]
-pub fn get_core() -> Cpu {
-    Cpu::ProCpu
-}
-
-mod critical_section_impl {
-    struct CriticalSection;
-
-    critical_section::set_impl!(CriticalSection);
-
-    #[cfg(xtensa)]
-    mod xtensa {
-        // PS has 15 useful bits. Bits 12..16 and 19..32 are unused, so we can use bit
-        // #31 as our reentry flag.
-        #[cfg(multi_core)]
-        const REENTRY_FLAG: u32 = 1 << 31;
-
-        unsafe impl critical_section::Impl for super::CriticalSection {
-            unsafe fn acquire() -> critical_section::RawRestoreState {
-                let mut tkn: critical_section::RawRestoreState;
-                core::arch::asm!("rsil {0}, 5", out(reg) tkn);
-                #[cfg(multi_core)]
-                {
-                    use super::multicore::{LockKind, MULTICORE_LOCK};
-
-                    match MULTICORE_LOCK.lock() {
-                        LockKind::Lock => {
-                            // We can assume the reserved bit is 0 otherwise
-                            // rsil - wsr pairings would be undefined behavior
-                        }
-                        LockKind::Reentry => tkn |= REENTRY_FLAG,
-                    }
-                }
-                tkn
-            }
-
-            unsafe fn release(token: critical_section::RawRestoreState) {
-                #[cfg(multi_core)]
-                {
-                    use super::multicore::MULTICORE_LOCK;
-
-                    debug_assert!(MULTICORE_LOCK.is_owned_by_current_thread());
-
-                    if token & REENTRY_FLAG != 0 {
-                        return;
-                    }
-
-                    MULTICORE_LOCK.unlock();
-                }
-
-                const RESERVED_MASK: u32 = 0b1111_1111_1111_1000_1111_0000_0000_0000;
-                debug_assert!(token & RESERVED_MASK == 0);
-
-                core::arch::asm!(
-                    "wsr.ps {0}",
-                    "rsync", in(reg) token)
-            }
-        }
-    }
-
-    #[cfg(riscv)]
-    mod riscv {
-        use esp_riscv_rt::riscv;
-
-        #[cfg(multi_core)]
-        // The restore state is a u8 that is casted from a bool, so it has a value of
-        // 0x00 or 0x01 before we add the reentry flag to it.
-        const REENTRY_FLAG: u8 = 1 << 7;
-
-        unsafe impl critical_section::Impl for super::CriticalSection {
-            unsafe fn acquire() -> critical_section::RawRestoreState {
-                let mut mstatus = 0u32;
-                core::arch::asm!("csrrci {0}, mstatus, 8", inout(reg) mstatus);
-                let tkn = ((mstatus & 0b1000) != 0) as critical_section::RawRestoreState;
-
-                #[cfg(multi_core)]
-                {
-                    use super::multicore::{LockKind, MULTICORE_LOCK};
-
-                    match MULTICORE_LOCK.lock() {
-                        LockKind::Lock => {}
-                        LockKind::Reentry => tkn |= REENTRY_FLAG,
-                    }
-                }
-
-                tkn
-            }
-
-            unsafe fn release(token: critical_section::RawRestoreState) {
-                #[cfg(multi_core)]
-                {
-                    use super::multicore::MULTICORE_LOCK;
-
-                    debug_assert!(MULTICORE_LOCK.is_owned_by_current_thread());
-
-                    if token & REENTRY_FLAG != 0 {
-                        return;
-                    }
-
-                    MULTICORE_LOCK.unlock();
-                }
-
-                if token != 0 {
-                    riscv::interrupt::enable();
-                }
-            }
-        }
-    }
-
-    #[cfg(multi_core)]
-    mod multicore {
-        use portable_atomic::{AtomicUsize, Ordering};
-
-        // We're using a value that we know get_raw_core() will never return. This
-        // avoids an unnecessary increment of the core ID.
-        #[cfg(xtensa)] // TODO: first multi-core RISC-V target will show if this value is OK
-                       // globally or only for Xtensa
-        const UNUSED_THREAD_ID_VALUE: usize = 0x0001;
-
-        fn thread_id() -> usize {
-            crate::get_raw_core() as usize
-        }
-
-        pub(super) static MULTICORE_LOCK: ReentrantMutex = ReentrantMutex::new();
-
-        pub(super) enum LockKind {
-            Lock = 0,
-            Reentry,
-        }
-
-        pub(super) struct ReentrantMutex {
-            owner: AtomicUsize,
-        }
-
-        impl ReentrantMutex {
-            const fn new() -> Self {
-                Self {
-                    owner: AtomicUsize::new(UNUSED_THREAD_ID_VALUE),
-                }
-            }
-
-            pub fn is_owned_by_current_thread(&self) -> bool {
-                self.owner.load(Ordering::Relaxed) == thread_id()
-            }
-
-            pub(super) fn lock(&self) -> LockKind {
-                let current_thread_id = thread_id();
-
-                if self.try_lock(current_thread_id) {
-                    return LockKind::Lock;
-                }
-
-                let current_owner = self.owner.load(Ordering::Relaxed);
-                if current_owner == current_thread_id {
-                    return LockKind::Reentry;
-                }
-
-                while !self.try_lock(current_thread_id) {}
-
-                LockKind::Lock
-            }
-
-            fn try_lock(&self, new_owner: usize) -> bool {
-                self.owner
-                    .compare_exchange(
-                        UNUSED_THREAD_ID_VALUE,
-                        new_owner,
-                        Ordering::Acquire,
-                        Ordering::Relaxed,
-                    )
-                    .is_ok()
-            }
-
-            pub(super) fn unlock(&self) {
-                self.owner.store(UNUSED_THREAD_ID_VALUE, Ordering::Release);
-            }
-        }
-    }
-}
-
-/// FlashSafeDma
-///
-/// The embedded-hal traits make no guarantees about
-/// where the buffers are placed. The DMA implementation in Espressif chips has
-/// a limitation in that it can only access the RAM address space, meaning data
-/// to be transmitted from the flash address space must be copied into RAM
-/// first.
-///
-/// This wrapper struct should be used when a peripheral using the DMA engine
-/// needs to transmit data from flash (ROM) via the embedded-hal traits. This is
-/// often a `const` variable.
-///
-/// Example usage using [`spi::master::dma::SpiDma`]
-/// ```no_run
-/// const ARRAY_IN_FLASH = [0xAA; 128]
-///
-/// let spi = SpiDma::new(/* */);
-///
-/// spi.write(&ARRAY_IN_FLASH[..]).unwrap(); // error when transmission starts
-///
-/// let spi = FlashSafeDma::new(spi);
-///
-/// spi.write(&ARRAY_IN_FLASH[..]).unwrap(); // success
-/// ```
-pub struct FlashSafeDma<T, const SIZE: usize> {
-    inner: T,
-    buffer: [u8; SIZE],
-}
-
-impl<T, const SIZE: usize> FlashSafeDma<T, SIZE> {
-    pub fn new(inner: T) -> Self {
-        Self {
-            inner,
-            buffer: [0u8; SIZE],
-        }
-    }
-
-    pub fn inner_mut(&mut self) -> &mut T {
-        &mut self.inner
-    }
-
-    pub fn inner(&self) -> &T {
-        &self.inner
-    }
-
-    pub fn free(self) -> T {
-        self.inner
-    }
-}

esp-hal-common/src/mcpwm/operator.rs

@@ -1,838 +0,0 @@
-//! # MCPWM peripheral - operator module
-//!
-//! ## Overview
-//! The `operator` module is part of the `MCPWM` peripheral driver for
-//! `ESP` chips. It is responsible for
-//! generating `PWM (Pulse Width Modulation)` signals and handling various
-//! aspects related to `PWM` signal generation.
-//!
-//! This module provides flexibility in configuring the PWM outputs. Its
-//! implementation allows for motor control and other applications that demand
-//! accurate pulse timing and sophisticated modulation techniques.
-
-use core::marker::PhantomData;
-
-use crate::{
-    gpio::OutputPin,
-    mcpwm::{timer::Timer, PwmPeripheral},
-    peripheral::{Peripheral, PeripheralRef},
-};
-
-/// Input/Output Stream descriptor for each channel
-pub enum PWMStream {
-    /// PWM Stream A
-    PWMA,
-    /// PWM Stream B
-    PWMB,
-}
-
-/// Configuration for MCPWM Operator DeadTime
-/// It's recommended to reference the technical manual for configuration
-pub struct DeadTimeCfg {
-    cfg_reg: u32,
-    rising_edge_delay: u16,
-    falling_edge_delay: u16,
-}
-
-impl DeadTimeCfg {
-    // NOTE: it's a bit difficult to make this typestate
-    // due to the different interconnections (FED/RED vs PWMxA/PWMxB) and
-    // the many mode of operation
-
-    /// Uses the following configuration:
-    /// * Clock: PWM_clk
-    /// * Bypass: A & B
-    /// * Inputs: A->A, B->B (InSel)
-    /// * Outputs: A->A, B->B (OutSwap)
-    /// * No Dual-edge B
-    /// * No Invert
-    /// * FED/RED update mode = immediate
-    /// * FED/RED = 0
-    pub fn new_bypass() -> DeadTimeCfg {
-        DeadTimeCfg {
-            cfg_reg: 0b0_11_00_00_00_0_000_000,
-            rising_edge_delay: 0,
-            falling_edge_delay: 0,
-        }
-    }
-
-    /// Active High Complementary (AHC) from Technical Reference manual
-    ///
-    /// Will generate a PWM from input PWMA, such that output PWMA & PWMB are
-    /// each others complement Except during a transition in which they will
-    /// be both off (as deadtime) such that they should never overlap, useful
-    /// for H-Bridge type scenarios
-    ///
-    /// Default delay on both rising (red) and falling (fed) edge is 16 cycles
-    pub fn new_ahc(red_delay: Option<u16>, fed_delay: Option<u16>) -> DeadTimeCfg {
-        DeadTimeCfg {
-            cfg_reg: 0b0_00_10_00_00_0_000_000,
-            rising_edge_delay: red_delay.unwrap_or(16u16),
-            falling_edge_delay: fed_delay.unwrap_or(16u16),
-        }
-    }
-    // TODO: Add some common configurations ~AHC~,ALC,AH,AC
-
-    fn set_flag(&mut self, offset: u8, val: bool) {
-        let mask = !(1 << offset);
-        self.cfg_reg = self.cfg_reg & mask | ((val as u32) << offset);
-    }
-
-    /// Sets the delay for the FED/RED module
-    pub fn set_delay(&mut self, rising_edge: u16, falling_edge: u16) {
-        self.rising_edge_delay = rising_edge;
-        self.falling_edge_delay = falling_edge;
-    }
-
-    /// Sets FED/RED output inverter
-    /// Inverts the output of the FED/RED module (excl DEB mode feedback)
-    pub fn invert_output(&mut self, fed: bool, red: bool) {
-        self.set_flag(13, fed);
-        self.set_flag(14, red);
-    }
-
-    /// Swaps the output of a PWM Stream
-    /// i.e. If streams have output_swap enabled, the output of the module
-    /// is swapped, while if only one is enabled that one 'copies' from the
-    /// other stream
-    pub fn set_output_swap(&mut self, stream: PWMStream, swap: bool) {
-        self.set_flag(
-            match stream {
-                PWMStream::PWMA => 9,
-                PWMStream::PWMB => 10,
-            },
-            swap,
-        );
-    }
-
-    /// Set PWMA/PWMB stream to bypass everything except output_swap
-    /// This means no deadtime is applied when enabled
-    pub fn set_bypass(&mut self, stream: PWMStream, enable: bool) {
-        self.set_flag(
-            match stream {
-                PWMStream::PWMA => 15,
-                PWMStream::PWMB => 16,
-            },
-            enable,
-        );
-    }
-
-    /// Select Between PWMClk & PT_Clk
-    pub fn select_clock(&mut self, pwm_clock: bool) {
-        self.set_flag(17, pwm_clock);
-    }
-
-    /// Select which stream is used for the input of FED/RED
-    pub fn select_input(&mut self, fed: PWMStream, red: PWMStream) {
-        self.set_flag(
-            12,
-            match fed {
-                PWMStream::PWMA => false,
-                PWMStream::PWMB => true,
-            },
-        );
-        self.set_flag(
-            11,
-            match red {
-                PWMStream::PWMA => false,
-                PWMStream::PWMB => true,
-            },
-        );
-    }
-}
-
-#[cfg(feature = "esp32s3")]
-fn dt_cfg<const OP: u8, PWM: PwmPeripheral>() -> &'static crate::peripherals::mcpwm0::DB0_CFG {
-    let block = unsafe { &*PWM::block() };
-    match OP {
-        0 => &block.db0_cfg(),
-        1 => unsafe { &*(&block.db1_cfg() as *const _ as *const _) },
-        2 => unsafe { &*(&block.db2_cfg() as *const _ as *const _) },
-        _ => unreachable!(),
-    }
-}
-#[cfg(feature = "esp32s3")]
-fn dt_fed<const OP: u8, PWM: PwmPeripheral>() -> &'static crate::peripherals::mcpwm0::DB0_FED_CFG {
-    let block = unsafe { &*PWM::block() };
-    match OP {
-        0 => &block.db0_fed_cfg(),
-        1 => unsafe { &*(&block.db1_fed_cfg() as *const _ as *const _) },
-        2 => unsafe { &*(&block.db2_fed_cfg() as *const _ as *const _) },
-        _ => unreachable!(),
-    }
-}
-#[cfg(feature = "esp32s3")]
-fn dt_red<const OP: u8, PWM: PwmPeripheral>() -> &'static crate::peripherals::mcpwm0::DB0_RED_CFG {
-    let block = unsafe { &*PWM::block() };
-    match OP {
-        0 => &block.db0_red_cfg(),
-        1 => unsafe { &*(&block.db1_red_cfg() as *const _ as *const _) },
-        2 => unsafe { &*(&block.db2_red_cfg() as *const _ as *const _) },
-        _ => unreachable!(),
-    }
-}
-
-// TODO: dt_cfg, dt_fed, dt_red (and similar functions in mcpwm can be made safe
-// by patching PACS)
-#[cfg(not(feature = "esp32s3"))]
-fn dt_cfg<const OP: u8, PWM: PwmPeripheral>() -> &'static crate::peripherals::mcpwm0::DT0_CFG {
-    let block = unsafe { &*PWM::block() };
-    match OP {
-        0 => &block.dt0_cfg(),
-        1 => unsafe { &*(&block.dt1_cfg() as *const _ as *const _) },
-        2 => unsafe { &*(&block.dt2_cfg() as *const _ as *const _) },
-        _ => unreachable!(),
-    }
-}
-
-#[cfg(not(feature = "esp32s3"))]
-fn dt_fed<const OP: u8, PWM: PwmPeripheral>() -> &'static crate::peripherals::mcpwm0::DT0_FED_CFG {
-    let block = unsafe { &*PWM::block() };
-    match OP {
-        0 => &block.dt0_fed_cfg(),
-        1 => unsafe { &*(&block.dt1_fed_cfg() as *const _ as *const _) },
-        2 => unsafe { &*(&block.dt2_fed_cfg() as *const _ as *const _) },
-        _ => unreachable!(),
-    }
-}
-#[cfg(not(feature = "esp32s3"))]
-fn dt_red<const OP: u8, PWM: PwmPeripheral>() -> &'static crate::peripherals::mcpwm0::DT0_RED_CFG {
-    let block = unsafe { &*PWM::block() };
-    match OP {
-        0 => &block.dt0_red_cfg(),
-        1 => unsafe { &*(&block.dt1_red_cfg() as *const _ as *const _) },
-        2 => unsafe { &*(&block.dt2_red_cfg() as *const _ as *const _) },
-        _ => unreachable!(),
-    }
-}
-
-/// A MCPWM operator
-///
-/// The PWM Operator submodule has the following functions:
-/// * Generates a PWM signal pair, based on timing references obtained from the
-///   corresponding PWM timer.
-/// * Each signal out of the PWM signal pair includes a specific pattern of dead
-///   time. (Not yet implemented)
-/// * Superimposes a carrier on the PWM signal, if configured to do so. (Not yet
-///   implemented)
-/// * Handles response under fault conditions. (Not yet implemented)
-pub struct Operator<const OP: u8, PWM> {
-    phantom: PhantomData<PWM>,
-}
-
-impl<const OP: u8, PWM: PwmPeripheral> Operator<OP, PWM> {
-    pub(super) fn new() -> Self {
-        // Side note:
-        // It would have been nice to deselect any timer reference on peripheral
-        // initialization.
-        // However experimentation (ESP32-S3) showed that writing `3` to timersel
-        // will not disable the timer reference but instead act as though `2` was
-        // written.
-        Operator {
-            phantom: PhantomData,
-        }
-    }
-
-    /// Select a [`Timer`] to be the timing reference for this operator
-    ///
-    /// ### Note:
-    /// By default TIMER0 is used
-    pub fn set_timer<const TIM: u8>(&mut self, timer: &Timer<TIM, PWM>) {
-        let _ = timer;
-        // SAFETY:
-        // We only write to our OPERATORx_TIMERSEL register
-        let block = unsafe { &*PWM::block() };
-        block.operator_timersel().modify(|_, w| match OP {
-            0 => w.operator0_timersel().variant(TIM),
-            1 => w.operator1_timersel().variant(TIM),
-            2 => w.operator2_timersel().variant(TIM),
-            _ => {
-                unreachable!()
-            }
-        });
-    }
-
-    /// Configures deadtime for this operator
-    pub fn set_deadtime(&mut self, cfg: &DeadTimeCfg) {
-        dt_fed::<OP, PWM>().write(|w| unsafe { w.bits(cfg.falling_edge_delay as u32) });
-        dt_red::<OP, PWM>().write(|w| unsafe { w.bits(cfg.rising_edge_delay as u32) });
-        dt_cfg::<OP, PWM>().write(|w| unsafe { w.bits(cfg.cfg_reg) });
-    }
-
-    /// Use the A output with the given pin and configuration
-    pub fn with_pin_a<'d, Pin: OutputPin>(
-        self,
-        pin: impl Peripheral<P = Pin> + 'd,
-        config: PwmPinConfig<true>,
-    ) -> PwmPin<'d, Pin, PWM, OP, true> {
-        PwmPin::new(pin, config)
-    }
-
-    /// Use the B output with the given pin and configuration
-    pub fn with_pin_b<'d, Pin: OutputPin>(
-        self,
-        pin: impl Peripheral<P = Pin> + 'd,
-        config: PwmPinConfig<false>,
-    ) -> PwmPin<'d, Pin, PWM, OP, false> {
-        PwmPin::new(pin, config)
-    }
-
-    /// Use both the A and the B output with the given pins and configurations
-    pub fn with_pins<'d, PinA: OutputPin, PinB: OutputPin>(
-        self,
-        pin_a: impl Peripheral<P = PinA> + 'd,
-        config_a: PwmPinConfig<true>,
-        pin_b: impl Peripheral<P = PinB> + 'd,
-        config_b: PwmPinConfig<false>,
-    ) -> (
-        PwmPin<'d, PinA, PWM, OP, true>,
-        PwmPin<'d, PinB, PWM, OP, false>,
-    ) {
-        (PwmPin::new(pin_a, config_a), PwmPin::new(pin_b, config_b))
-    }
-}
-
-/// Configuration describing how the operator generates a signal on a connected
-/// pin
-pub struct PwmPinConfig<const IS_A: bool> {
-    actions: PwmActions<IS_A>,
-    update_method: PwmUpdateMethod,
-}
-
-impl<const IS_A: bool> PwmPinConfig<IS_A> {
-    /// A configuration using [`PwmActions::UP_ACTIVE_HIGH`] and
-    /// [`PwmUpdateMethod::SYNC_ON_ZERO`]
-    pub const UP_ACTIVE_HIGH: Self =
-        Self::new(PwmActions::UP_ACTIVE_HIGH, PwmUpdateMethod::SYNC_ON_ZERO);
-    /// A configuration using [`PwmActions::UP_DOWN_ACTIVE_HIGH`] and
-    /// [`PwmUpdateMethod::SYNC_ON_ZERO`]
-    pub const UP_DOWN_ACTIVE_HIGH: Self = Self::new(
-        PwmActions::UP_DOWN_ACTIVE_HIGH,
-        PwmUpdateMethod::SYNC_ON_ZERO,
-    );
-
-    /// Get a configuration using the given `PwmActions` and `PwmUpdateMethod`
-    pub const fn new(actions: PwmActions<IS_A>, update_method: PwmUpdateMethod) -> Self {
-        PwmPinConfig {
-            actions,
-            update_method,
-        }
-    }
-}
-
-/// A pin driven by an MCPWM operator
-pub struct PwmPin<'d, Pin, PWM, const OP: u8, const IS_A: bool> {
-    _pin: PeripheralRef<'d, Pin>,
-    phantom: PhantomData<PWM>,
-}
-
-impl<'d, Pin: OutputPin, PWM: PwmPeripheral, const OP: u8, const IS_A: bool>
-    PwmPin<'d, Pin, PWM, OP, IS_A>
-{
-    fn new(pin: impl Peripheral<P = Pin> + 'd, config: PwmPinConfig<IS_A>) -> Self {
-        crate::into_ref!(pin);
-        let output_signal = PWM::output_signal::<OP, IS_A>();
-        pin.enable_output(true)
-            .connect_peripheral_to_output(output_signal);
-        let mut pin = PwmPin {
-            _pin: pin,
-            phantom: PhantomData,
-        };
-        pin.set_actions(config.actions);
-        pin.set_update_method(config.update_method);
-        pin
-    }
-
-    /// Updates dead-time FED register
-    ///
-    /// WARNING: FED is connected to the operator, and could be connected to
-    /// another pin
-    #[inline]
-    pub fn update_fed(&self, cycles: u16) {
-        dt_fed::<OP, PWM>().write(|w| unsafe { w.bits(cycles as u32) });
-    }
-
-    /// Updates dead-time RED register
-    ///
-    /// WARNING: RED is connected to the operator, and could be connected to
-    /// another pin
-    #[inline]
-    pub fn update_red(&self, cycles: u16) {
-        dt_red::<OP, PWM>().write(|w| unsafe { w.bits(cycles as u32) });
-    }
-
-    /// Configure what actions should be taken on timing events
-    pub fn set_actions(&mut self, value: PwmActions<IS_A>) {
-        // SAFETY:
-        // We only write to our GENx_x register
-        let block = unsafe { &*PWM::block() };
-
-        let bits = value.0;
-
-        // SAFETY:
-        // `bits` is a valid bit pattern
-        unsafe {
-            match (OP, IS_A) {
-                (0, true) => block.gen0_a().write(|w| w.bits(bits)),
-                (1, true) => block.gen1_a().write(|w| w.bits(bits)),
-                (2, true) => block.gen2_a().write(|w| w.bits(bits)),
-                (0, false) => block.gen0_b().write(|w| w.bits(bits)),
-                (1, false) => block.gen1_b().write(|w| w.bits(bits)),
-                (2, false) => block.gen2_b().write(|w| w.bits(bits)),
-                _ => unreachable!(),
-            }
-        }
-    }
-
-    /// Set how a new timestamp syncs with the timer
-    #[cfg(esp32)]
-    pub fn set_update_method(&mut self, update_method: PwmUpdateMethod) {
-        // SAFETY:
-        // We only write to our GENx_x_UPMETHOD register
-        let block = unsafe { &*PWM::block() };
-        let bits = update_method.0;
-        match (OP, IS_A) {
-            (0, true) => block
-                .gen0_stmp_cfg()
-                .modify(|_, w| w.gen0_a_upmethod().variant(bits)),
-            (1, true) => block
-                .gen1_stmp_cfg()
-                .modify(|_, w| w.gen1_a_upmethod().variant(bits)),
-            (2, true) => block
-                .gen2_stmp_cfg()
-                .modify(|_, w| w.gen2_a_upmethod().variant(bits)),
-            (0, false) => block
-                .gen0_stmp_cfg()
-                .modify(|_, w| w.gen0_b_upmethod().variant(bits)),
-            (1, false) => block
-                .gen1_stmp_cfg()
-                .modify(|_, w| w.gen1_b_upmethod().variant(bits)),
-            (2, false) => block
-                .gen2_stmp_cfg()
-                .modify(|_, w| w.gen2_b_upmethod().variant(bits)),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Set how a new timestamp syncs with the timer
-    #[cfg(esp32s3)]
-    pub fn set_update_method(&mut self, update_method: PwmUpdateMethod) {
-        // SAFETY:
-        // We only write to our GENx_x_UPMETHOD register
-        let block = unsafe { &*PWM::block() };
-        let bits = update_method.0;
-        match (OP, IS_A) {
-            (0, true) => block
-                .cmpr0_cfg()
-                .modify(|_, w| w.cmpr0_a_upmethod().variant(bits)),
-            (1, true) => block
-                .cmpr1_cfg()
-                .modify(|_, w| w.cmpr1_a_upmethod().variant(bits)),
-            (2, true) => block
-                .cmpr2_cfg()
-                .modify(|_, w| w.cmpr2_a_upmethod().variant(bits)),
-            (0, false) => block
-                .cmpr0_cfg()
-                .modify(|_, w| w.cmpr0_b_upmethod().variant(bits)),
-            (1, false) => block
-                .cmpr1_cfg()
-                .modify(|_, w| w.cmpr1_b_upmethod().variant(bits)),
-            (2, false) => block
-                .cmpr2_cfg()
-                .modify(|_, w| w.cmpr2_b_upmethod().variant(bits)),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Set how a new timestamp syncs with the timer
-    #[cfg(any(esp32c6, esp32h2))]
-    pub fn set_update_method(&mut self, update_method: PwmUpdateMethod) {
-        // SAFETY:
-        // We only write to our GENx_x_UPMETHOD register
-        let block = unsafe { &*PWM::block() };
-        let bits = update_method.0;
-        match (OP, IS_A) {
-            (0, true) => block
-                .gen0_stmp_cfg()
-                .modify(|_, w| w.cmpr0_a_upmethod().variant(bits)),
-            (1, true) => block
-                .gen1_stmp_cfg()
-                .modify(|_, w| w.cmpr1_a_upmethod().variant(bits)),
-            (2, true) => block
-                .gen2_stmp_cfg()
-                .modify(|_, w| w.cmpr2_a_upmethod().variant(bits)),
-            (0, false) => block
-                .gen0_stmp_cfg()
-                .modify(|_, w| w.cmpr0_b_upmethod().variant(bits)),
-            (1, false) => block
-                .gen1_stmp_cfg()
-                .modify(|_, w| w.cmpr1_b_upmethod().variant(bits)),
-            (2, false) => block
-                .gen2_stmp_cfg()
-                .modify(|_, w| w.cmpr2_b_upmethod().variant(bits)),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Write a new timestamp.
-    /// The written value will take effect according to the set
-    /// [`PwmUpdateMethod`].
-    #[cfg(esp32)]
-    pub fn set_timestamp(&mut self, value: u16) {
-        // SAFETY:
-        // We only write to our GENx_TSTMP_x register
-        let block = unsafe { &*PWM::block() };
-        match (OP, IS_A) {
-            (0, true) => block.gen0_tstmp_a().write(|w| w.gen0_a().variant(value)),
-            (1, true) => block.gen1_tstmp_a().write(|w| w.gen1_a().variant(value)),
-            (2, true) => block.gen2_tstmp_a().write(|w| w.gen2_a().variant(value)),
-            (0, false) => block.gen0_tstmp_b().write(|w| w.gen0_b().variant(value)),
-            (1, false) => block.gen1_tstmp_b().write(|w| w.gen1_b().variant(value)),
-            (2, false) => block.gen2_tstmp_b().write(|w| w.gen2_b().variant(value)),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Get the old timestamp.
-    /// The value of the timestamp will take effect according to the set
-    /// [`PwmUpdateMethod`].
-    #[cfg(esp32)]
-    pub fn get_timestamp(&self) -> u16 {
-        // SAFETY:
-        // We only read to our GENx_TSTMP_x register
-        let block = unsafe { &*PWM::block() };
-        match (OP, IS_A) {
-            (0, true) => block.gen0_tstmp_a().read().gen0_a().bits(),
-            (1, true) => block.gen1_tstmp_a().read().gen1_a().bits(),
-            (2, true) => block.gen2_tstmp_a().read().gen2_a().bits(),
-            (0, false) => block.gen0_tstmp_b().read().gen0_b().bits(),
-            (1, false) => block.gen1_tstmp_b().read().gen1_b().bits(),
-            (2, false) => block.gen2_tstmp_b().read().gen2_b().bits(),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Write a new timestamp.
-    /// The written value will take effect according to the set
-    /// [`PwmUpdateMethod`].
-    #[cfg(esp32s3)]
-    pub fn set_timestamp(&mut self, value: u16) {
-        // SAFETY:
-        // We only write to our CMPRx_VALUEx register
-        let block = unsafe { &*PWM::block() };
-        match (OP, IS_A) {
-            (0, true) => block.cmpr0_value0().write(|w| w.cmpr0_a().variant(value)),
-            (1, true) => block.cmpr1_value0().write(|w| w.cmpr1_a().variant(value)),
-            (2, true) => block.cmpr2_value0().write(|w| w.cmpr2_a().variant(value)),
-            (0, false) => block.cmpr0_value1().write(|w| w.cmpr0_b().variant(value)),
-            (1, false) => block.cmpr1_value1().write(|w| w.cmpr1_b().variant(value)),
-            (2, false) => block.cmpr2_value1().write(|w| w.cmpr2_b().variant(value)),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Get the old timestamp.
-    /// The value of the timestamp will take effect according to the set
-    /// [`PwmUpdateMethod`].
-    #[cfg(esp32s3)]
-    pub fn get_timestamp(&self) -> u16 {
-        // SAFETY:
-        // We only read to our GENx_TSTMP_x register
-        let block = unsafe { &*PWM::block() };
-        match (OP, IS_A) {
-            (0, true) => block.cmpr0_value0().read().cmpr0_a().bits(),
-            (1, true) => block.cmpr1_value0().read().cmpr1_a().bits(),
-            (2, true) => block.cmpr2_value0().read().cmpr2_a().bits(),
-            (0, false) => block.cmpr0_value1().read().cmpr0_b().bits(),
-            (1, false) => block.cmpr1_value1().read().cmpr1_b().bits(),
-            (2, false) => block.cmpr2_value1().read().cmpr2_b().bits(),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Write a new timestamp.
-    /// The written value will take effect according to the set
-    /// [`PwmUpdateMethod`].
-    #[cfg(any(esp32c6, esp32h2))]
-    pub fn set_timestamp(&mut self, value: u16) {
-        // SAFETY:
-        // We only write to our GENx_TSTMP_x register
-        let block = unsafe { &*PWM::block() };
-        match (OP, IS_A) {
-            (0, true) => block.gen0_tstmp_a().write(|w| w.cmpr0_a().variant(value)),
-            (1, true) => block.gen1_tstmp_a().write(|w| w.cmpr1_a().variant(value)),
-            (2, true) => block.gen2_tstmp_a().write(|w| w.cmpr2_a().variant(value)),
-            (0, false) => block.gen0_tstmp_b().write(|w| w.cmpr0_b().variant(value)),
-            (1, false) => block.gen1_tstmp_b().write(|w| w.cmpr1_b().variant(value)),
-            (2, false) => block.gen2_tstmp_b().write(|w| w.cmpr2_b().variant(value)),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Get the old timestamp.
-    /// The value of the timestamp will take effect according to the set
-    /// [`PwmUpdateMethod`].
-    #[cfg(any(esp32c6, esp32h2))]
-    pub fn get_timestamp(&self) -> u16 {
-        // SAFETY:
-        // We only read to our GENx_TSTMP_x register
-        let block = unsafe { &*PWM::block() };
-        match (OP, IS_A) {
-            (0, true) => block.gen0_tstmp_a().read().cmpr0_a().bits(),
-            (1, true) => block.gen1_tstmp_a().read().cmpr1_a().bits(),
-            (2, true) => block.gen2_tstmp_a().read().cmpr2_a().bits(),
-            (0, false) => block.gen0_tstmp_b().read().cmpr0_b().bits(),
-            (1, false) => block.gen1_tstmp_b().read().cmpr1_b().bits(),
-            (2, false) => block.gen2_tstmp_b().read().cmpr2_b().bits(),
-            _ => {
-                unreachable!()
-            }
-        }
-    }
-
-    /// Get the period of the timer.
-    fn get_period(&self) -> u16 {
-        // SAFETY:
-        // We only grant access to our CFG0 register with the lifetime of &mut self
-        let block = unsafe { &*PWM::block() };
-
-        let tim_select = block.operator_timersel().read();
-        let tim = match OP {
-            0 => tim_select.operator0_timersel().bits(),
-            1 => tim_select.operator1_timersel().bits(),
-            2 => tim_select.operator2_timersel().bits(),
-            _ => {
-                unreachable!()
-            }
-        };
-
-        // SAFETY:
-        // The CFG0 registers are identical for all timers so we can pretend they're
-        // TIMER0_CFG0
-        let timer0_cfg = &block.timer0_cfg0();
-        let timer0_cfg = match tim {
-            0 => timer0_cfg,
-            1 => unsafe { &*(&block.timer1_cfg0() as *const _ as *const _) },
-            2 => unsafe { &*(&block.timer2_cfg0() as *const _ as *const _) },
-            _ => unreachable!(),
-        };
-
-        timer0_cfg.read().timer0_period().bits()
-    }
-}
-
-impl<'d, Pin: OutputPin, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> embedded_hal::PwmPin
-    for PwmPin<'d, Pin, PWM, OP, IS_A>
-{
-    type Duty = u16;
-
-    /// This only set the timestamp to 0, if you want to disable the PwmPin,
-    /// it must be done on the timer itself.
-    fn disable(&mut self) {
-        self.set_timestamp(0);
-    }
-
-    /// This only set the timestamp to the maximum, if you want to disable the
-    /// PwmPin, it must be done on the timer itself.
-    fn enable(&mut self) {
-        self.set_timestamp(u16::MAX);
-    }
-
-    /// Get the duty of the pin
-    fn get_duty(&self) -> Self::Duty {
-        self.get_timestamp()
-    }
-
-    /// Get the max duty of the pin
-    fn get_max_duty(&self) -> Self::Duty {
-        self.get_period()
-    }
-
-    /// Set the duty of the pin
-    fn set_duty(&mut self, duty: Self::Duty) {
-        self.set_timestamp(duty);
-    }
-}
-
-/// Implement no error type for the PwmPin because the method are infallible
-#[cfg(feature = "eh1")]
-impl<'d, Pin: OutputPin, PWM: PwmPeripheral, const OP: u8, const IS_A: bool>
-    embedded_hal_1::pwm::ErrorType for &mut PwmPin<'d, Pin, PWM, OP, IS_A>
-{
-    type Error = core::convert::Infallible;
-}
-
-/// Implement the trait SetDutyCycle for PwmPin
-#[cfg(feature = "eh1")]
-impl<'d, Pin: OutputPin, PWM: PwmPeripheral, const OP: u8, const IS_A: bool>
-    embedded_hal_1::pwm::SetDutyCycle for &mut PwmPin<'d, Pin, PWM, OP, IS_A>
-{
-    /// Get the max duty of the PwmPin
-    fn max_duty_cycle(&self) -> u16 {
-        self.get_period()
-    }
-
-    /// Set the max duty of the PwmPin
-    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), core::convert::Infallible> {
-        self.set_timestamp(duty);
-        Ok(())
-    }
-}
-
-/// An action the operator applies to an output
-#[non_exhaustive]
-#[repr(u32)]
-pub enum UpdateAction {
-    /// Clear the output by setting it to a low level.
-    SetLow  = 1,
-    /// Set the to a high level.
-    SetHigh = 2,
-    /// Change the current output level to the opposite value.
-    /// If it is currently pulled high, pull it low, or vice versa.
-    Toggle  = 3,
-}
-
-/// Settings for what actions should be taken on timing events
-///
-/// ### Note:
-/// The hardware supports using a timestamp A event to trigger an action on
-/// output B or vice versa. For clearer ownership semantics this HAL does not
-/// support such configurations.
-pub struct PwmActions<const IS_A: bool>(u32);
-
-impl<const IS_A: bool> PwmActions<IS_A> {
-    /// Using this setting together with a timer configured with
-    /// [`PwmWorkingMode::Increase`](super::timer::PwmWorkingMode::Increase)
-    /// will set the output high for a duration proportional to the set
-    /// timestamp.
-    pub const UP_ACTIVE_HIGH: Self = Self::empty()
-        .on_up_counting_timer_equals_zero(UpdateAction::SetHigh)
-        .on_up_counting_timer_equals_timestamp(UpdateAction::SetLow);
-
-    /// Using this setting together with a timer configured with
-    /// [`PwmWorkingMode::UpDown`](super::timer::PwmWorkingMode::UpDown) will
-    /// set the output high for a duration proportional to the set
-    /// timestamp.
-    pub const UP_DOWN_ACTIVE_HIGH: Self = Self::empty()
-        .on_down_counting_timer_equals_timestamp(UpdateAction::SetHigh)
-        .on_up_counting_timer_equals_timestamp(UpdateAction::SetLow);
-
-    /// `PwmActions` with no `UpdateAction`s set
-    pub const fn empty() -> Self {
-        PwmActions(0)
-    }
-
-    /// Choose an `UpdateAction` for an `UTEZ` event
-    pub const fn on_up_counting_timer_equals_zero(self, action: UpdateAction) -> Self {
-        self.with_value_at_offset(action as u32, 0)
-    }
-
-    /// Choose an `UpdateAction` for an `UTEP` event
-    pub const fn on_up_counting_timer_equals_period(self, action: UpdateAction) -> Self {
-        self.with_value_at_offset(action as u32, 2)
-    }
-
-    /// Choose an `UpdateAction` for an `UTEA`/`UTEB` event
-    pub const fn on_up_counting_timer_equals_timestamp(self, action: UpdateAction) -> Self {
-        match IS_A {
-            true => self.with_value_at_offset(action as u32, 4),
-            false => self.with_value_at_offset(action as u32, 6),
-        }
-    }
-
-    /// Choose an `UpdateAction` for an `UTEA`/`UTEB` event where you can
-    /// specify which of the A/B to use
-    pub const fn on_up_counting_timer_equals_ch_timestamp<const CH_A: bool>(
-        self,
-        action: UpdateAction,
-    ) -> Self {
-        match CH_A {
-            true => self.with_value_at_offset(action as u32, 4),
-            false => self.with_value_at_offset(action as u32, 6),
-        }
-    }
-
-    /// Choose an `UpdateAction` for an `DTEZ` event
-    pub const fn on_down_counting_timer_equals_zero(self, action: UpdateAction) -> Self {
-        self.with_value_at_offset(action as u32, 12)
-    }
-
-    /// Choose an `UpdateAction` for an `DTEP` event
-    pub const fn on_down_counting_timer_equals_period(self, action: UpdateAction) -> Self {
-        self.with_value_at_offset(action as u32, 14)
-    }
-
-    /// Choose an `UpdateAction` for an `DTEA`/`DTEB` event
-    pub const fn on_down_counting_timer_equals_timestamp(self, action: UpdateAction) -> Self {
-        match IS_A {
-            true => self.with_value_at_offset(action as u32, 16),
-            false => self.with_value_at_offset(action as u32, 18),
-        }
-    }
-
-    /// Choose an `UpdateAction` for an `DTEA`/`DTEB` event where you can
-    /// specify which of the A/B to use
-    pub const fn on_down_counting_timer_equals_ch_timestamp<const CH_A: bool>(
-        self,
-        action: UpdateAction,
-    ) -> Self {
-        match CH_A {
-            true => self.with_value_at_offset(action as u32, 16),
-            false => self.with_value_at_offset(action as u32, 18),
-        }
-    }
-
-    const fn with_value_at_offset(self, value: u32, offset: u32) -> Self {
-        let mask = !(0b11 << offset);
-        let value = (self.0 & mask) | (value << offset);
-        PwmActions(value)
-    }
-}
-
-/// Settings for when [`PwmPin::set_timestamp`] takes effect
-///
-/// Multiple syncing triggers can be set.
-pub struct PwmUpdateMethod(u8);
-
-impl PwmUpdateMethod {
-    /// New timestamp will be applied immediately
-    pub const SYNC_IMMEDIATLY: Self = Self::empty();
-    /// New timestamp will be applied when timer is equal to zero
-    pub const SYNC_ON_ZERO: Self = Self::empty().sync_on_timer_equals_zero();
-    /// New timestamp will be applied when timer is equal to period
-    pub const SYNC_ON_PERIOD: Self = Self::empty().sync_on_timer_equals_period();
-
-    /// `PwmUpdateMethod` with no sync triggers.
-    /// Corresponds to syncing immediately
-    pub const fn empty() -> Self {
-        PwmUpdateMethod(0)
-    }
-
-    /// Enable syncing new timestamp values when timer is equal to zero
-    pub const fn sync_on_timer_equals_zero(mut self) -> Self {
-        self.0 |= 0b0001;
-        self
-    }
-
-    /// Enable syncing new timestamp values when timer is equal to period
-    pub const fn sync_on_timer_equals_period(mut self) -> Self {
-        self.0 |= 0b0010;
-        self
-    }
-}

esp-hal-common/src/otg_fs.rs

@@ -1,142 +0,0 @@
-//! # USB OTG full-speed peripheral
-//!
-//! ## Overview
-//! The USB OTG Full-speed peripheral driver provides support for the USB
-//! On-The-Go (OTG) full-speed functionality on ESP chips, allows communication
-//! with USB devices.
-//!
-//! The driver uses the `esp_synopsys_usb_otg` crate, which provides the `USB
-//! bus` implementation and `USB peripheral traits`. It also relies on other
-//! peripheral modules, such as `GPIO`, `system`, and `clock control`, to
-//! configure and enable the `USB` peripheral.
-//!
-//! To use the USB OTG Full-speed peripheral driver, you need to initialize the
-//! peripheral and configure its settings. The USB struct represents the USB
-//! peripheral and requires the implementation of the `UsbSel`, `UsbDp`, and
-//! `UsbDm` traits, which define the specific types used for USB pin selection
-//! and data pins.
-//!
-//! The USB struct provides a `new` function for initialization.
-//! Inside the `new` function, the `into_ref!` macro is used to convert the
-//! peripheral references into `PeripheralRef` instances.
-//!
-//! The `USB` struct implements the `UsbPeripheral` trait from the
-//! `esp_synopsys_usb_otg` crate, which defines the required constants and
-//! functions for `USB peripheral` operation. The trait implementation includes
-//! enabling the `USB peripheral`, configuring the `USB` settings and connecting
-//! the appropriate `GPIO` pins to the `USB peripheral`.
-
-pub use esp_synopsys_usb_otg::UsbBus;
-use esp_synopsys_usb_otg::UsbPeripheral;
-
-use crate::{
-    gpio::InputSignal,
-    peripheral::{Peripheral, PeripheralRef},
-    peripherals,
-    system::{Peripheral as PeripheralEnable, PeripheralClockControl},
-};
-
-#[doc(hidden)]
-pub trait UsbDp {}
-
-#[doc(hidden)]
-pub trait UsbDm {}
-
-pub struct USB<'d, P, M>
-where
-    P: UsbDp + Send + Sync,
-    M: UsbDm + Send + Sync,
-{
-    _usb0: PeripheralRef<'d, peripherals::USB0>,
-    _usb_dp: PeripheralRef<'d, P>,
-    _usb_dm: PeripheralRef<'d, M>,
-}
-
-impl<'d, P, M> USB<'d, P, M>
-where
-    P: UsbDp + Send + Sync,
-    M: UsbDm + Send + Sync,
-{
-    pub fn new(
-        usb0: impl Peripheral<P = peripherals::USB0> + 'd,
-        usb_dp: impl Peripheral<P = P> + 'd,
-        usb_dm: impl Peripheral<P = M> + 'd,
-    ) -> Self {
-        crate::into_ref!(usb_dp, usb_dm);
-
-        PeripheralClockControl::enable(PeripheralEnable::Usb);
-
-        Self {
-            _usb0: usb0.into_ref(),
-            _usb_dp: usb_dp,
-            _usb_dm: usb_dm,
-        }
-    }
-}
-
-unsafe impl<'d, P, M> Sync for USB<'d, P, M>
-where
-    P: UsbDp + Send + Sync,
-    M: UsbDm + Send + Sync,
-{
-}
-
-unsafe impl<'d, P, M> UsbPeripheral for USB<'d, P, M>
-where
-    P: UsbDp + Send + Sync,
-    M: UsbDm + Send + Sync,
-{
-    const REGISTERS: *const () = peripherals::USB0::ptr() as *const ();
-
-    const HIGH_SPEED: bool = false;
-    const FIFO_DEPTH_WORDS: usize = 256;
-    const ENDPOINT_COUNT: usize = 5;
-
-    fn enable() {
-        unsafe {
-            let usb_wrap = &*peripherals::USB_WRAP::PTR;
-            usb_wrap.otg_conf().modify(|_, w| {
-                w.usb_pad_enable()
-                    .set_bit()
-                    .phy_sel()
-                    .clear_bit()
-                    .clk_en()
-                    .set_bit()
-                    .ahb_clk_force_on()
-                    .set_bit()
-                    .phy_clk_force_on()
-                    .set_bit()
-            });
-
-            #[cfg(esp32s3)]
-            {
-                let rtc = &*peripherals::RTC_CNTL::PTR;
-                rtc.usb_conf()
-                    .modify(|_, w| w.sw_hw_usb_phy_sel().set_bit().sw_usb_phy_sel().set_bit());
-            }
-
-            crate::gpio::connect_high_to_peripheral(InputSignal::USB_OTG_IDDIG); // connected connector is mini-B side
-            crate::gpio::connect_high_to_peripheral(InputSignal::USB_SRP_BVALID); // HIGH to force USB device mode
-            crate::gpio::connect_high_to_peripheral(InputSignal::USB_OTG_VBUSVALID); // receiving a valid Vbus from device
-            crate::gpio::connect_low_to_peripheral(InputSignal::USB_OTG_AVALID);
-
-            usb_wrap.otg_conf().modify(|_, w| {
-                w.pad_pull_override()
-                    .set_bit()
-                    .dp_pullup()
-                    .set_bit()
-                    .dp_pulldown()
-                    .clear_bit()
-                    .dm_pullup()
-                    .clear_bit()
-                    .dm_pulldown()
-                    .clear_bit()
-            });
-        }
-    }
-
-    fn ahb_frequency_hz(&self) -> u32 {
-        // unused
-        80_000_000
-    }
-}

esp-hal-common/src/pcnt/channel.rs

@@ -1,254 +0,0 @@
-//! # PCNT - channel configuration
-//!
-//! ## Overview
-//! The `channel` module is part of the `PCNT` peripheral driver
-//! for `ESP` chips.
-//!
-//! It provides a convenient and efficient way to configure and use
-//! individual channels of the `PCNT` peripheral of pulse counting and signal
-//! edge detection on ESP chips.
-
-use super::unit;
-use crate::{
-    gpio::{InputPin, InputSignal, ONE_INPUT, ZERO_INPUT},
-    peripheral::Peripheral,
-    peripherals::GPIO,
-};
-
-/// Channel number
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-pub enum Number {
-    Channel0,
-    Channel1,
-}
-
-/// PCNT channel action on signal edge
-#[derive(Debug, Copy, Clone, Default)]
-pub enum EdgeMode {
-    /// Hold current count value
-    Hold      = 0,
-    /// Increase count value
-    #[default]
-    Increment = 1,
-    /// Decrease count value
-    Decrement = 2,
-}
-
-/// PCNT channel action on control level
-#[derive(Debug, Copy, Clone, Default)]
-pub enum CtrlMode {
-    /// Keep current count mode
-    Keep    = 0,
-    /// Invert current count mode (increase -> decrease, decrease -> increase)
-    #[default]
-    Reverse = 1,
-    /// Hold current count value
-    Disable = 2,
-}
-
-/// Pulse Counter configuration for a single channel
-#[derive(Debug, Copy, Clone, Default)]
-pub struct Config {
-    /// PCNT low control mode
-    pub lctrl_mode: CtrlMode,
-    /// PCNT high control mode
-    pub hctrl_mode: CtrlMode,
-    /// PCNT signal positive edge count mode
-    pub pos_edge: EdgeMode,
-    /// PCNT signal negative edge count mode
-    pub neg_edge: EdgeMode,
-    pub invert_ctrl: bool,
-    pub invert_sig: bool,
-}
-
-/// PcntPin can be always high, always low, or an actual pin
-#[derive(Clone, Copy)]
-pub struct PcntSource {
-    source: u8,
-}
-
-impl PcntSource {
-    pub fn from_pin<'a, P: InputPin>(pin: impl Peripheral<P = P> + 'a) -> Self {
-        crate::into_ref!(pin);
-        Self {
-            source: pin.number(),
-        }
-    }
-    pub fn always_high() -> Self {
-        Self { source: ONE_INPUT }
-    }
-    pub fn always_low() -> Self {
-        Self { source: ZERO_INPUT }
-    }
-}
-
-pub struct Channel {
-    unit: unit::Number,
-    channel: Number,
-}
-
-impl Channel {
-    /// return a new Channel
-    pub(super) fn new(unit: unit::Number, channel: Number) -> Self {
-        Self { unit, channel }
-    }
-
-    /// Configure the channel
-    pub fn configure(&mut self, ctrl_signal: PcntSource, edge_signal: PcntSource, config: Config) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        let conf0 = match self.unit {
-            unit::Number::Unit0 => pcnt.u0_conf0(),
-            unit::Number::Unit1 => pcnt.u1_conf0(),
-            unit::Number::Unit2 => pcnt.u2_conf0(),
-            unit::Number::Unit3 => pcnt.u3_conf0(),
-            #[cfg(esp32)]
-            unit::Number::Unit4 => pcnt.u4_conf0(),
-            #[cfg(esp32)]
-            unit::Number::Unit5 => pcnt.u5_conf0(),
-            #[cfg(esp32)]
-            unit::Number::Unit6 => pcnt.u6_conf0(),
-            #[cfg(esp32)]
-            unit::Number::Unit7 => pcnt.u7_conf0(),
-        };
-        match self.channel {
-            Number::Channel0 => {
-                conf0.modify(|_, w| unsafe {
-                    w.ch0_hctrl_mode()
-                        .bits(config.hctrl_mode as u8)
-                        .ch0_lctrl_mode()
-                        .bits(config.lctrl_mode as u8)
-                        .ch0_neg_mode()
-                        .bits(config.neg_edge as u8)
-                        .ch0_pos_mode()
-                        .bits(config.pos_edge as u8)
-                });
-            }
-            Number::Channel1 => {
-                conf0.modify(|_, w| unsafe {
-                    w.ch1_hctrl_mode()
-                        .bits(config.hctrl_mode as u8)
-                        .ch1_lctrl_mode()
-                        .bits(config.lctrl_mode as u8)
-                        .ch1_neg_mode()
-                        .bits(config.neg_edge as u8)
-                        .ch1_pos_mode()
-                        .bits(config.pos_edge as u8)
-                });
-            }
-        }
-        self.set_ctrl_signal(ctrl_signal, config.invert_ctrl);
-        self.set_edge_signal(edge_signal, config.invert_sig);
-    }
-
-    /// Set the control signal (pin/high/low) for this channel
-    pub fn set_ctrl_signal(&self, source: PcntSource, invert: bool) -> &Self {
-        let signal = match self.unit {
-            unit::Number::Unit0 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT0_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT0_CTRL_CH1,
-            },
-            unit::Number::Unit1 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT1_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT1_CTRL_CH1,
-            },
-            unit::Number::Unit2 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT2_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT2_CTRL_CH1,
-            },
-            unit::Number::Unit3 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT3_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT3_CTRL_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit4 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT4_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT4_CTRL_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit5 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT5_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT5_CTRL_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit6 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT6_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT6_CTRL_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit7 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT7_CTRL_CH0,
-                Number::Channel1 => InputSignal::PCNT7_CTRL_CH1,
-            },
-        };
-
-        if (signal as usize) <= crate::gpio::INPUT_SIGNAL_MAX as usize {
-            unsafe { &*GPIO::PTR }
-                .func_in_sel_cfg(signal as usize)
-                .modify(|_, w| unsafe {
-                    w.sel()
-                        .set_bit()
-                        .in_inv_sel()
-                        .bit(invert)
-                        .in_sel()
-                        .bits(source.source)
-                });
-        }
-        self
-    }
-
-    /// Set the edge signal (pin/high/low) for this channel
-    pub fn set_edge_signal(&self, source: PcntSource, invert: bool) -> &Self {
-        let signal = match self.unit {
-            unit::Number::Unit0 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT0_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT0_SIG_CH1,
-            },
-            unit::Number::Unit1 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT1_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT1_SIG_CH1,
-            },
-            unit::Number::Unit2 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT2_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT2_SIG_CH1,
-            },
-            unit::Number::Unit3 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT3_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT3_SIG_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit4 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT4_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT4_SIG_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit5 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT5_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT5_SIG_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit6 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT6_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT6_SIG_CH1,
-            },
-            #[cfg(esp32)]
-            unit::Number::Unit7 => match self.channel {
-                Number::Channel0 => InputSignal::PCNT7_SIG_CH0,
-                Number::Channel1 => InputSignal::PCNT7_SIG_CH1,
-            },
-        };
-
-        if (signal as usize) <= crate::gpio::INPUT_SIGNAL_MAX as usize {
-            unsafe { &*GPIO::PTR }
-                .func_in_sel_cfg(signal as usize)
-                .modify(|_, w| unsafe {
-                    w.sel()
-                        .set_bit()
-                        .in_inv_sel()
-                        .bit(invert)
-                        .in_sel()
-                        .bits(source.source)
-                });
-        }
-        self
-    }
-}

esp-hal-common/src/pcnt/mod.rs

@@ -1,162 +0,0 @@
-//! # Pulse Counter peripheral driver
-//!
-//! ## Overview
-//! The `PCNT (Pulse Counter)` driver for `ESP` chips is a software component
-//! that provides an interface for controlling and utilizing the `PCNT`
-//! peripheral. The `PCNT` peripheral is a hardware module available in `ESP`
-//! chips, which functions as a pulse counter and encoder. It is capable of
-//! counting pulses and monitoring changes in signal levels from external
-//! sources.
-//!
-//! The `PCNT` driver is designed to offer convenient and efficient access to
-//! the functionalities of the `PCNT` peripheral. It consists of two main
-//! modules:
-//!    * [channel]
-//!    * [unit]
-//!
-//! The `channel` module allows users to configure and manage individual
-//! channels of the `PCNT` peripheral. It provides methods to set various
-//! parameters for each channel, such as control modes for signal edges, action
-//! on control level, and configurations for positive and negative edge count
-//! modes.
-//!
-//! The `unit` module is responsible for configuring and handling individual
-//! units of the `PCNT` peripheral. Each unit represents a separate instance of
-//! the `PCNT` module, identified by unit numbers like `Unit0`, `Unit1`, and so
-//! on. Users can interact with these units to configure settings such as low
-//! and high limits, thresholds, and optional filtering. The unit module also
-//! enables users to pause, resume, and clear the counter, as well as enable or
-//! disable interrupts for specific events associated with the unit.
-//!
-//! ## Example
-//! ```no_run
-//! let unit_number = unit::Number::Unit1;
-//!
-//! // setup a pulse couter
-//! println!("setup pulse counter unit 0");
-//! let pcnt = PCNT::new(peripherals.PCNT);
-//! let mut u0 = pcnt.get_unit(unit_number);
-//! u0.configure(unit::Config {
-//!     low_limit: -100,
-//!     high_limit: 100,
-//!     filter: Some(min(10u16 * 80, 1023u16)),
-//!     ..Default::default()
-//! })
-//! .unwrap();
-//!
-//! println!("setup channel 0");
-//! let mut ch0 = u0.get_channel(channel::Number::Channel0);
-//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
-//! let mut pin_a = io.pins.gpio5.into_pull_up_input();
-//! let mut pin_b = io.pins.gpio6.into_pull_up_input();
-//!
-//! ch0.configure(
-//!     PcntSource::from_pin(&mut pin_a),
-//!     PcntSource::from_pin(&mut pin_b),
-//!     channel::Config {
-//!         lctrl_mode: channel::CtrlMode::Reverse,
-//!         hctrl_mode: channel::CtrlMode::Keep,
-//!         pos_edge: channel::EdgeMode::Decrement,
-//!         neg_edge: channel::EdgeMode::Increment,
-//!         invert_ctrl: false,
-//!         invert_sig: false,
-//!     },
-//! );
-//!
-//! println!("setup channel 1");
-//! let mut ch1 = u0.get_channel(channel::Number::Channel1);
-//! ch1.configure(
-//!     PcntSource::from_pin(&mut pin_b),
-//!     PcntSource::from_pin(&mut pin_a),
-//!     channel::Config {
-//!         lctrl_mode: channel::CtrlMode::Reverse,
-//!         hctrl_mode: channel::CtrlMode::Keep,
-//!         pos_edge: channel::EdgeMode::Increment,
-//!         neg_edge: channel::EdgeMode::Decrement,
-//!         invert_ctrl: false,
-//!         invert_sig: false,
-//!     },
-//! );
-//! println!("subscribing to events");
-//! u0.events(unit::Events {
-//!     low_limit: true,
-//!     high_limit: true,
-//!     thresh0: false,
-//!     thresh1: false,
-//!     zero: false,
-//! });
-//!
-//! println!("enabling interrupts");
-//! u0.listen();
-//! println!("resume pulse counter unit 0");
-//! u0.resume();
-//!
-//! critical_section::with(|cs| UNIT0.borrow_ref_mut(cs).replace(u0));
-//!
-//! interrupt::enable(peripherals::Interrupt::PCNT, interrupt::Priority::Priority2).unwrap();
-//!
-//! let mut last_value: i32 = 0;
-//! loop {
-//!     critical_section::with(|cs| {
-//!         let mut u0 = UNIT0.borrow_ref_mut(cs);
-//!         let u0 = u0.as_mut().unwrap();
-//!         let value: i32 = u0.get_value() as i32 + VALUE.load(Ordering::SeqCst);
-//!         if value != last_value {
-//!             println!("value: {value}");
-//!             last_value = value;
-//!         }
-//!     });
-//! }
-//! ```
-//!
-//! Where the `PCNT` interrupt handler is defined as:
-//! ```no_run
-//! #[interrupt]
-//! fn PCNT() {
-//!     critical_section::with(|cs| {
-//!         let mut u0 = UNIT0.borrow_ref_mut(cs);
-//!         let u0 = u0.as_mut().unwrap();
-//!         if u0.interrupt_set() {
-//!             let events = u0.get_events();
-//!             if events.high_limit {
-//!                 VALUE.fetch_add(100, Ordering::SeqCst);
-//!             } else if events.low_limit {
-//!                 VALUE.fetch_add(-100, Ordering::SeqCst);
-//!             }
-//!             u0.reset_interrupt();
-//!         }
-//!     });
-//! }
-//! ```
-//!
-//! [channel]: channel/index.html
-//! [unit]: unit/index.html
-
-use self::unit::Unit;
-use crate::{
-    peripheral::{Peripheral, PeripheralRef},
-    system::PeripheralClockControl,
-};
-
-pub mod channel;
-pub mod unit;
-
-pub struct PCNT<'d> {
-    _instance: PeripheralRef<'d, crate::peripherals::PCNT>,
-}
-
-impl<'d> PCNT<'d> {
-    /// Return a new PCNT
-    pub fn new(_instance: impl Peripheral<P = crate::peripherals::PCNT> + 'd) -> Self {
-        crate::into_ref!(_instance);
-        // Enable the PCNT peripherals clock in the system peripheral
-        PeripheralClockControl::enable(crate::system::Peripheral::Pcnt);
-
-        PCNT { _instance }
-    }
-
-    /// Return a unit
-    pub fn get_unit(&self, number: unit::Number) -> Unit {
-        Unit::new(number)
-    }
-}

esp-hal-common/src/pcnt/unit.rs

@@ -1,408 +0,0 @@
-//! # PCNT - Unit module
-//!
-//! ## Overview
-//! The `unit` module is a part of the `PCNT` peripheral driver
-//! for ESP chips. It offers functionalities for configuring and utilizing
-//! specific units of the PCNT peripheral.
-//!
-//! Each unit is identified by a unit number, such as `Unit0`, `Unit1`, `Unit2`,
-//! and so on. This module provides methods to configure a unit with specific
-//! settings, like low and high limits, thresholds, and optional filtering.
-//! Users can easily configure these units based on their requirements.
-
-use critical_section::CriticalSection;
-
-use super::channel;
-
-/// Unit number
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-pub enum Number {
-    Unit0,
-    Unit1,
-    Unit2,
-    Unit3,
-    #[cfg(esp32)]
-    Unit4,
-    #[cfg(esp32)]
-    Unit5,
-    #[cfg(esp32)]
-    Unit6,
-    #[cfg(esp32)]
-    Unit7,
-}
-
-/// Unit errors
-#[derive(Debug, Clone, Copy, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Error {
-    /// Invalid filter threshold value
-    InvalidFilterThresh,
-    /// Invalid low limit - must be < 0
-    InvalidLowLimit,
-    /// Invalid high limit - must be > 0
-    InvalidHighLimit,
-}
-
-/// the current status of the counter.
-#[derive(Copy, Clone, Debug, Default, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum ZeroMode {
-    /// pulse counter decreases from positive to 0.
-    #[default]
-    PosZero  = 0,
-    /// pulse counter increases from negative to 0
-    NegZero  = 1,
-    /// pulse counter is negative (not implemented?)
-    Negitive = 2,
-    /// pulse counter is positive (not implemented?)
-    Positive = 3,
-}
-
-impl From<u8> for ZeroMode {
-    fn from(value: u8) -> Self {
-        match value {
-            0 => Self::PosZero,
-            1 => Self::NegZero,
-            2 => Self::Negitive,
-            3 => Self::Positive,
-            _ => unreachable!(), // TODO: is this good enoough?  should we use some default?
-        }
-    }
-}
-
-// Events
-#[derive(Copy, Clone, Debug, Default)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct Events {
-    pub low_limit: bool,
-    pub high_limit: bool,
-    pub thresh0: bool,
-    pub thresh1: bool,
-    pub zero: bool,
-}
-
-/// Unit configuration
-#[derive(Copy, Clone, Default)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct Config {
-    pub low_limit: i16,
-    pub high_limit: i16,
-    pub thresh0: i16,
-    pub thresh1: i16,
-    pub filter: Option<u16>,
-}
-
-pub struct Unit {
-    number: Number,
-}
-
-impl Unit {
-    /// return a new Unit
-    pub(super) fn new(number: Number) -> Self {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        let conf0 = match number {
-            Number::Unit0 => pcnt.u0_conf0(),
-            Number::Unit1 => pcnt.u1_conf0(),
-            Number::Unit2 => pcnt.u2_conf0(),
-            Number::Unit3 => pcnt.u3_conf0(),
-            #[cfg(esp32)]
-            Number::Unit4 => pcnt.u4_conf0(),
-            #[cfg(esp32)]
-            Number::Unit5 => pcnt.u5_conf0(),
-            #[cfg(esp32)]
-            Number::Unit6 => pcnt.u6_conf0(),
-            #[cfg(esp32)]
-            Number::Unit7 => pcnt.u7_conf0(),
-        };
-        // disable filter and all events
-        conf0.modify(|_, w| unsafe {
-            w.filter_en()
-                .clear_bit()
-                .filter_thres()
-                .bits(0)
-                .thr_l_lim_en()
-                .clear_bit()
-                .thr_h_lim_en()
-                .clear_bit()
-                .thr_thres0_en()
-                .clear_bit()
-                .thr_thres1_en()
-                .clear_bit()
-                .thr_zero_en()
-                .clear_bit()
-        });
-        Self { number }
-    }
-
-    pub fn configure(&mut self, config: Config) -> Result<(), Error> {
-        // low limit must be >= or the limit is -32768 and when thats
-        // hit the event status claims it was the high limit.
-        // tested on an esp32s3
-        if config.low_limit >= 0 {
-            return Err(Error::InvalidLowLimit);
-        }
-        if config.high_limit <= 0 {
-            return Err(Error::InvalidHighLimit);
-        }
-        let (filter_en, filter) = match config.filter {
-            Some(filter) => (true, filter),
-            None => (false, 0),
-        };
-        // filter must be less than 1024
-        if filter > 1023 {
-            return Err(Error::InvalidFilterThresh);
-        }
-
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        let (conf0, conf1, conf2) = match self.number {
-            Number::Unit0 => (pcnt.u0_conf0(), pcnt.u0_conf1(), pcnt.u0_conf2()),
-            Number::Unit1 => (pcnt.u1_conf0(), pcnt.u1_conf1(), pcnt.u1_conf2()),
-            Number::Unit2 => (pcnt.u2_conf0(), pcnt.u2_conf1(), pcnt.u2_conf2()),
-            Number::Unit3 => (pcnt.u3_conf0(), pcnt.u3_conf1(), pcnt.u3_conf2()),
-            #[cfg(esp32)]
-            Number::Unit4 => (pcnt.u4_conf0(), pcnt.u4_conf1(), pcnt.u4_conf2()),
-            #[cfg(esp32)]
-            Number::Unit5 => (pcnt.u5_conf0(), pcnt.u5_conf1(), pcnt.u5_conf2()),
-            #[cfg(esp32)]
-            Number::Unit6 => (pcnt.u6_conf0(), pcnt.u6_conf1(), pcnt.u6_conf2()),
-            #[cfg(esp32)]
-            Number::Unit7 => (pcnt.u7_conf0(), pcnt.u7_conf1(), pcnt.u7_conf2()),
-        };
-        conf2.write(|w| unsafe {
-            w.cnt_l_lim()
-                .bits(config.low_limit as u16)
-                .cnt_h_lim()
-                .bits(config.high_limit as u16)
-        });
-        conf1.write(|w| unsafe {
-            w.cnt_thres0()
-                .bits(config.thresh0 as u16)
-                .cnt_thres1()
-                .bits(config.thresh1 as u16)
-        });
-        conf0.modify(|_, w| unsafe { w.filter_thres().bits(filter).filter_en().bit(filter_en) });
-        self.pause();
-        self.clear();
-        Ok(())
-    }
-
-    pub fn get_channel(&self, number: channel::Number) -> super::channel::Channel {
-        super::channel::Channel::new(self.number, number)
-    }
-
-    pub fn clear(&self) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        critical_section::with(|_cs| {
-            match self.number {
-                Number::Unit0 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u0().set_bit()),
-                Number::Unit1 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u1().set_bit()),
-                Number::Unit2 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u2().set_bit()),
-                Number::Unit3 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u3().set_bit()),
-                #[cfg(esp32)]
-                Number::Unit4 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u4().set_bit()),
-                #[cfg(esp32)]
-                Number::Unit5 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u5().set_bit()),
-                #[cfg(esp32)]
-                Number::Unit6 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u6().set_bit()),
-                #[cfg(esp32)]
-                Number::Unit7 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u7().set_bit()),
-            }
-            // TODO: does this need a delay? (liebman / Jan 2 2023)
-            match self.number {
-                Number::Unit0 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u0().clear_bit()),
-                Number::Unit1 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u1().clear_bit()),
-                Number::Unit2 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u2().clear_bit()),
-                Number::Unit3 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u3().clear_bit()),
-                #[cfg(esp32)]
-                Number::Unit4 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u4().clear_bit()),
-                #[cfg(esp32)]
-                Number::Unit5 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u5().clear_bit()),
-                #[cfg(esp32)]
-                Number::Unit6 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u6().clear_bit()),
-                #[cfg(esp32)]
-                Number::Unit7 => pcnt.ctrl().modify(|_, w| w.cnt_rst_u7().clear_bit()),
-            }
-        });
-    }
-
-    /// Pause the counter
-    pub fn pause(&self) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        critical_section::with(|_cs| match self.number {
-            Number::Unit0 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u0().set_bit()),
-            Number::Unit1 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u1().set_bit()),
-            Number::Unit2 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u2().set_bit()),
-            Number::Unit3 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u3().set_bit()),
-            #[cfg(esp32)]
-            Number::Unit4 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u4().set_bit()),
-            #[cfg(esp32)]
-            Number::Unit5 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u5().set_bit()),
-            #[cfg(esp32)]
-            Number::Unit6 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u6().set_bit()),
-            #[cfg(esp32)]
-            Number::Unit7 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u7().set_bit()),
-        });
-    }
-
-    /// Resume the counter
-    pub fn resume(&self) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        critical_section::with(|_cs| match self.number {
-            Number::Unit0 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u0().clear_bit()),
-            Number::Unit1 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u1().clear_bit()),
-            Number::Unit2 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u2().clear_bit()),
-            Number::Unit3 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u3().clear_bit()),
-            #[cfg(esp32)]
-            Number::Unit4 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u4().clear_bit()),
-            #[cfg(esp32)]
-            Number::Unit5 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u5().clear_bit()),
-            #[cfg(esp32)]
-            Number::Unit6 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u6().clear_bit()),
-            #[cfg(esp32)]
-            Number::Unit7 => pcnt.ctrl().modify(|_, w| w.cnt_pause_u7().clear_bit()),
-        });
-    }
-
-    /// Enable which events generate interrupts on this unit.
-    pub fn events(&self, events: Events) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        let conf0 = match self.number {
-            Number::Unit0 => pcnt.u0_conf0(),
-            Number::Unit1 => pcnt.u1_conf0(),
-            Number::Unit2 => pcnt.u2_conf0(),
-            Number::Unit3 => pcnt.u3_conf0(),
-            #[cfg(esp32)]
-            Number::Unit4 => pcnt.u4_conf0(),
-            #[cfg(esp32)]
-            Number::Unit5 => pcnt.u5_conf0(),
-            #[cfg(esp32)]
-            Number::Unit6 => pcnt.u6_conf0(),
-            #[cfg(esp32)]
-            Number::Unit7 => pcnt.u7_conf0(),
-        };
-        conf0.modify(|_, w| {
-            w.thr_l_lim_en()
-                .bit(events.low_limit)
-                .thr_h_lim_en()
-                .bit(events.high_limit)
-                .thr_thres0_en()
-                .bit(events.thresh0)
-                .thr_thres1_en()
-                .bit(events.thresh1)
-                .thr_zero_en()
-                .bit(events.zero)
-        });
-    }
-
-    /// Get the latest events for this unit.
-    pub fn get_events(&self) -> Events {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        let status = pcnt.u_status(self.number as usize).read();
-
-        Events {
-            low_limit: status.l_lim().bit(),
-            high_limit: status.h_lim().bit(),
-            thresh0: status.thres0().bit(),
-            thresh1: status.thres1().bit(),
-            zero: status.zero().bit(),
-        }
-    }
-
-    /// Get the mode of the last zero crossing
-    pub fn get_zero_mode(&self) -> ZeroMode {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        pcnt.u_status(self.number as usize)
-            .read()
-            .zero_mode()
-            .bits()
-            .into()
-    }
-
-    /// Enable interrupts for this unit.
-    pub fn listen(&self) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        critical_section::with(|_cs| {
-            pcnt.int_ena().modify(|_, w| match self.number {
-                Number::Unit0 => w.cnt_thr_event_u0().set_bit(),
-                Number::Unit1 => w.cnt_thr_event_u1().set_bit(),
-                Number::Unit2 => w.cnt_thr_event_u2().set_bit(),
-                Number::Unit3 => w.cnt_thr_event_u3().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit4 => w.cnt_thr_event_u4().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit5 => w.cnt_thr_event_u5().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit6 => w.cnt_thr_event_u6().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit7 => w.cnt_thr_event_u7().set_bit(),
-            })
-        });
-    }
-
-    /// Disable interrupts for this unit.
-    pub fn unlisten(&self, _cs: CriticalSection) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        critical_section::with(|_cs| {
-            pcnt.int_ena().write(|w| match self.number {
-                Number::Unit0 => w.cnt_thr_event_u0().clear_bit(),
-                Number::Unit1 => w.cnt_thr_event_u1().clear_bit(),
-                Number::Unit2 => w.cnt_thr_event_u2().clear_bit(),
-                Number::Unit3 => w.cnt_thr_event_u3().clear_bit(),
-                #[cfg(esp32)]
-                Number::Unit4 => w.cnt_thr_event_u4().clear_bit(),
-                #[cfg(esp32)]
-                Number::Unit5 => w.cnt_thr_event_u5().clear_bit(),
-                #[cfg(esp32)]
-                Number::Unit6 => w.cnt_thr_event_u6().clear_bit(),
-                #[cfg(esp32)]
-                Number::Unit7 => w.cnt_thr_event_u7().clear_bit(),
-            })
-        });
-    }
-
-    /// Returns true if an interrupt is active for this unit.
-    pub fn interrupt_set(&self) -> bool {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        match self.number {
-            Number::Unit0 => pcnt.int_st().read().cnt_thr_event_u0().bit(),
-            Number::Unit1 => pcnt.int_st().read().cnt_thr_event_u1().bit(),
-            Number::Unit2 => pcnt.int_st().read().cnt_thr_event_u2().bit(),
-            Number::Unit3 => pcnt.int_st().read().cnt_thr_event_u3().bit(),
-            #[cfg(esp32)]
-            Number::Unit4 => pcnt.int_st().read().cnt_thr_event_u4().bit(),
-            #[cfg(esp32)]
-            Number::Unit5 => pcnt.int_st().read().cnt_thr_event_u5().bit(),
-            #[cfg(esp32)]
-            Number::Unit6 => pcnt.int_st().read().cnt_thr_event_u6().bit(),
-            #[cfg(esp32)]
-            Number::Unit7 => pcnt.int_st().read().cnt_thr_event_u7().bit(),
-        }
-    }
-
-    /// Clear the interrupt bit for this unit.
-    pub fn reset_interrupt(&self) {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        critical_section::with(|_cs| {
-            pcnt.int_clr().write(|w| match self.number {
-                Number::Unit0 => w.cnt_thr_event_u0().set_bit(),
-                Number::Unit1 => w.cnt_thr_event_u1().set_bit(),
-                Number::Unit2 => w.cnt_thr_event_u2().set_bit(),
-                Number::Unit3 => w.cnt_thr_event_u3().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit4 => w.cnt_thr_event_u4().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit5 => w.cnt_thr_event_u5().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit6 => w.cnt_thr_event_u6().set_bit(),
-                #[cfg(esp32)]
-                Number::Unit7 => w.cnt_thr_event_u7().set_bit(),
-            })
-        });
-    }
-
-    /// Get the current counter value.
-    pub fn get_value(&self) -> i16 {
-        let pcnt = unsafe { &*crate::peripherals::PCNT::ptr() };
-        pcnt.u_cnt(self.number as usize).read().cnt().bits() as i16
-    }
-}

esp-hal-common/src/peripheral.rs

@@ -1,387 +0,0 @@
-//! # Exclusive peripheral access
-//!
-//! ## Overview
-//! The Peripheral module provides an exclusive access mechanism to peripherals
-//! on ESP chips. It includes the `PeripheralRef` struct, which represents an
-//! exclusive reference to a peripheral. It offers memory efficiency benefits
-//! for zero-sized types.
-//!
-//! The `PeripheralRef` struct is used to access and interact with peripherals.
-//! It implements the `Deref` and `DerefMut` traits, allowing you to dereference
-//! it to access the underlying peripheral. It also provides methods for cloning
-//! and re-borrowing the peripheral.
-//!
-//! The module also defines the `Peripheral` trait, which is implemented by
-//! types that can be used as peripherals. The trait allows conversion between
-//! owned and borrowed peripherals and provides an unsafe method for cloning the
-//! peripheral. By implementing this trait, a type can be used with the
-//! `PeripheralRef` struct.
-//!
-//! The module also includes a `peripheral_macros` module, which contains macros
-//! for generating peripheral structs and associated traits based on
-//! configuration options.
-//!
-//! ## Examples
-//!
-//! ### Initialization
-//! ```no_run
-//! let peripherals = Peripherals::take();
-//! ```
-//! ### Accessing peripherals
-//! ```no_run
-//! let mut rtc = Rtc::new(peripherals.RTC_CNTL);
-//! ```
-//! ```no_run
-//! let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
-//! ```
-
-use core::{
-    marker::PhantomData,
-    ops::{Deref, DerefMut},
-};
-
-/// An exclusive reference to a peripheral.
-///
-/// This is functionally the same as a `&'a mut T`. The reason for having a
-/// dedicated struct is memory efficiency:
-///
-/// Peripheral singletons are typically either zero-sized (for concrete
-/// peripehrals like `PA9` or `Spi4`) or very small (for example `AnyPin` which
-/// is 1 byte). However `&mut T` is always 4 bytes for 32-bit targets, even if T
-/// is zero-sized. PeripheralRef stores a copy of `T` instead, so it's the same
-/// size.
-///
-/// but it is the size of `T` not the size
-/// of a pointer. This is useful if T is a zero sized type.
-pub struct PeripheralRef<'a, T> {
-    inner: T,
-    _lifetime: PhantomData<&'a mut T>,
-}
-
-impl<'a, T> PeripheralRef<'a, T> {
-    #[inline]
-    pub fn new(inner: T) -> Self {
-        Self {
-            inner,
-            _lifetime: PhantomData,
-        }
-    }
-
-    /// Unsafely clone (duplicate) a peripheral singleton.
-    ///
-    /// # Safety
-    ///
-    /// This returns an owned clone of the peripheral. You must manually ensure
-    /// only one copy of the peripheral is in use at a time. For example, don't
-    /// create two SPI drivers on `SPI1`, because they will "fight" each other.
-    ///
-    /// You should strongly prefer using `reborrow()` instead. It returns a
-    /// `PeripheralRef` that borrows `self`, which allows the borrow checker
-    /// to enforce this at compile time.
-    pub unsafe fn clone_unchecked(&mut self) -> PeripheralRef<'a, T>
-    where
-        T: Peripheral<P = T>,
-    {
-        PeripheralRef::new(self.inner.clone_unchecked())
-    }
-
-    /// Reborrow into a "child" PeripheralRef.
-    ///
-    /// `self` will stay borrowed until the child PeripheralRef is dropped.
-    pub fn reborrow(&mut self) -> PeripheralRef<'_, T>
-    where
-        T: Peripheral<P = T>,
-    {
-        // safety: we're returning the clone inside a new PeripheralRef that borrows
-        // self, so user code can't use both at the same time.
-        PeripheralRef::new(unsafe { self.inner.clone_unchecked() })
-    }
-
-    /// Map the inner peripheral using `Into`.
-    ///
-    /// This converts from `PeripheralRef<'a, T>` to `PeripheralRef<'a, U>`,
-    /// using an `Into` impl to convert from `T` to `U`.
-    ///
-    /// For example, this can be useful to degrade GPIO pins: converting from
-    /// PeripheralRef<'a, PB11>` to `PeripheralRef<'a, AnyPin>`.
-    #[inline]
-    pub fn map_into<U>(self) -> PeripheralRef<'a, U>
-    where
-        T: Into<U>,
-    {
-        PeripheralRef {
-            inner: self.inner.into(),
-            _lifetime: PhantomData,
-        }
-    }
-}
-
-impl<'a, T> Deref for PeripheralRef<'a, T> {
-    type Target = T;
-
-    #[inline]
-    fn deref(&self) -> &Self::Target {
-        &self.inner
-    }
-}
-
-impl<'a, T> DerefMut for PeripheralRef<'a, T> {
-    #[inline]
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.inner
-    }
-}
-
-/// Trait for any type that can be used as a peripheral of type `P`.
-///
-/// This is used in driver constructors, to allow passing either owned
-/// peripherals (e.g. `TWISPI0`), or borrowed peripherals (e.g. `&mut TWISPI0`).
-///
-/// For example, if you have a driver with a constructor like this:
-///
-/// ```ignore
-/// impl<'d, T: Instance> Twim<'d, T> {
-///     pub fn new(
-///         twim: impl Peripheral<P = T> + 'd,
-///         irq: impl Peripheral<P = T::Interrupt> + 'd,
-///         sda: impl Peripheral<P = impl GpioPin> + 'd,
-///         scl: impl Peripheral<P = impl GpioPin> + 'd,
-///         config: Config,
-///     ) -> Self { .. }
-/// }
-/// ```
-///
-/// You may call it with owned peripherals, which yields an instance that can
-/// live forever (`'static`):
-///
-/// ```ignore
-/// let mut twi: Twim<'static, ...> = Twim::new(p.TWISPI0, irq, p.P0_03, p.P0_04, config);
-/// ```
-///
-/// Or you may call it with borrowed peripherals, which yields an instance that
-/// can only live for as long as the borrows last:
-///
-/// ```ignore
-/// let mut twi: Twim<'_, ...> = Twim::new(&mut p.TWISPI0, &mut irq, &mut p.P0_03, &mut p.P0_04, config);
-/// ```
-///
-/// # Implementation details, for HAL authors
-///
-/// When writing a HAL, the intended way to use this trait is to take `impl
-/// Peripheral<P = ..>` in the HAL's public API (such as driver constructors),
-/// calling `.into_ref()` to obtain a `PeripheralRef`, and storing that in the
-/// driver struct.
-///
-/// `.into_ref()` on an owned `T` yields a `PeripheralRef<'static, T>`.
-/// `.into_ref()` on an `&'a mut T` yields a `PeripheralRef<'a, T>`.
-pub trait Peripheral: Sized + sealed::Sealed {
-    /// Peripheral singleton type
-    type P;
-
-    /// Unsafely clone (duplicate) a peripheral singleton.
-    ///
-    /// # Safety
-    ///
-    /// This returns an owned clone of the peripheral. You must manually ensure
-    /// only one copy of the peripheral is in use at a time. For example, don't
-    /// create two SPI drivers on `SPI1`, because they will "fight" each other.
-    ///
-    /// You should strongly prefer using `into_ref()` instead. It returns a
-    /// `PeripheralRef`, which allows the borrow checker to enforce this at
-    /// compile time.
-    unsafe fn clone_unchecked(&mut self) -> Self::P;
-
-    /// Convert a value into a `PeripheralRef`.
-    ///
-    /// When called on an owned `T`, yields a `PeripheralRef<'static, T>`.
-    /// When called on an `&'a mut T`, yields a `PeripheralRef<'a, T>`.
-    #[inline]
-    fn into_ref<'a>(mut self) -> PeripheralRef<'a, Self::P>
-    where
-        Self: 'a,
-    {
-        PeripheralRef::new(unsafe { self.clone_unchecked() })
-    }
-}
-
-impl<T> Peripheral for &mut T
-where
-    T: Peripheral<P = T>,
-{
-    type P = T;
-
-    unsafe fn clone_unchecked(&mut self) -> Self::P {
-        T::clone_unchecked(self)
-    }
-}
-
-impl<T> sealed::Sealed for &mut T where T: sealed::Sealed {}
-
-pub(crate) mod sealed {
-    pub trait Sealed {}
-}
-
-mod peripheral_macros {
-    #[doc(hidden)]
-    #[macro_export]
-    macro_rules! peripherals {
-        ($($(#[$cfg:meta])? $name:ident <= $from_pac:tt),*$(,)?) => {
-
-            /// Contains the generated peripherals which implement [`Peripheral`]
-            mod peripherals {
-                pub use super::pac::*;
-                $(
-                    crate::create_peripheral!($(#[$cfg])? $name <= $from_pac);
-                )*
-            }
-
-            #[allow(non_snake_case)]
-            pub struct Peripherals {
-                $(
-                    $(#[$cfg])?
-                    pub $name: peripherals::$name,
-                )*
-            }
-
-            impl Peripherals {
-                /// Returns all the peripherals *once*
-                #[inline]
-                pub fn take() -> Self {
-
-                    #[no_mangle]
-                    static mut _ESP_HAL_DEVICE_PERIPHERALS: bool = false;
-
-                    critical_section::with(|_| unsafe {
-                        if _ESP_HAL_DEVICE_PERIPHERALS {
-                            panic!("init called more than once!")
-                        }
-                        _ESP_HAL_DEVICE_PERIPHERALS = true;
-                        Self::steal()
-                    })
-                }
-            }
-
-            impl Peripherals {
-                /// Unsafely create an instance of this peripheral out of thin air.
-                ///
-                /// # Safety
-                ///
-                /// You must ensure that you're only using one instance of this type at a time.
-                #[inline]
-                pub unsafe fn steal() -> Self {
-                    Self {
-                        $(
-                            $(#[$cfg])?
-                            $name: peripherals::$name::steal(),
-                        )*
-                    }
-                }
-            }
-
-            // expose the new structs
-            $(
-                pub use peripherals::$name;
-            )*
-        }
-    }
-
-    #[doc(hidden)]
-    #[macro_export]
-    macro_rules! into_ref {
-        ($($name:ident),*) => {
-            $(
-                #[allow(unused_mut)]
-                let mut $name = $name.into_ref();
-            )*
-        }
-    }
-
-    #[doc(hidden)]
-    #[macro_export]
-    macro_rules! create_peripheral {
-        ($(#[$cfg:meta])? $name:ident <= virtual) => {
-            $(#[$cfg])?
-            #[derive(Debug)]
-            #[allow(non_camel_case_types)]
-            pub struct $name { _inner: () }
-
-            $(#[$cfg])?
-            impl $name {
-                /// Unsafely create an instance of this peripheral out of thin air.
-                ///
-                /// # Safety
-                ///
-                /// You must ensure that you're only using one instance of this type at a time.
-                #[inline]
-                pub unsafe fn steal() -> Self {
-                    Self { _inner: () }
-                }
-            }
-
-            impl crate::peripheral::Peripheral for $name {
-                type P = $name;
-
-                #[inline]
-                unsafe fn clone_unchecked(&mut self) -> Self::P {
-                    Self::steal()
-                }
-            }
-
-            impl crate::peripheral::sealed::Sealed for $name {}
-        };
-        ($(#[$cfg:meta])? $name:ident <= $base:ident) => {
-            $(#[$cfg])?
-            #[derive(Debug)]
-            #[allow(non_camel_case_types)]
-            pub struct $name { _inner: () }
-
-            $(#[$cfg])?
-            impl $name {
-                /// Unsafely create an instance of this peripheral out of thin air.
-                ///
-                /// # Safety
-                ///
-                /// You must ensure that you're only using one instance of this type at a time.
-                #[inline]
-                pub unsafe fn steal() -> Self {
-                    Self { _inner: () }
-                }
-
-                #[doc = r"Pointer to the register block"]
-                pub const PTR: *const <super::pac::$base as core::ops::Deref>::Target = super::pac::$base::PTR;
-
-                #[doc = r"Return the pointer to the register block"]
-                #[inline(always)]
-                pub const fn ptr() -> *const <super::pac::$base as core::ops::Deref>::Target {
-                    super::pac::$base::PTR
-                }
-            }
-
-            impl core::ops::Deref for $name {
-                type Target = <super::pac::$base as core::ops::Deref>::Target;
-
-                fn deref(&self) -> &Self::Target {
-                    unsafe { &*Self::PTR }
-                }
-            }
-
-            impl core::ops::DerefMut for $name {
-
-                fn deref_mut(&mut self) -> &mut Self::Target {
-                    unsafe { &mut *(Self::PTR as *mut _)  }
-                }
-            }
-
-            impl crate::peripheral::Peripheral for $name {
-                type P = $name;
-
-                #[inline]
-                unsafe fn clone_unchecked(&mut self) -> Self::P {
-                    Self::steal()
-                }
-            }
-
-            impl crate::peripheral::sealed::Sealed for $name {}
-        };
-    }
-}

esp-hal-common/src/prelude.rs

@@ -1,62 +0,0 @@
-//! The prelude
-//!
-//! Re-exports all traits required for interacting with the various peripheral
-//! drivers implemented in this crate.
-
-pub use embedded_dma::{
-    ReadBuffer as _embedded_dma_ReadBuffer,
-    ReadTarget as _embedded_dma_ReadTarget,
-    Word as _embedded_dma_Word,
-    WriteBuffer as _embedded_dma_WriteBuffer,
-    WriteTarget as _embedded_dma_WriteTarget,
-};
-pub use embedded_hal::{
-    digital::v2::{
-        InputPin as _embedded_hal_digital_v2_InputPin,
-        OutputPin as _embedded_hal_digital_v2_OutputPin,
-        StatefulOutputPin as _embedded_hal_digital_v2_StatefulOutputPin,
-        ToggleableOutputPin as _embedded_hal_digital_v2_ToggleableOutputPin,
-    },
-    prelude::*,
-};
-pub use fugit::{
-    ExtU32 as _fugit_ExtU32,
-    ExtU64 as _fugit_ExtU64,
-    RateExtU32 as _fugit_RateExtU32,
-    RateExtU64 as _fugit_RateExtU64,
-};
-pub use nb;
-
-#[cfg(any(apb_saradc, sens))]
-pub use crate::analog::AnalogExt as _esp_hal_analog_AnalogExt;
-#[cfg(any(gdma, pdma))]
-pub use crate::dma::{
-    DmaTransfer as _esp_hal_dma_DmaTransfer,
-    DmaTransferRxTx as _esp_hal_dma_DmaTransferRxTx,
-};
-#[cfg(gpio)]
-pub use crate::gpio::{
-    InputPin as _esp_hal_gpio_InputPin,
-    OutputPin as _esp_hal_gpio_OutputPin,
-    Pin as _esp_hal_gpio_Pin,
-};
-#[cfg(any(i2c0, i2c1))]
-pub use crate::i2c::Instance as _esp_hal_i2c_Instance;
-#[cfg(ledc)]
-pub use crate::ledc::{
-    channel::{
-        ChannelHW as _esp_hal_ledc_channel_ChannelHW,
-        ChannelIFace as _esp_hal_ledc_channel_ChannelIFace,
-    },
-    timer::{TimerHW as _esp_hal_ledc_timer_TimerHW, TimerIFace as _esp_hal_ledc_timer_TimerIFace},
-};
-#[cfg(any(dport, pcr, system))]
-pub use crate::system::SystemExt as _esp_hal_system_SystemExt;
-#[cfg(any(timg0, timg1))]
-pub use crate::timer::{
-    Instance as _esp_hal_timer_Instance,
-    TimerGroupInstance as _esp_hal_timer_TimerGroupInstance,
-};
-#[cfg(any(uart0, uart1, uart2))]
-pub use crate::uart::{Instance as _esp_hal_uart_Instance, UartPins as _esp_hal_uart_UartPins};
-pub use crate::{clock::Clock as _esp_hal_clock_Clock, entry, macros::*};

esp-hal-common/src/rng.rs

@@ -1,106 +0,0 @@
-//! # Random Number Generator
-//!
-//! ## Overview
-//! The Random Number Generator (RNG) Driver for ESP chips is a software module
-//! that provides an interface to generate random numbers using the RNG
-//! peripheral on ESP chips. This driver allows you to generate random numbers
-//! that can be used for various cryptographic, security, or general-purpose
-//! applications.
-//!
-//! The RNG peripheral on ESP chips produces random numbers based on physical
-//! noise sources, which provide true random numbers under specific conditions
-//! (see conditions below).
-//!
-//! To use the [Rng] Driver, you need to initialize it with the RNG peripheral.
-//! Once initialized, you can generate random numbers by calling the `random`
-//! method, which returns a 32-bit unsigned integer.
-//!
-//! Additionally, this driver implements the
-//! [Read](embedded_hal::blocking::rng::Read) trait from the `embedded_hal`
-//! crate, allowing you to generate random bytes by calling the `read` method.
-//
-//! # Important Note
-//!
-//! There are certain pre-conditions which must be met in order for the RNG to
-//! produce *true* random numbers. The hardware RNG produces true random numbers
-//! under any of the following conditions:
-//!
-//! - RF subsystem is enabled (i.e. Wi-Fi or Bluetooth are enabled).
-//! - An internal entropy source has been enabled by calling
-//!   `bootloader_random_enable()` and not yet disabled by calling
-//!   `bootloader_random_disable()`.
-//! - While the ESP-IDF Second stage bootloader is running. This is because the
-//!   default ESP-IDF bootloader implementation calls
-//!   `bootloader_random_enable()` when the bootloader starts, and
-//!   `bootloader_random_disable()` before executing the app.
-//!
-//! When any of these conditions are true, samples of physical noise are
-//! continuously mixed into the internal hardware RNG state to provide entropy.
-//! If none of the above conditions are true, the output of the RNG should be
-//! considered pseudo-random only.
-//!
-//! For more information, please refer to the ESP-IDF documentation:  
-//! <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/random.html>
-//!
-//! # Examples
-//!
-//! ## Initialization
-//!
-//! ```no_run
-//! let mut rng = Rng::new(peripherals.RNG);
-//! ```
-//!
-//! ## Generate a random word (u32)
-//!
-//! ```no_run
-//! let random: u32 = rng.random();
-//! ```
-//!
-//! ## Fill a buffer of arbitrary size with random bytes
-//!
-//! ```no_run
-//! let mut buffer = [0u8; 32];
-//! rng.read(&mut buffer).unwrap();
-//! ```
-
-use core::{convert::Infallible, marker::PhantomData};
-
-use crate::{peripheral::Peripheral, peripherals::RNG};
-
-/// Random number generator driver
-#[derive(Clone, Copy)]
-pub struct Rng {
-    _phantom: PhantomData<RNG>,
-}
-
-impl Rng {
-    /// Create a new random number generator instance
-    pub fn new(_rng: impl Peripheral<P = RNG>) -> Self {
-        Self {
-            _phantom: PhantomData,
-        }
-    }
-
-    #[inline]
-    /// Reads currently available `u32` integer from `RNG`
-    pub fn random(&mut self) -> u32 {
-        // SAFETY: read-only register access
-        unsafe { &*crate::peripherals::RNG::PTR }
-            .data()
-            .read()
-            .bits()
-    }
-}
-
-impl embedded_hal::blocking::rng::Read for Rng {
-    type Error = Infallible;
-
-    fn read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error> {
-        for chunk in buffer.chunks_mut(4) {
-            let bytes = self.random().to_le_bytes();
-            chunk.copy_from_slice(&bytes[..chunk.len()]);
-        }
-
-        Ok(())
-    }
-}

esp-hal-common/src/rsa/esp32.rs

@@ -1,216 +0,0 @@
-use core::{
-    convert::Infallible,
-    marker::PhantomData,
-    ptr::{copy_nonoverlapping, write_bytes},
-};
-
-use crate::rsa::{
-    implement_op,
-    Multi,
-    Rsa,
-    RsaMode,
-    RsaModularExponentiation,
-    RsaModularMultiplication,
-    RsaMultiplication,
-};
-
-impl<'d> Rsa<'d> {
-    /// After the RSA Accelerator is released from reset, the memory blocks
-    /// needs to be initialized, only after that peripheral should be used.
-    /// This function would return without an error if the memory is initialized
-    pub fn ready(&mut self) -> nb::Result<(), Infallible> {
-        if self.rsa.clean().read().clean().bit_is_clear() {
-            return Err(nb::Error::WouldBlock);
-        }
-        Ok(())
-    }
-
-    pub(super) fn write_multi_mode(&mut self, mode: u32) {
-        self.rsa
-            .mult_mode()
-            .write(|w| unsafe { w.bits(mode as u32) });
-    }
-
-    pub(super) fn write_modexp_mode(&mut self, mode: u32) {
-        self.rsa.modexp_mode().write(|w| unsafe { w.bits(mode) });
-    }
-
-    pub(super) fn write_modexp_start(&mut self) {
-        self.rsa
-            .modexp_start()
-            .write(|w| w.modexp_start().set_bit());
-    }
-
-    pub(super) fn write_multi_start(&mut self) {
-        self.rsa.mult_start().write(|w| w.mult_start().set_bit());
-    }
-
-    pub(super) fn clear_interrupt(&mut self) {
-        self.rsa.interrupt().write(|w| w.interrupt().set_bit());
-    }
-
-    pub(super) fn is_idle(&mut self) -> bool {
-        self.rsa.interrupt().read().bits() == 1
-    }
-
-    unsafe fn write_multi_operand_a<const N: usize>(&mut self, operand_a: &[u32; N]) {
-        copy_nonoverlapping(
-            operand_a.as_ptr(),
-            self.rsa.x_mem(0).as_ptr() as *mut u32,
-            N,
-        );
-        write_bytes(self.rsa.x_mem(0).as_ptr().add(N), 0, N);
-    }
-
-    unsafe fn write_multi_operand_b<const N: usize>(&mut self, operand_b: &[u32; N]) {
-        write_bytes(self.rsa.z_mem(0).as_ptr(), 0, N);
-        copy_nonoverlapping(
-            operand_b.as_ptr(),
-            self.rsa.z_mem(0).as_ptr().add(N) as *mut u32,
-            N,
-        );
-    }
-}
-
-pub mod operand_sizes {
-    //! Marker types for the operand sizes
-    use paste::paste;
-
-    use super::{implement_op, Multi, RsaMode};
-
-    implement_op!(
-        (512, multi),
-        (1024, multi),
-        (1536, multi),
-        (2048, multi),
-        (2560),
-        (3072),
-        (3584),
-        (4096)
-    );
-}
-
-impl<'a, 'd, T: RsaMode, const N: usize> RsaModularMultiplication<'a, 'd, T>
-where
-    T: RsaMode<InputType = [u32; N]>,
-{
-    /// Creates an Instance of `RsaMultiplication`.  
-    /// `m_prime` could be calculated using `-(modular multiplicative inverse of
-    /// modulus) mod 2^32`, for more information check 24.3.2 in the
-    /// <https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf>
-    pub fn new(rsa: &'a mut Rsa<'d>, modulus: &T::InputType, m_prime: u32) -> Self {
-        Self::set_mode(rsa);
-        unsafe {
-            rsa.write_modulus(modulus);
-        }
-        rsa.write_mprime(m_prime);
-
-        Self {
-            rsa,
-            phantom: PhantomData,
-        }
-    }
-
-    fn set_mode(rsa: &mut Rsa) {
-        rsa.write_multi_mode((N / 16 - 1) as u32)
-    }
-
-    /// Starts the first step of modular multiplication operation. `r` could be
-    /// calculated using `2 ^ ( bitlength * 2 ) mod modulus`,
-    /// for more information check 24.3.2 in the
-    /// <https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf>
-    pub fn start_step1(&mut self, operand_a: &T::InputType, r: &T::InputType) {
-        unsafe {
-            self.rsa.write_operand_a(operand_a);
-            self.rsa.write_r(r);
-        }
-        self.set_start();
-    }
-
-    /// Starts the second step of modular multiplication operation.
-    /// This is a non blocking function that returns without an error if
-    /// operation is completed successfully. `start_step1` must be called
-    /// before calling this function.
-    pub fn start_step2(&mut self, operand_b: &T::InputType) {
-        loop {
-            if self.rsa.is_idle() {
-                self.rsa.clear_interrupt();
-                unsafe {
-                    self.rsa.write_operand_a(operand_b);
-                }
-                self.set_start();
-                break;
-            }
-        }
-    }
-
-    fn set_start(&mut self) {
-        self.rsa.write_multi_start();
-    }
-}
-
-impl<'a, 'd, T: RsaMode, const N: usize> RsaModularExponentiation<'a, 'd, T>
-where
-    T: RsaMode<InputType = [u32; N]>,
-{
-    /// Creates an Instance of `RsaModularExponentiation`.  
-    /// `m_prime` could be calculated using `-(modular multiplicative inverse of
-    /// modulus) mod 2^32`, for more information check 24.3.2 in the
-    /// <https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf>
-    pub fn new(
-        rsa: &'a mut Rsa<'d>,
-        exponent: &T::InputType,
-        modulus: &T::InputType,
-        m_prime: u32,
-    ) -> Self {
-        Self::set_mode(rsa);
-        unsafe {
-            rsa.write_operand_b(exponent);
-            rsa.write_modulus(modulus);
-        }
-        rsa.write_mprime(m_prime);
-        Self {
-            rsa,
-            phantom: PhantomData,
-        }
-    }
-
-    pub(super) fn set_mode(rsa: &mut Rsa) {
-        rsa.write_modexp_mode((N / 16 - 1) as u32)
-    }
-
-    pub(super) fn set_start(&mut self) {
-        self.rsa.write_modexp_start();
-    }
-}
-
-impl<'a, 'd, T: RsaMode + Multi, const N: usize> RsaMultiplication<'a, 'd, T>
-where
-    T: RsaMode<InputType = [u32; N]>,
-{
-    /// Creates an Instance of `RsaMultiplication`.
-    pub fn new(rsa: &'a mut Rsa<'d>) -> Self {
-        Self::set_mode(rsa);
-        Self {
-            rsa,
-            phantom: PhantomData,
-        }
-    }
-
-    /// Starts the multiplication operation.
-    pub fn start_multiplication(&mut self, operand_a: &T::InputType, operand_b: &T::InputType) {
-        unsafe {
-            self.rsa.write_multi_operand_a(operand_a);
-            self.rsa.write_multi_operand_b(operand_b);
-        }
-        self.set_start();
-    }
-
-    pub(super) fn set_mode(rsa: &mut Rsa) {
-        rsa.write_multi_mode(((N * 2) / 16 + 7) as u32)
-    }
-
-    pub(super) fn set_start(&mut self) {
-        self.rsa.write_multi_start();
-    }
-}

esp-hal-common/src/rsa/esp32cX.rs

@@ -1,349 +0,0 @@
-use core::{convert::Infallible, marker::PhantomData, ptr::copy_nonoverlapping};
-
-use crate::rsa::{
-    implement_op,
-    Multi,
-    Rsa,
-    RsaMode,
-    RsaModularExponentiation,
-    RsaModularMultiplication,
-    RsaMultiplication,
-};
-
-impl<'d> Rsa<'d> {
-    /// After the RSA Accelerator is released from reset, the memory blocks
-    /// needs to be initialized, only after that peripheral should be used.
-    /// This function would return without an error if the memory is initialized
-    pub fn ready(&mut self) -> nb::Result<(), Infallible> {
-        if self.rsa.query_clean().read().query_clean().bit_is_clear() {
-            return Err(nb::Error::WouldBlock);
-        }
-        Ok(())
-    }
-
-    /// Enables/disables rsa interrupt, when enabled rsa perpheral would
-    /// generate an interrupt when a operation is finished.
-    pub fn enable_disable_interrupt(&mut self, enable: bool) {
-        match enable {
-            true => self.rsa.int_ena().write(|w| w.int_ena().set_bit()),
-            false => self.rsa.int_ena().write(|w| w.int_ena().clear_bit()),
-        }
-    }
-
-    fn write_mode(&mut self, mode: u32) {
-        self.rsa.mode().write(|w| unsafe { w.bits(mode as u32) });
-    }
-
-    /// Enables/disables search acceleration, when enabled it would increases
-    /// the performance of modular exponentiation by discarding the
-    /// exponent's bits before the most significant set bit. Note: this might
-    /// affect the security, for more info refer 18.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf>
-    pub fn enable_disable_search_acceleration(&mut self, enable: bool) {
-        match enable {
-            true => self
-                .rsa
-                .search_enable()
-                .write(|w| w.search_enable().set_bit()),
-            false => self
-                .rsa
-                .search_enable()
-                .write(|w| w.search_enable().clear_bit()),
-        }
-    }
-
-    pub(super) fn is_search_enabled(&mut self) -> bool {
-        self.rsa.search_enable().read().search_enable().bit_is_set()
-    }
-
-    pub(super) fn write_search_position(&mut self, search_position: u32) {
-        self.rsa
-            .search_pos()
-            .write(|w| unsafe { w.bits(search_position) });
-    }
-
-    /// Enables/disables constant time acceleration, when enabled it would
-    /// increases the performance of modular exponentiation by simplifying
-    /// the calculation concerning the 0 bits of the exponent i.e. lesser the
-    /// hamming weight, greater the performance. Note : this might affect
-    /// the security, for more info refer 18.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf>
-    pub fn enable_disable_constant_time_acceleration(&mut self, enable: bool) {
-        match enable {
-            true => self
-                .rsa
-                .constant_time()
-                .write(|w| w.constant_time().clear_bit()),
-            false => self
-                .rsa
-                .constant_time()
-                .write(|w| w.constant_time().set_bit()),
-        }
-    }
-
-    pub(super) fn write_modexp_start(&mut self) {
-        self.rsa
-            .set_start_modexp()
-            .write(|w| w.set_start_modexp().set_bit());
-    }
-
-    pub(super) fn write_multi_start(&mut self) {
-        self.rsa
-            .set_start_mult()
-            .write(|w| w.set_start_mult().set_bit());
-    }
-
-    fn write_modmulti_start(&mut self) {
-        self.rsa
-            .set_start_modmult()
-            .write(|w| w.set_start_modmult().set_bit());
-    }
-
-    pub(super) fn clear_interrupt(&mut self) {
-        self.rsa.int_clr().write(|w| w.clear_interrupt().set_bit());
-    }
-
-    pub(super) fn is_idle(&mut self) -> bool {
-        self.rsa.query_idle().read().query_idle().bit_is_set()
-    }
-
-    unsafe fn write_multi_operand_b<const N: usize>(&mut self, operand_b: &[u32; N]) {
-        copy_nonoverlapping(
-            operand_b.as_ptr(),
-            self.rsa.z_mem(0).as_ptr().add(N) as *mut u32,
-            N,
-        );
-    }
-}
-
-pub mod operand_sizes {
-    //! Marker types for the operand sizes
-    use paste::paste;
-
-    use super::{implement_op, Multi, RsaMode};
-
-    implement_op!(
-        (32, multi),
-        (64, multi),
-        (96, multi),
-        (128, multi),
-        (160, multi),
-        (192, multi),
-        (224, multi),
-        (256, multi),
-        (288, multi),
-        (320, multi),
-        (352, multi),
-        (384, multi),
-        (416, multi),
-        (448, multi),
-        (480, multi),
-        (512, multi),
-        (544, multi),
-        (576, multi),
-        (608, multi),
-        (640, multi),
-        (672, multi),
-        (704, multi),
-        (736, multi),
-        (768, multi),
-        (800, multi),
-        (832, multi),
-        (864, multi),
-        (896, multi),
-        (928, multi),
-        (960, multi),
-        (992, multi),
-        (1024, multi),
-        (1056, multi),
-        (1088, multi),
-        (1120, multi),
-        (1152, multi),
-        (1184, multi),
-        (1216, multi),
-        (1248, multi),
-        (1280, multi),
-        (1312, multi),
-        (1344, multi),
-        (1376, multi),
-        (1408, multi),
-        (1440, multi),
-        (1472, multi),
-        (1504, multi),
-        (1536, multi),
-        (1568),
-        (1600),
-        (1632),
-        (1664),
-        (1696),
-        (1728),
-        (1760),
-        (1792),
-        (1824),
-        (1856),
-        (1888),
-        (1920),
-        (1952),
-        (1984),
-        (2016),
-        (2048),
-        (2080),
-        (2112),
-        (2144),
-        (2176),
-        (2208),
-        (2240),
-        (2272),
-        (2304),
-        (2336),
-        (2368),
-        (2400),
-        (2432),
-        (2464),
-        (2496),
-        (2528),
-        (2560),
-        (2592),
-        (2624),
-        (2656),
-        (2688),
-        (2720),
-        (2752),
-        (2784),
-        (2816),
-        (2848),
-        (2880),
-        (2912),
-        (2944),
-        (2976),
-        (3008),
-        (3040),
-        (3072)
-    );
-}
-
-impl<'a, 'd, T: RsaMode, const N: usize> RsaModularExponentiation<'a, 'd, T>
-where
-    T: RsaMode<InputType = [u32; N]>,
-{
-    /// Creates an Instance of `RsaModularExponentiation`.  
-    /// `m_prime` could be calculated using `-(modular multiplicative inverse of
-    /// modulus) mod 2^32`, for more information check 19.3.1 in the
-    /// <https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf>
-    pub fn new(
-        rsa: &'a mut Rsa<'d>,
-        exponent: &T::InputType,
-        modulus: &T::InputType,
-        m_prime: u32,
-    ) -> Self {
-        Self::set_mode(rsa);
-        unsafe {
-            rsa.write_operand_b(exponent);
-            rsa.write_modulus(modulus);
-        }
-        rsa.write_mprime(m_prime);
-        if rsa.is_search_enabled() {
-            rsa.write_search_position(Self::find_search_pos(exponent));
-        }
-        Self {
-            rsa,
-            phantom: PhantomData,
-        }
-    }
-
-    fn find_search_pos(exponent: &T::InputType) -> u32 {
-        for (i, byte) in exponent.iter().rev().enumerate() {
-            if *byte == 0 {
-                continue;
-            }
-            return (exponent.len() * 32) as u32 - (byte.leading_zeros() + i as u32 * 32) - 1;
-        }
-        0
-    }
-
-    pub(super) fn set_mode(rsa: &mut Rsa) {
-        rsa.write_mode((N - 1) as u32)
-    }
-
-    pub(super) fn set_start(&mut self) {
-        self.rsa.write_modexp_start();
-    }
-}
-
-impl<'a, 'd, T: RsaMode, const N: usize> RsaModularMultiplication<'a, 'd, T>
-where
-    T: RsaMode<InputType = [u32; N]>,
-{
-    fn write_mode(rsa: &mut Rsa) {
-        rsa.write_mode((N - 1) as u32)
-    }
-
-    /// Creates an Instance of `RsaModularMultiplication`.  
-    /// `m_prime` could be calculated using `-(modular multiplicative inverse of
-    /// modulus) mod 2^32`, for more information check 19.3.1 in the
-    /// <https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf>
-    pub fn new(
-        rsa: &'a mut Rsa<'d>,
-        operand_a: &T::InputType,
-        operand_b: &T::InputType,
-        modulus: &T::InputType,
-        m_prime: u32,
-    ) -> Self {
-        Self::write_mode(rsa);
-        rsa.write_mprime(m_prime);
-        unsafe {
-            rsa.write_modulus(modulus);
-            rsa.write_operand_a(operand_a);
-            rsa.write_operand_b(operand_b);
-        }
-        Self {
-            rsa,
-            phantom: PhantomData,
-        }
-    }
-
-    /// Starts the modular multiplication operation. `r` could be calculated
-    /// using `2 ^ ( bitlength * 2 ) mod modulus`, for more information
-    /// check 19.3.1 in the <https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf>
-    pub fn start_modular_multiplication(&mut self, r: &T::InputType) {
-        unsafe {
-            self.rsa.write_r(r);
-        }
-        self.set_start();
-    }
-
-    fn set_start(&mut self) {
-        self.rsa.write_modmulti_start();
-    }
-}
-
-impl<'a, 'd, T: RsaMode + Multi, const N: usize> RsaMultiplication<'a, 'd, T>
-where
-    T: RsaMode<InputType = [u32; N]>,
-{
-    /// Creates an Instance of `RsaMultiplication`.
-    pub fn new(rsa: &'a mut Rsa<'d>, operand_a: &T::InputType) -> Self {
-        Self::set_mode(rsa);
-        unsafe {
-            rsa.write_operand_a(operand_a);
-        }
-        Self {
-            rsa,
-            phantom: PhantomData,
-        }
-    }
-
-    /// Starts the multiplication operation.
-    pub fn start_multiplication(&mut self, operand_b: &T::InputType) {
-        unsafe {
-            self.rsa.write_multi_operand_b(operand_b);
-        }
-        self.set_start();
-    }
-
-    pub(super) fn set_mode(rsa: &mut Rsa) {
-        rsa.write_mode((N * 2 - 1) as u32)
-    }
-
-    pub(super) fn set_start(&mut self) {
-        self.rsa.write_multi_start();
-    }
-}