Fix DMA starving SPI (#2152)
* Fix DMA starving SPI * Simplify cfgs * Trigger an update before starting transaction * Do not update after enable_dma, use start_operation
This commit is contained in:
Dániel Buga
GitHub
parent
351a64937b
commit
2a74addee0
@ -61,9 +61,9 @@
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use core::marker::PhantomData;
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pub use dma::*;
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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use enumset::EnumSet;
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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use enumset::EnumSetType;
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use fugit::HertzU32;
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#[cfg(feature = "place-spi-driver-in-ram")]
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@ -91,7 +91,7 @@ use crate::{
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};
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/// Enumeration of possible SPI interrupt events.
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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#[derive(EnumSetType)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum SpiInterrupt {
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@ -999,25 +999,25 @@ mod dma {
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}
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/// Listen for the given interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn listen(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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self.spi.listen(interrupts);
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}
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/// Unlisten the given interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn unlisten(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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self.spi.unlisten(interrupts);
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}
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/// Gets asserted interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn interrupts(&mut self) -> EnumSet<SpiInterrupt> {
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self.spi.interrupts()
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}
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/// Resets asserted interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn clear_interrupts(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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self.spi.clear_interrupts(interrupts);
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}
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@ -1516,7 +1516,7 @@ mod dma {
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}
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/// Listen for the given interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn listen(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
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spi_dma.listen(interrupts);
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@ -1524,7 +1524,7 @@ mod dma {
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}
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/// Unlisten the given interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn unlisten(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
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spi_dma.unlisten(interrupts);
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@ -1532,7 +1532,7 @@ mod dma {
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}
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/// Gets asserted interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn interrupts(&mut self) -> EnumSet<SpiInterrupt> {
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let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
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let interrupts = spi_dma.interrupts();
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@ -1542,7 +1542,7 @@ mod dma {
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}
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/// Resets asserted interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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pub fn clear_interrupts(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
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spi_dma.clear_interrupts(interrupts);
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@ -2231,9 +2231,8 @@ pub trait InstanceDma: Instance {
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.modify(|_, w| w.usr_miso().bit(true).usr_mosi().bit(true));
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self.enable_dma();
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self.update();
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self.clear_dma_interrupts();
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reset_dma_before_load_dma_dscr(reg_block);
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rx.prepare_transfer(self.dma_peripheral(), rx_buffer)
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.and_then(|_| rx.start_transfer())?;
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@ -2242,7 +2241,7 @@ pub trait InstanceDma: Instance {
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reset_dma_before_usr_cmd(reg_block);
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reg_block.cmd().modify(|_, w| w.usr().set_bit());
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self.start_operation();
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Ok(())
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}
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@ -2281,23 +2280,16 @@ pub trait InstanceDma: Instance {
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}
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self.enable_dma();
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self.update();
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self.clear_dma_interrupts();
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reset_dma_before_load_dma_dscr(reg_block);
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self.clear_dma_interrupts();
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tx.prepare_transfer(self.dma_peripheral(), buffer)?;
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tx.start_transfer()?;
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reset_dma_before_usr_cmd(reg_block);
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// Wait for at least one clock cycle for the DMA to fill the SPI async FIFO,
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// before starting the SPI
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#[cfg(riscv)]
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riscv::asm::delay(1);
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#[cfg(xtensa)]
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xtensa_lx::timer::delay(1);
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reg_block.cmd().modify(|_, w| w.usr().set_bit());
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self.start_operation();
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Ok(())
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}
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@ -2330,17 +2322,16 @@ pub trait InstanceDma: Instance {
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}
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self.enable_dma();
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self.update();
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self.clear_dma_interrupts();
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reset_dma_before_load_dma_dscr(reg_block);
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self.clear_dma_interrupts();
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reset_dma_before_usr_cmd(reg_block);
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rx.prepare_transfer(self.dma_peripheral(), buffer)?;
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rx.start_transfer()?;
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reg_block.cmd().modify(|_, w| w.usr().set_bit());
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reset_dma_before_usr_cmd(reg_block);
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self.start_operation();
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Ok(())
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}
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@ -2354,19 +2345,19 @@ pub trait InstanceDma: Instance {
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}
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}
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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#[cfg(gdma)]
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fn enable_dma(&self) {
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let reg_block = self.register_block();
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reg_block.dma_conf().modify(|_, w| w.dma_tx_ena().set_bit());
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reg_block.dma_conf().modify(|_, w| w.dma_rx_ena().set_bit());
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}
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#[cfg(any(esp32, esp32s2))]
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#[cfg(pdma)]
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fn enable_dma(&self) {
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// for non GDMA this is done in `assign_tx_device` / `assign_rx_device`
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}
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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#[cfg(gdma)]
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fn clear_dma_interrupts(&self) {
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let reg_block = self.register_block();
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reg_block.dma_int_clr().write(|w| {
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@ -2383,7 +2374,7 @@ pub trait InstanceDma: Instance {
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});
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}
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#[cfg(any(esp32, esp32s2))]
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#[cfg(pdma)]
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fn clear_dma_interrupts(&self) {
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let reg_block = self.register_block();
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reg_block.dma_int_clr().write(|w| {
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@ -2409,9 +2400,9 @@ pub trait InstanceDma: Instance {
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}
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}
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#[cfg(not(any(esp32, esp32s2)))]
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fn reset_dma_before_usr_cmd(reg_block: &RegisterBlock) {
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reg_block.dma_conf().modify(|_, w| {
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fn reset_dma_before_usr_cmd(_reg_block: &RegisterBlock) {
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#[cfg(gdma)]
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_reg_block.dma_conf().modify(|_, w| {
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w.rx_afifo_rst()
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.set_bit()
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.buf_afifo_rst()
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@ -2421,13 +2412,10 @@ fn reset_dma_before_usr_cmd(reg_block: &RegisterBlock) {
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});
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}
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#[cfg(any(esp32, esp32s2))]
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fn reset_dma_before_usr_cmd(_reg_block: &RegisterBlock) {}
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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fn reset_dma_before_load_dma_dscr(_reg_block: &RegisterBlock) {}
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#[cfg(any(esp32, esp32s2))]
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#[cfg(pdma)]
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fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
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reg_block.dma_conf().modify(|_, w| {
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w.out_rst()
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@ -2514,7 +2502,7 @@ pub trait Instance: private::Sealed {
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.clear_bit()
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});
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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reg_block.clk_gate().modify(|_, w| {
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w.clk_en()
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.set_bit()
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@ -2533,7 +2521,7 @@ pub trait Instance: private::Sealed {
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.modify(|_, w| w.spi2_clkm_sel().bits(1));
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}
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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reg_block.ctrl().modify(|_, w| {
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w.q_pol()
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.clear_bit()
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@ -2853,7 +2841,7 @@ pub trait Instance: private::Sealed {
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fn set_interrupt_handler(&mut self, handler: InterruptHandler);
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/// Listen for the given interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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fn listen(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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let reg_block = self.register_block();
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@ -2869,7 +2857,7 @@ pub trait Instance: private::Sealed {
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}
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/// Unlisten the given interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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fn unlisten(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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let reg_block = self.register_block();
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@ -2885,7 +2873,7 @@ pub trait Instance: private::Sealed {
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}
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/// Gets asserted interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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fn interrupts(&mut self) -> EnumSet<SpiInterrupt> {
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let mut res = EnumSet::new();
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let reg_block = self.register_block();
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@ -2900,7 +2888,7 @@ pub trait Instance: private::Sealed {
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}
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/// Resets asserted interrupts
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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fn clear_interrupts(&mut self, interrupts: EnumSet<SpiInterrupt>) {
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let reg_block = self.register_block();
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@ -2967,7 +2955,7 @@ pub trait Instance: private::Sealed {
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fn ch_bus_freq(&mut self, frequency: HertzU32) {
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// Disable clock source
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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self.register_block().clk_gate().modify(|_, w| {
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w.clk_en()
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.clear_bit()
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@ -2981,7 +2969,7 @@ pub trait Instance: private::Sealed {
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self.setup(frequency);
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// Enable clock source
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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self.register_block().clk_gate().modify(|_, w| {
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w.clk_en()
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.set_bit()
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@ -3048,9 +3036,7 @@ pub trait Instance: private::Sealed {
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let reg_block = self.register_block();
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reg_block.w(0).write(|w| w.buf().set(word.into()));
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self.update();
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reg_block.cmd().modify(|_, w| w.usr().set_bit());
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self.start_operation();
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Ok(())
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}
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@ -3103,9 +3089,7 @@ pub trait Instance: private::Sealed {
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}
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}
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self.update();
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self.register_block().cmd().modify(|_, w| w.usr().set_bit());
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self.start_operation();
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// Wait for all chunks to complete except the last one.
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// The function is allowed to return before the bus is idle.
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@ -3222,7 +3206,7 @@ pub trait Instance: private::Sealed {
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.bit(command_state)
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});
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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reg_block.clk_gate().modify(|_, w| {
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w.clk_en()
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.set_bit()
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@ -3370,13 +3354,12 @@ pub trait Instance: private::Sealed {
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}
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self.configure_datalen(buffer.len() as u32 * 8);
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self.update();
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reg_block.cmd().modify(|_, w| w.usr().set_bit());
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self.start_operation();
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self.flush()?;
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self.read_bytes_from_fifo(buffer)
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}
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#[cfg(not(any(esp32, esp32s2)))]
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#[cfg(gdma)]
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fn update(&self) {
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let reg_block = self.register_block();
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@ -3387,7 +3370,7 @@ pub trait Instance: private::Sealed {
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}
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}
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#[cfg(any(esp32, esp32s2))]
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#[cfg(pdma)]
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fn update(&self) {
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// not need/available on ESP32/ESP32S2
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}
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@ -60,32 +60,40 @@ mod tests {
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}
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}
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let mosi_loopback = mosi.peripheral_input();
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let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
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let miso = mosi.peripheral_input();
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let spi = Spi::new(peripherals.SPI2, 10000.kHz(), SpiMode::Mode0)
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.with_sck(sclk)
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.with_mosi(mosi)
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.with_miso(mosi_loopback)
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.with_miso(miso)
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.with_dma(dma_channel.configure(false, DmaPriority::Priority0));
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Context { spi }
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_dma_transfer(ctx: Context) {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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// This test case sends a large amount of data, twice, to verify that
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// https://github.com/esp-rs/esp-hal/issues/2151 is and remains fixed.
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
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for (i, v) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
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*v = (i % 255) as u8;
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}
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let transfer = ctx
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.spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice());
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let mut spi = ctx.spi;
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for i in 0..4 {
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dma_tx_buf.as_mut_slice()[0] = i as u8;
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*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
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let transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice());
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}
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}
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#[test]
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