GetLitFam/esp-hal
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Remove PcntSource (#2134)

Browse Source
This commit is contained in:
Dániel Buga 2024-09-12 10:30:16 +02:00 committed by GitHub
parent b5152dcae5
commit 515e67092b
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
9 changed files with 72 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
esp-hal/CHANGELOG.md
View File

@ -61,6 +61,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Removed `Rtc::get_time_raw` (#1883)
- Removed `_with_default_pins` UART constructors (#2132)
- Removed `uart::{DefaultRxPin, DefaultTxPin}` (#2132)
- Removed `PcntSource` and `PcntInputConfig`. (#2134)
## [0.20.1] - 2024-08-30

21
esp-hal/MIGRATING-0.20.md
View File

@ -125,3 +125,24 @@ let rtc = Rtc::new(peripherals.LPWR);
- let current_time_ms = rtc.get_time_ms();
+ let current_time_ms = rtc.current_time().and_utc().timestamp_millis(); // assuming UTC
```
## PCNT input config
The `PcntSource` and `PcntInputConfig` have been removed. You can use `Input` or `Flex` instead to
configure an input pin, and pass it to `set_edge_signal` or `set_ctrl_signal`.
```diff
- let mut pin_a = io.pins.gpio4;
- ch0.set_ctrl_signal(PcntSource::from_pin(
- &mut pin_a,
- PcntInputConfig { pull: Pull::Up },
- ));
+ ch0.set_ctrl_signal(Input::new(io.pins.gpio4, Pull::Up));
- let mut pin_b = io.pins.gpio5;
- ch0.set_edge_signal(PcntSource::from_pin(
- &mut pin_b,
- PcntInputConfig { pull: Pull::Down },
- ));
+ ch0.set_edge_signal(Input::new(io.pins.gpio5, Pull::Down));
```

53
esp-hal/src/pcnt/channel.rs
View File

@ -9,40 +9,11 @@
use core::marker::PhantomData;
use crate::gpio::{interconnect::AnyInputSignal, InputSignal, PeripheralInput, Pull};
/// Configuration for an PCNT input pin
#[derive(Clone, Copy, Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct PcntInputConfig {
/// Configuration for the internal pull-up resistors
pub pull: Pull,
}
impl Default for PcntInputConfig {
fn default() -> Self {
Self { pull: Pull::None }
}
}
pub use crate::peripherals::pcnt::unit::conf0::{CTRL_MODE as CtrlMode, EDGE_MODE as EdgeMode};
/// PcntPin can be always high, always low, or an actual pin
#[derive(Clone)]
pub struct PcntSource {
source: AnyInputSignal,
}
impl PcntSource {
/// Creates a `PcntSource` from an input pin with the specified
/// configuration.
pub fn from(source: impl Into<AnyInputSignal>, pin_config: PcntInputConfig) -> Self {
let source = source.into();
source.init_input(pin_config.pull, crate::private::Internal);
Self { source }
}
}
use crate::{
gpio::{InputSignal, PeripheralInput},
peripheral::Peripheral,
};
/// Represents a channel within a pulse counter unit.
pub struct Channel<'d, const UNIT: usize, const NUM: usize> {
@ -95,7 +66,7 @@ impl<'d, const UNIT: usize, const NUM: usize> Channel<'d, UNIT, NUM> {
}
/// Set the control signal (pin/high/low) for this channel
pub fn set_ctrl_signal(&self, mut source: PcntSource) -> &Self {
pub fn set_ctrl_signal<P: PeripheralInput>(&self, source: impl Peripheral<P = P>) -> &Self {
let signal = match UNIT {
0 => match NUM {
0 => InputSignal::PCNT0_CTRL_CH0,
@ -145,15 +116,15 @@ impl<'d, const UNIT: usize, const NUM: usize> Channel<'d, UNIT, NUM> {
};
if (signal as usize) <= crate::gpio::INPUT_SIGNAL_MAX as usize {
source
.source
.connect_input_to_peripheral(signal, crate::private::Internal);
crate::into_ref!(source);
source.enable_input(true, crate::private::Internal);
source.connect_input_to_peripheral(signal, crate::private::Internal);
}
self
}
/// Set the edge signal (pin/high/low) for this channel
pub fn set_edge_signal(&self, mut source: PcntSource) -> &Self {
pub fn set_edge_signal<P: PeripheralInput>(&self, source: impl Peripheral<P = P>) -> &Self {
let signal = match UNIT {
0 => match NUM {
0 => InputSignal::PCNT0_SIG_CH0,
@ -203,9 +174,9 @@ impl<'d, const UNIT: usize, const NUM: usize> Channel<'d, UNIT, NUM> {
};
if (signal as usize) <= crate::gpio::INPUT_SIGNAL_MAX as usize {
source
.source
.connect_input_to_peripheral(signal, crate::private::Internal);
crate::into_ref!(source);
source.enable_input(true, crate::private::Internal);
source.connect_input_to_peripheral(signal, crate::private::Internal);
}
self
}

32
examples/src/bin/pcnt_encoder.rs
View File

@ -20,13 +20,9 @@ use core::{cell::RefCell, cmp::min, sync::atomic::Ordering};
use critical_section::Mutex;
use esp_backtrace as _;
use esp_hal::{
gpio::{Io, Pull},
gpio::{Input, Io, Pull},
interrupt::Priority,
pcnt::{
channel::{self, PcntInputConfig, PcntSource},
unit,
Pcnt,
},
pcnt::{channel, unit, Pcnt},
prelude::*,
};
use esp_println::println;
@ -53,30 +49,18 @@ fn main() -> ! {
println!("setup channel 0");
let ch0 = &u0.channel0;
let pin_a = io.pins.gpio4;
let pin_b = io.pins.gpio5;
let pin_a = Input::new(io.pins.gpio4, Pull::Up);
let pin_b = Input::new(io.pins.gpio5, Pull::Up);
ch0.set_ctrl_signal(PcntSource::from(
pin_a.peripheral_input(),
PcntInputConfig { pull: Pull::Up },
));
ch0.set_edge_signal(PcntSource::from(
pin_b.peripheral_input(),
PcntInputConfig { pull: Pull::Up },
));
ch0.set_ctrl_signal(pin_a.peripheral_input());
ch0.set_edge_signal(pin_b.peripheral_input());
ch0.set_ctrl_mode(channel::CtrlMode::Reverse, channel::CtrlMode::Keep);
ch0.set_input_mode(channel::EdgeMode::Increment, channel::EdgeMode::Decrement);
println!("setup channel 1");
let ch1 = &u0.channel1;
ch1.set_ctrl_signal(PcntSource::from(
pin_b.peripheral_input(),
PcntInputConfig { pull: Pull::Up },
));
ch1.set_edge_signal(PcntSource::from(
pin_a.peripheral_input(),
PcntInputConfig { pull: Pull::Up },
));
ch1.set_ctrl_signal(pin_b.peripheral_input());
ch1.set_edge_signal(pin_a.peripheral_input());
ch1.set_ctrl_mode(channel::CtrlMode::Reverse, channel::CtrlMode::Keep);
ch1.set_input_mode(channel::EdgeMode::Decrement, channel::EdgeMode::Increment);

43
hil-test/tests/pcnt.rs
View File

@ -7,11 +7,8 @@
use esp_hal::{
delay::Delay,
gpio::{AnyPin, Io, Level, Output, Pin, Pull},
pcnt::{
channel::{EdgeMode, PcntInputConfig, PcntSource},
Pcnt,
},
gpio::{AnyPin, Input, Io, Level, Output, Pin, Pull},
pcnt::{channel::EdgeMode, Pcnt},
};
use hil_test as _;
@ -51,10 +48,8 @@ mod tests {
let unit = ctx.pcnt.unit0;
// Setup channel 0 to increment the count when gpio2 does LOW -> HIGH
unit.channel0.set_edge_signal(PcntSource::from(
ctx.input,
PcntInputConfig { pull: Pull::Down },
));
unit.channel0
.set_edge_signal(Input::new(ctx.input, Pull::Down));
unit.channel0
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
@ -90,10 +85,8 @@ mod tests {
let unit = ctx.pcnt.unit1;
// Setup channel 0 to increment the count when gpio2 does LOW -> HIGH
unit.channel0.set_edge_signal(PcntSource::from(
ctx.input,
PcntInputConfig { pull: Pull::Up },
));
unit.channel0
.set_edge_signal(Input::new(ctx.input, Pull::Up));
unit.channel0
.set_input_mode(EdgeMode::Increment, EdgeMode::Hold);
@ -131,10 +124,8 @@ mod tests {
unit.set_high_limit(Some(3)).unwrap();
// Setup channel 0 to increment the count when gpio2 does LOW -> HIGH
unit.channel0.set_edge_signal(PcntSource::from(
ctx.input,
PcntInputConfig { pull: Pull::Up },
));
unit.channel0
.set_edge_signal(Input::new(ctx.input, Pull::Up));
unit.channel0
.set_input_mode(EdgeMode::Increment, EdgeMode::Hold);
@ -194,10 +185,8 @@ mod tests {
unit.clear();
// Setup channel 0 to increment the count when gpio2 does LOW -> HIGH
unit.channel0.set_edge_signal(PcntSource::from(
ctx.input,
PcntInputConfig { pull: Pull::Up },
));
unit.channel0
.set_edge_signal(Input::new(ctx.input, Pull::Up));
unit.channel0
.set_input_mode(EdgeMode::Increment, EdgeMode::Hold);
@ -261,10 +250,8 @@ mod tests {
unit.clear();
// Setup channel 0 to decrement the count when gpio2 does LOW -> HIGH
unit.channel0.set_edge_signal(PcntSource::from(
ctx.input,
PcntInputConfig { pull: Pull::Up },
));
unit.channel0
.set_edge_signal(Input::new(ctx.input, Pull::Up));
unit.channel0
.set_input_mode(EdgeMode::Decrement, EdgeMode::Hold);
@ -319,10 +306,8 @@ mod tests {
let unit = ctx.pcnt.unit2;
// Setup channel 1 to increment the count when gpio2 does LOW -> HIGH
unit.channel1.set_edge_signal(PcntSource::from(
ctx.input,
PcntInputConfig { pull: Pull::Up },
));
unit.channel1
.set_edge_signal(Input::new(ctx.input, Pull::Up));
unit.channel1
.set_input_mode(EdgeMode::Increment, EdgeMode::Hold);

15
hil-test/tests/qspi_write.rs
View File

@ -8,12 +8,8 @@
use esp_hal::{
dma::{Channel, Dma, DmaPriority, DmaTxBuf},
dma_buffers,
gpio::{AnyPin, Io, Pull},
pcnt::{
channel::{EdgeMode, PcntInputConfig, PcntSource},
unit::Unit,
Pcnt,
},
gpio::{interconnect::InputSignal, AnyPin, Io, Pull},
pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
prelude::*,
spi::{
master::{Address, Command, Spi, SpiDma},
@ -38,7 +34,7 @@ cfg_if::cfg_if! {
struct Context {
spi: esp_hal::peripherals::SPI2,
pcnt_source: PcntSource,
pcnt_source: InputSignal,
pcnt: esp_hal::peripherals::PCNT,
dma_channel: Channel<'static, DmaChannel0, Blocking>,
mosi: AnyPin,
@ -121,10 +117,7 @@ mod tests {
Context {
spi: peripherals.SPI2,
pcnt_source: PcntSource::from(
mosi.peripheral_input(),
PcntInputConfig { pull: Pull::None },
),
pcnt_source: mosi.peripheral_input(),
pcnt: peripherals.PCNT,
dma_channel,
mosi,

12
hil-test/tests/spi_full_duplex_dma_async.rs
View File

@ -10,12 +10,8 @@ use embedded_hal_async::spi::SpiBus;
use esp_hal::{
dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
dma_buffers,
gpio::{Io, Pull},
pcnt::{
channel::{EdgeMode, PcntInputConfig, PcntSource},
unit::Unit,
Pcnt,
},
gpio::{interconnect::InputSignal, Io},
pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
peripherals::SPI2,
prelude::*,
spi::{
@ -42,7 +38,7 @@ const DMA_BUFFER_SIZE: usize = 5;
struct Context {
spi: SpiDmaBus<'static, SPI2, DmaChannel0, FullDuplexMode, Async>,
pcnt_source: PcntSource,
pcnt_source: InputSignal,
pcnt_unit: Unit<'static, 0>,
}
@ -88,7 +84,7 @@ mod tests {
Context {
spi,
pcnt_source: PcntSource::from(mosi_loopback_pcnt, PcntInputConfig { pull: Pull::Down }),
pcnt_source: mosi_loopback_pcnt,
pcnt_unit: pcnt.unit0,
}
}

12
hil-test/tests/spi_full_duplex_dma_pcnt.rs
View File

@ -8,12 +8,8 @@
use esp_hal::{
dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
dma_buffers,
gpio::{Io, Pull},
pcnt::{
channel::{EdgeMode, PcntInputConfig, PcntSource},
unit::Unit,
Pcnt,
},
gpio::{interconnect::InputSignal, Io},
pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
peripherals::SPI2,
prelude::*,
spi::{
@ -38,7 +34,7 @@ cfg_if::cfg_if! {
struct Context {
spi: SpiDma<'static, SPI2, DmaChannel0, FullDuplexMode, Blocking>,
pcnt_source: PcntSource,
pcnt_source: InputSignal,
pcnt_unit: Unit<'static, 0>,
}
@ -79,7 +75,7 @@ mod tests {
Context {
spi,
pcnt_source: PcntSource::from(mosi_loopback_pcnt, PcntInputConfig { pull: Pull::Down }),
pcnt_source: mosi_loopback_pcnt,
pcnt_unit: pcnt.unit0,
}
}

12
hil-test/tests/spi_half_duplex_write.rs
View File

@ -8,12 +8,8 @@
use esp_hal::{
dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
dma_buffers,
gpio::{Io, Pull},
pcnt::{
channel::{EdgeMode, PcntInputConfig, PcntSource},
unit::Unit,
Pcnt,
},
gpio::{interconnect::InputSignal, Io},
pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
peripherals::SPI2,
prelude::*,
spi::{
@ -40,7 +36,7 @@ cfg_if::cfg_if! {
struct Context {
spi: SpiDma<'static, SPI2, DmaChannel0, HalfDuplexMode, Blocking>,
pcnt_unit: Unit<'static, 0>,
pcnt_source: PcntSource,
pcnt_source: InputSignal,
}
#[cfg(test)]
@ -81,8 +77,8 @@ mod tests {
Context {
spi,
pcnt_source: PcntSource::from(mosi_loopback, PcntInputConfig { pull: Pull::Down }),
pcnt_unit: pcnt.unit0,
pcnt_source: mosi_loopback,
}
}