140 lines
4.0 KiB
Rust
140 lines
4.0 KiB
Rust
//! SPI Full Duplex DMA Test
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//% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: generic-queue
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#![no_std]
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#![no_main]
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use embedded_hal_async::spi::SpiBus;
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use esp_hal::{
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dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
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dma_buffers,
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gpio::{interconnect::InputSignal, Io},
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pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
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peripherals::SPI2,
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prelude::*,
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spi::{
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master::{Spi, SpiDmaBus},
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FullDuplexMode,
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SpiMode,
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},
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Async,
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};
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(any(
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feature = "esp32",
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feature = "esp32s2",
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))] {
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use esp_hal::dma::Spi2DmaChannel as DmaChannel0;
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} else {
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use esp_hal::dma::DmaChannel0;
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}
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}
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const DMA_BUFFER_SIZE: usize = 5;
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struct Context {
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spi: SpiDmaBus<'static, SPI2, DmaChannel0, FullDuplexMode, Async>,
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pcnt_source: InputSignal,
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pcnt_unit: Unit<'static, 0>,
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}
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#[cfg(test)]
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#[embedded_test::tests(executor = esp_hal_embassy::Executor::new())]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let pcnt = Pcnt::new(peripherals.PCNT);
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let sclk = io.pins.gpio0;
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let (_, mosi) = hil_test::common_test_pins!(io);
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let dma = Dma::new(peripherals.DMA);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
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let dma_channel = dma.spi2channel;
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} else {
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let dma_channel = dma.channel0;
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}
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}
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mosi_loopback = mosi.peripheral_input();
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let mosi_loopback_pcnt = mosi.peripheral_input();
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let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
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.with_sck(sclk)
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.with_mosi(mosi)
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.with_miso(mosi_loopback)
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.with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0))
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.with_buffers(dma_rx_buf, dma_tx_buf);
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Context {
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spi,
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pcnt_source: mosi_loopback_pcnt,
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pcnt_unit: pcnt.unit0,
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}
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}
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#[test]
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#[timeout(3)]
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async fn test_async_dma_read_dma_write_pcnt(mut ctx: Context) {
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ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
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ctx.pcnt_unit
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.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut receive = [0; DMA_BUFFER_SIZE];
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// Fill the buffer where each byte has 3 pos edges.
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let transmit = [0b0110_1010; DMA_BUFFER_SIZE];
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for i in 1..4 {
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receive.copy_from_slice(&[5, 5, 5, 5, 5]);
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SpiBus::read(&mut ctx.spi, &mut receive).await.unwrap();
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assert_eq!(receive, [0, 0, 0, 0, 0]);
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SpiBus::write(&mut ctx.spi, &transmit).await.unwrap();
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assert_eq!(ctx.pcnt_unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
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}
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}
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#[test]
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#[timeout(3)]
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async fn test_async_dma_read_dma_transfer_pcnt(mut ctx: Context) {
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ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
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ctx.pcnt_unit
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.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut receive = [0; DMA_BUFFER_SIZE];
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// Fill the buffer where each byte has 3 pos edges.
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let transmit = [0b0110_1010; DMA_BUFFER_SIZE];
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for i in 1..4 {
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receive.copy_from_slice(&[5, 5, 5, 5, 5]);
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SpiBus::read(&mut ctx.spi, &mut receive).await.unwrap();
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assert_eq!(receive, [0, 0, 0, 0, 0]);
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SpiBus::transfer(&mut ctx.spi, &mut receive, &transmit)
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.await
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.unwrap();
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assert_eq!(ctx.pcnt_unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
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}
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}
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}
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