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Slight cleanup throughout (#2575)

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* Slight cleanup throughout

* Explain empty build script
This commit is contained in:
Dániel Buga 2024-11-21 10:06:49 +01:00 committed by GitHub
parent 02ddad47c0
commit 457ed44802
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10 changed files with 46 additions and 87 deletions
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27
esp-hal/Cargo.toml
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@ -45,13 +45,11 @@ nb = "1.1.0"
paste = "1.0.15"
portable-atomic = { version = "1.9.0", default-features = false }
procmacros = { version = "0.15.0", features = ["enum-dispatch", "interrupt", "ram"], package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
riscv = { version = "0.12.1", optional = true }
strum = { version = "0.26.3", default-features = false, features = ["derive"] }
void = { version = "1.0.2", default-features = false }
usb-device = { version = "0.3.2", optional = true }
rand_core = "0.6.4"
ufmt-write = "0.1.0"
xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
@ -65,10 +63,14 @@ esp32s2 = { version = "0.25.0", features = ["critical-section", "rt"], optional
esp32s3 = { version = "0.29.0", features = ["critical-section", "rt"], optional = true }
[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.9.1", path = "../esp-riscv-rt" }
riscv = { version = "0.12.1" }
esp-riscv-rt = { version = "0.9.1", path = "../esp-riscv-rt" }
critical-section = { version = "1.2.0", features = ["restore-state-u8"] }
[target.'cfg(target_arch = "xtensa")'.dependencies]
xtensa-lx-rt = { version = "0.17.2", path = "../xtensa-lx-rt" }
xtensa-lx = { version = "0.9.0", path = "../xtensa-lx" }
xtensa-lx-rt = { version = "0.17.2", path = "../xtensa-lx-rt" }
critical-section = { version = "1.2.0", features = ["restore-state-u32"] }
[build-dependencies]
basic-toml = "0.1.9"
@ -81,9 +83,6 @@ serde = { version = "1.0.215", features = ["derive"] }
[features]
default = []
riscv = ["dep:riscv", "critical-section/restore-state-u8"]
xtensa = ["dep:xtensa-lx", "critical-section/restore-state-u32"]
bluetooth = []
usb-otg = ["dep:embassy-usb-driver", "dep:embassy-usb-synopsys-otg", "dep:esp-synopsys-usb-otg", "dep:usb-device"]
@ -105,19 +104,19 @@ log = ["dep:log"]
# Chip Support Feature Flags
# Target the ESP32.
esp32 = ["dep:esp32", "xtensa", "xtensa-lx/spin", "xtensa-lx-rt/esp32"]
esp32 = ["dep:esp32", "xtensa-lx-rt/esp32"]
# Target the ESP32-C2.
esp32c2 = ["dep:esp32c2", "riscv", "portable-atomic/unsafe-assume-single-core"]
esp32c2 = ["dep:esp32c2", "portable-atomic/unsafe-assume-single-core"]
# Target the ESP32-C3.
esp32c3 = ["dep:esp32c3", "riscv", "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
esp32c3 = ["dep:esp32c3", "portable-atomic/unsafe-assume-single-core", "esp-riscv-rt/rtc-ram"]
# Target the ESP32-C6.
esp32c6 = ["dep:esp32c6", "riscv", "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
esp32c6 = ["dep:esp32c6", "procmacros/has-lp-core", "esp-riscv-rt/rtc-ram"]
# Target the ESP32-H2.
esp32h2 = ["dep:esp32h2", "riscv", "esp-riscv-rt/rtc-ram"]
esp32h2 = ["dep:esp32h2", "esp-riscv-rt/rtc-ram"]
# Target the ESP32-S2.
esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
esp32s2 = ["dep:esp32s2", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
# Target the ESP32-S3.
esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx/spin", "xtensa-lx-rt/esp32s3", "usb-otg"]
esp32s3 = ["dep:esp32s3", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s3", "usb-otg"]
#! ### RISC-V Exclusive Feature Flags
## Move the stack to start of RAM to get zero-cost stack overflow protection

2
esp-hal/src/aes/esp32.rs
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@ -3,7 +3,7 @@ use crate::{
system::{Peripheral as PeripheralEnable, PeripheralClockControl},
};
impl<'d> Aes<'d> {
impl Aes<'_> {
pub(super) fn init(&mut self) {
PeripheralClockControl::enable(PeripheralEnable::Aes);
self.write_endianness(

9
esp-hal/src/aes/esp32s2.rs
View File

@ -3,7 +3,7 @@ use crate::{
system::{Peripheral as PeripheralEnable, PeripheralClockControl},
};
impl<'d> Aes<'d> {
impl Aes<'_> {
pub(super) fn init(&mut self) {
PeripheralClockControl::enable(PeripheralEnable::Aes);
self.write_dma(false);
@ -18,10 +18,9 @@ impl<'d> Aes<'d> {
}
fn write_dma(&mut self, enable_dma: bool) {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
};
self.aes
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}
pub(super) fn write_key(&mut self, key: &[u8]) {

9
esp-hal/src/aes/esp32s3.rs
View File

@ -3,17 +3,16 @@ use crate::{
system::{Peripheral as PeripheralEnable, PeripheralClockControl},
};
impl<'d> Aes<'d> {
impl Aes<'_> {
pub(super) fn init(&mut self) {
PeripheralClockControl::enable(PeripheralEnable::Aes);
self.write_dma(false);
}
fn write_dma(&mut self, enable_dma: bool) {
match enable_dma {
true => self.aes.dma_enable().write(|w| w.dma_enable().set_bit()),
false => self.aes.dma_enable().write(|w| w.dma_enable().clear_bit()),
};
self.aes
.dma_enable()
.write(|w| w.dma_enable().bit(enable_dma));
}
pub(super) fn write_key(&mut self, key: &[u8]) {

10
esp-hal/src/i2c/master/mod.rs
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@ -601,10 +601,6 @@ impl<'a> I2cFuture<'a> {
w.arbitration_lost().set_bit();
w.time_out().set_bit();
#[cfg(esp32)]
w.ack_err().set_bit();
#[cfg(not(esp32))]
w.nack().set_bit();
w
@ -635,16 +631,10 @@ impl<'a> I2cFuture<'a> {
return Err(Error::TimeOut);
}
#[cfg(not(esp32))]
if r.nack().bit_is_set() {
return Err(Error::AckCheckFailed);
}
#[cfg(esp32)]
if r.ack_err().bit_is_set() {
return Err(Error::AckCheckFailed);
}
#[cfg(not(esp32))]
if r.trans_complete().bit_is_set()
&& self

26
esp-hal/src/rsa/esp32sX.rs
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@ -44,16 +44,9 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
///
/// For more information refer to 20.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf>.
pub fn enable_disable_search_acceleration(&mut self, enable: bool) {
match enable {
true => self
.rsa
.search_enable()
.write(|w| w.search_enable().set_bit()),
false => self
.rsa
.search_enable()
.write(|w| w.search_enable().clear_bit()),
};
self.rsa
.search_enable()
.write(|w| w.search_enable().bit(enable));
}
/// Checks if the search functionality is enabled in the RSA hardware.
@ -79,16 +72,9 @@ impl<'d, DM: crate::Mode> Rsa<'d, DM> {
///
/// For more information refer to 20.3.4 of <https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf>.
pub fn enable_disable_constant_time_acceleration(&mut self, enable: bool) {
match enable {
true => self
.rsa
.constant_time()
.write(|w| w.constant_time().clear_bit()),
false => self
.rsa
.constant_time()
.write(|w| w.constant_time().set_bit()),
};
self.rsa
.constant_time()
.write(|w| w.constant_time().bit(!enable));
}
/// Starts the modular exponentiation operation.

31
esp-hal/src/soc/esp32s3/psram.rs
View File

@ -685,7 +685,7 @@ pub(crate) mod utils {
#[ram]
fn psram_set_cs_timing() {
unsafe {
let spi = &*crate::peripherals::SPI0::PTR;
let spi = crate::peripherals::SPI0::steal();
// SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers
// for PSRAM, so we only need to set SPI0 related registers here
spi.spi_smem_ac()
@ -705,8 +705,7 @@ pub(crate) mod utils {
let cs1_io: u8 = PSRAM_CS_IO;
if cs1_io == SPI_CS1_GPIO_NUM {
unsafe {
let iomux = &*esp32s3::IO_MUX::PTR;
iomux
esp32s3::IO_MUX::steal()
.gpio(cs1_io as usize)
.modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1));
}
@ -714,8 +713,7 @@ pub(crate) mod utils {
unsafe {
esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, false, false);
let iomux = &*esp32s3::IO_MUX::PTR;
iomux
esp32s3::IO_MUX::steal()
.gpio(cs1_io as usize)
.modify(|_, w| w.mcu_sel().bits(PIN_FUNC_GPIO));
}
@ -1105,7 +1103,7 @@ pub(crate) mod utils {
// requirement
fn config_psram_spi_phases() {
unsafe {
let spi = &*crate::peripherals::SPI0::PTR;
let spi = crate::peripherals::SPI0::steal();
// Config Write CMD phase for SPI0 to access PSRAM
spi.cache_sctrl()
.modify(|_, w| w.cache_sram_usr_wcmd().set_bit());
@ -1163,7 +1161,7 @@ pub(crate) mod utils {
#[ram]
fn spi_flash_set_rom_required_regs() {
// Disable the variable dummy mode when doing timing tuning
let spi = unsafe { &*crate::peripherals::SPI1::PTR };
let spi = unsafe { crate::peripherals::SPI1::steal() };
spi.ddr().modify(|_, w| w.spi_fmem_var_dummy().clear_bit());
// STR /DTR mode setting is done every time when
// `esp_rom_opiflash_exec_cmd` is called
@ -1174,9 +1172,7 @@ pub(crate) mod utils {
#[ram]
fn mspi_pin_init() {
unsafe {
esp_rom_opiflash_pin_config();
}
unsafe { esp_rom_opiflash_pin_config() };
spi_timing_set_pin_drive_strength();
// Set F4R4 board pin drive strength. TODO: IDF-3663
}
@ -1186,7 +1182,7 @@ pub(crate) mod utils {
// For now, set them all to 3. Need to check after QVL test results are out.
// TODO: IDF-3663 Set default clk
unsafe {
let spi = &*crate::peripherals::SPI0::PTR;
let spi = crate::peripherals::SPI0::steal();
spi.date()
.modify(|_, w| w.spi_spiclk_pad_drv_ctl_en().set_bit());
@ -1196,10 +1192,11 @@ pub(crate) mod utils {
.modify(|_, w| w.spi_fmem_spiclk_fun_drv().bits(3));
// Set default mspi d0 ~ d7, dqs pin drive strength
let pins = &[27usize, 28, 31, 32, 33, 34, 35, 36, 37];
let pins = [27usize, 28, 31, 32, 33, 34, 35, 36, 37];
for pin in pins {
let iomux = &*esp32s3::IO_MUX::PTR;
iomux.gpio(*pin).modify(|_, w| w.fun_drv().bits(3));
esp32s3::IO_MUX::steal()
.gpio(pin)
.modify(|_, w| w.fun_drv().bits(3));
}
}
}
@ -1284,16 +1281,14 @@ pub(crate) mod utils {
fn init_psram_pins() {
// Set cs1 pin function
unsafe {
let iomux = &*esp32s3::IO_MUX::PTR;
iomux
esp32s3::IO_MUX::steal()
.gpio(OCT_PSRAM_CS1_IO as usize)
.modify(|_, w| w.mcu_sel().bits(FUNC_SPICS1_SPICS1));
}
// Set mspi cs1 drive strength
unsafe {
let iomux = &*esp32s3::IO_MUX::PTR;
iomux
esp32s3::IO_MUX::steal()
.gpio(OCT_PSRAM_CS1_IO as usize)
.modify(|_, w| w.fun_drv().bits(3));
}

2
xtensa-lx-rt/Cargo.toml
View File

@ -17,7 +17,7 @@ bare-metal = "1.0.0"
document-features = "0.2.10"
macros = { version = "0.2.2", package = "xtensa-lx-rt-proc-macros", path = "./procmacros" }
r0 = "1.0.0"
xtensa-lx = "0.9.0"
xtensa-lx = { version = "0.9.0", path = "../xtensa-lx" }
[build-dependencies]
anyhow = "1.0.89"

8
xtensa-lx/README.md
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@ -5,13 +5,7 @@
![Crates.io](https://img.shields.io/crates/l/xtensa-lx?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
Low level access to Xtensa LX processors. This crate currently supports the following CPUs:
| Feature | Supported CPUs |
| --------- | ---------------- |
| `esp32` | ESP32 (_LX6_) |
| `esp32s2` | ESP32-S2 (_LX7_) |
| `esp32s3` | ESP32-S3 (_LX7_) |
Low level access to Xtensa LX processors.
## [Documentation](https://docs.rs/crate/xtensa-lx)

9
xtensa-lx/build.rs
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@ -1,6 +1,3 @@
use std::{env, path::PathBuf};
fn main() {
let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out_dir.display());
}
// We can't remove build.rs because our Cargo.toml contains the `links` key.
// directive.
fn main() {}