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Updates for Xtensa enabled 1.83 compiler (#2615)

Browse Source 
* test ci

* fix ci with new compiler

* god bless clippy fix

* refmuts

* clippy

* tests work

* use new compiler

* use new compiler

* bump MSRV of esp-hal and crates that depend on esp-hal

* fix eyesore

* clippy again

* remove hardcoded compiler version

* bump rust-version as well

* note MSRV bump in changelog
This commit is contained in:
Scott Mabin 2024-12-17 15:02:03 +00:00 committed by GitHub
parent a12e7fece1
commit 85d30e9816
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GPG Key ID: B5690EEEBB952194
39 changed files with 809 additions and 846 deletions
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2
.github/workflows/ci.yml vendored
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@ -23,7 +23,7 @@ on:
env:
CARGO_TERM_COLOR: always
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
MSRV: "1.79.0"
MSRV: "1.83.0"
RUSTDOCFLAGS: -Dwarnings
DEFMT_LOG: trace

3
esp-hal-embassy/CHANGELOG.md
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@ -7,10 +7,13 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
## [Unreleased]
### Added
### Changed
- Bump MSRV to 1.83 (#2615)
### Fixed
### Removed

2
esp-hal-embassy/Cargo.toml
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@ -2,7 +2,7 @@
name = "esp-hal-embassy"
version = "0.5.0"
edition = "2021"
rust-version = "1.79.0"
rust-version = "1.83.0"
description = "Embassy support for esp-hal"
repository = "https://github.com/esp-rs/esp-hal"
license = "MIT OR Apache-2.0"

4
esp-hal-embassy/README.md
View File

@ -2,7 +2,7 @@
[![Crates.io](https://img.shields.io/crates/v/esp-hal-embassy?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-hal-embassy)
[![docs.rs](https://img.shields.io/docsrs/esp-hal-embassy?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-hal-embassy)
![MSRV](https://img.shields.io/badge/MSRV-1.76-blue?labelColor=1C2C2E&style=flat-square)
![MSRV](https://img.shields.io/badge/MSRV-1.83-blue?labelColor=1C2C2E&style=flat-square)
![Crates.io](https://img.shields.io/crates/l/esp-hal-embassy?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
@ -18,7 +18,7 @@ Note that this crate currently requires you to enable the `unstable` feature on
## Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.79 and up. It _might_
This crate is guaranteed to compile on stable Rust 1.83 and up. It _might_
compile with older versions but that may change in any new patch release.
## License

2
esp-hal-procmacros/Cargo.toml
View File

@ -2,7 +2,7 @@
name = "esp-hal-procmacros"
version = "0.15.0"
edition = "2021"
rust-version = "1.76.0"
rust-version = "1.83.0"
description = "Procedural macros for esp-hal"
repository = "https://github.com/esp-rs/esp-hal"
license = "MIT OR Apache-2.0"

4
esp-hal/CHANGELOG.md
View File

@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
## [Unreleased]
### Added
- ESP32-S3: Added SDMMC signals (#2556)
@ -35,6 +36,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Changed
- Bump MSRV to 1.83 (#2615)
- In addition to taking by value, peripheral drivers can now mutably borrow DMA channel objects. (#2526)
- DMA channel objects are no longer wrapped in `Channel`. The `Channel` drivers are now managed by DMA enabled peripheral drivers. (#2526)
- The `Dpi` driver and `DpiTransfer` now have a `Mode` type parameter. The driver's asyncness is determined by the asyncness of the `Lcd` used to create it. (#2526)
@ -200,8 +202,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
## [0.21.0]
- Bump MSRV to 1.79.0 (#1971)
### Added
- Introduce traits for the DMA buffer objects (#1976, #2213)

2
esp-hal/Cargo.toml
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@ -2,7 +2,7 @@
name = "esp-hal"
version = "0.22.0"
edition = "2021"
rust-version = "1.79.0"
rust-version = "1.83.0"
description = "Bare-metal HAL for Espressif devices"
documentation = "https://docs.esp-rs.org/esp-hal/"
repository = "https://github.com/esp-rs/esp-hal"

4
esp-hal/README.md
View File

@ -2,7 +2,7 @@
[![Crates.io](https://img.shields.io/crates/v/esp-hal?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-hal)
[![docs.rs](https://img.shields.io/docsrs/esp-hal?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.esp-rs.org/esp-hal)
![MSRV](https://img.shields.io/badge/MSRV-1.76-blue?labelColor=1C2C2E&style=flat-square)
![MSRV](https://img.shields.io/badge/MSRV-1.83-blue?labelColor=1C2C2E&style=flat-square)
![Crates.io](https://img.shields.io/crates/l/esp-hal?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
@ -48,7 +48,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
## Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.79 and up. It _might_
This crate is guaranteed to compile on stable Rust 1.83 and up. It _might_
compile with older versions but that may change in any new patch release.
## License

2
esp-hal/src/analog/adc/esp32.rs
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@ -327,7 +327,7 @@ where
}
}
impl<'d, ADC1> Adc<'d, ADC1> {
impl<ADC1> Adc<'_, ADC1> {
/// Enable the Hall sensor
pub fn enable_hall_sensor() {
unsafe { &*RTC_IO::ptr() }

2
esp-hal/src/assist_debug.rs
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@ -391,7 +391,7 @@ impl DebugAssist<'_> {
}
#[cfg(all(assist_debug_region_monitor, multi_core))]
impl<'d> DebugAssist<'d> {
impl DebugAssist<'_> {
/// Enable region monitoring of read/write performed by the secondary CPU in
/// a certain memory region0. Whenever the bus reads or writes in the
/// specified memory region, an interrupt will be triggered.

4
esp-hal/src/dma/mod.rs
View File

@ -1892,7 +1892,7 @@ where
}
}
impl<'a, M, CH> ChannelRx<'a, M, CH>
impl<M, CH> ChannelRx<'_, M, CH>
where
M: Mode,
CH: DmaRxChannel,
@ -2186,7 +2186,7 @@ where
}
}
impl<'a, M, CH> ChannelTx<'a, M, CH>
impl<M, CH> ChannelTx<'_, M, CH>
where
M: Mode,
CH: DmaTxChannel,

2
esp-hal/src/dma/pdma/mod.rs
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@ -194,7 +194,7 @@ pub(super) fn init_dma(_cs: CriticalSection<'_>) {
}
}
impl<'d, CH, M> Channel<'d, M, CH>
impl<CH, M> Channel<'_, M, CH>
where
CH: DmaChannel,
M: Mode,

2
esp-hal/src/gpio/mod.rs
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@ -2459,7 +2459,7 @@ mod asynch {
pin: Flex<'d, P>,
}
impl<'d, P: InputPin> PinFuture<'d, P> {
impl<P: InputPin> PinFuture<'_, P> {
fn pin_mask(&self) -> u32 {
let bank = self.pin.gpio_bank(private::Internal);
1 << (self.pin.number() - bank.offset())

6
esp-hal/src/i2s/parallel.rs
View File

@ -401,7 +401,7 @@ where
}
}
impl<'d, I, BUF, DM> Deref for I2sParallelTransfer<'d, BUF, DM, I>
impl<I, BUF, DM> Deref for I2sParallelTransfer<'_, BUF, DM, I>
where
I: Instance,
BUF: DmaTxBuffer,
@ -414,7 +414,7 @@ where
}
}
impl<'d, I, BUF, DM> DerefMut for I2sParallelTransfer<'d, BUF, DM, I>
impl<I, BUF, DM> DerefMut for I2sParallelTransfer<'_, BUF, DM, I>
where
I: Instance,
BUF: DmaTxBuffer,
@ -425,7 +425,7 @@ where
}
}
impl<'d, I, BUF, DM> Drop for I2sParallelTransfer<'d, BUF, DM, I>
impl<I, BUF, DM> Drop for I2sParallelTransfer<'_, BUF, DM, I>
where
I: Instance,
BUF: DmaTxBuffer,

6
esp-hal/src/lcd_cam/cam.rs
View File

@ -432,7 +432,7 @@ impl<'d, BUF: DmaRxBuffer> CameraTransfer<'d, BUF> {
}
}
impl<'d, BUF: DmaRxBuffer> Deref for CameraTransfer<'d, BUF> {
impl<BUF: DmaRxBuffer> Deref for CameraTransfer<'_, BUF> {
type Target = BUF::View;
fn deref(&self) -> &Self::Target {
@ -440,13 +440,13 @@ impl<'d, BUF: DmaRxBuffer> Deref for CameraTransfer<'d, BUF> {
}
}
impl<'d, BUF: DmaRxBuffer> DerefMut for CameraTransfer<'d, BUF> {
impl<BUF: DmaRxBuffer> DerefMut for CameraTransfer<'_, BUF> {
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.buffer_view
}
}
impl<'d, BUF: DmaRxBuffer> Drop for CameraTransfer<'d, BUF> {
impl<BUF: DmaRxBuffer> Drop for CameraTransfer<'_, BUF> {
fn drop(&mut self) {
self.stop_peripherals();

6
esp-hal/src/lcd_cam/lcd/dpi.rs
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@ -661,7 +661,7 @@ impl<'d, BUF: DmaTxBuffer, DM: Mode> DpiTransfer<'d, BUF, DM> {
}
}
impl<'d, BUF: DmaTxBuffer, DM: Mode> Deref for DpiTransfer<'d, BUF, DM> {
impl<BUF: DmaTxBuffer, DM: Mode> Deref for DpiTransfer<'_, BUF, DM> {
type Target = BUF::View;
fn deref(&self) -> &Self::Target {
@ -669,13 +669,13 @@ impl<'d, BUF: DmaTxBuffer, DM: Mode> Deref for DpiTransfer<'d, BUF, DM> {
}
}
impl<'d, BUF: DmaTxBuffer, DM: Mode> DerefMut for DpiTransfer<'d, BUF, DM> {
impl<BUF: DmaTxBuffer, DM: Mode> DerefMut for DpiTransfer<'_, BUF, DM> {
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.buffer_view
}
}
impl<'d, BUF: DmaTxBuffer, DM: Mode> Drop for DpiTransfer<'d, BUF, DM> {
impl<BUF: DmaTxBuffer, DM: Mode> Drop for DpiTransfer<'_, BUF, DM> {
fn drop(&mut self) {
self.stop_peripherals();

12
esp-hal/src/lcd_cam/lcd/i8080.rs
View File

@ -396,7 +396,7 @@ where
}
}
impl<'d, DM: Mode> core::fmt::Debug for I8080<'d, DM> {
impl<DM: Mode> core::fmt::Debug for I8080<'_, DM> {
fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result {
f.debug_struct("I8080").finish()
}
@ -470,7 +470,7 @@ impl<'d, BUF: DmaTxBuffer, DM: Mode> I8080Transfer<'d, BUF, DM> {
}
}
impl<'d, BUF: DmaTxBuffer, DM: Mode> Deref for I8080Transfer<'d, BUF, DM> {
impl<BUF: DmaTxBuffer, DM: Mode> Deref for I8080Transfer<'_, BUF, DM> {
type Target = BUF::View;
fn deref(&self) -> &Self::Target {
@ -478,7 +478,7 @@ impl<'d, BUF: DmaTxBuffer, DM: Mode> Deref for I8080Transfer<'d, BUF, DM> {
}
}
impl<'d, BUF: DmaTxBuffer, DM: Mode> DerefMut for I8080Transfer<'d, BUF, DM> {
impl<BUF: DmaTxBuffer, DM: Mode> DerefMut for I8080Transfer<'_, BUF, DM> {
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.buf_view
}
@ -523,7 +523,7 @@ impl<'d, BUF: DmaTxBuffer> I8080Transfer<'d, BUF, crate::Async> {
}
}
impl<'d, BUF: DmaTxBuffer, DM: Mode> Drop for I8080Transfer<'d, BUF, DM> {
impl<BUF: DmaTxBuffer, DM: Mode> Drop for I8080Transfer<'_, BUF, DM> {
fn drop(&mut self) {
self.stop_peripherals();
@ -645,7 +645,7 @@ impl<'d> TxEightBits<'d> {
}
}
impl<'d> TxPins for TxEightBits<'d> {
impl TxPins for TxEightBits<'_> {
fn configure(&mut self) {
const SIGNALS: [OutputSignal; 8] = [
OutputSignal::LCD_DATA_0,
@ -706,7 +706,7 @@ impl<'d> TxSixteenBits<'d> {
}
}
impl<'d> TxPins for TxSixteenBits<'d> {
impl TxPins for TxSixteenBits<'_> {
fn configure(&mut self) {
const SIGNALS: [OutputSignal; 16] = [
OutputSignal::LCD_DATA_0,

2
esp-hal/src/ledc/timer.rs
View File

@ -369,7 +369,7 @@ impl TimerHW<LowSpeed> for Timer<'_, LowSpeed> {
#[cfg(esp32)]
/// Timer HW implementation for HighSpeed timers
impl<'a> TimerHW<HighSpeed> for Timer<'a, HighSpeed> {
impl TimerHW<HighSpeed> for Timer<'_, HighSpeed> {
/// Get the current source timer frequency from the HW
fn freq_hw(&self) -> Option<HertzU32> {
self.clock_source.map(|source| match source {

8
esp-hal/src/otg_fs.rs
View File

@ -109,9 +109,9 @@ impl<'d> Usb<'d> {
}
}
unsafe impl<'d> Sync for Usb<'d> {}
unsafe impl Sync for Usb<'_> {}
unsafe impl<'d> UsbPeripheral for Usb<'d> {
unsafe impl UsbPeripheral for Usb<'_> {
const REGISTERS: *const () = peripherals::USB0::ptr() as *const ();
const HIGH_SPEED: bool = false;
@ -250,7 +250,7 @@ pub mod asynch {
_usb: Usb<'d>,
}
impl<'d> Bus<'d> {
impl Bus<'_> {
fn init(&mut self) {
Usb::_enable();
@ -328,7 +328,7 @@ pub mod asynch {
}
}
impl<'d> Drop for Bus<'d> {
impl Drop for Bus<'_> {
fn drop(&mut self) {
Bus::disable(self);
}

8
esp-hal/src/rsa/esp32.rs
View File

@ -10,7 +10,7 @@ use crate::rsa::{
RsaMultiplication,
};
impl<'d, DM: crate::Mode> Rsa<'d, DM> {
impl<DM: crate::Mode> Rsa<'_, DM> {
/// After the RSA Accelerator is released from reset, the memory blocks
/// needs to be initialized, only after that peripheral should be used.
/// This function would return without an error if the memory is initialized
@ -79,7 +79,7 @@ pub mod operand_sizes {
);
}
impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'a, 'd, T, DM>
impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'_, 'd, T, DM>
where
T: RsaMode<InputType = [u32; N]>,
{
@ -98,7 +98,7 @@ where
}
}
impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'a, 'd, T, DM>
impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'_, 'd, T, DM>
where
T: RsaMode<InputType = [u32; N]>,
{
@ -108,7 +108,7 @@ where
}
}
impl<'a, 'd, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'a, 'd, T, DM>
impl<'d, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'_, 'd, T, DM>
where
T: RsaMode<InputType = [u32; N]>,
{

8
esp-hal/src/rsa/esp32sX.rs
View File

@ -10,7 +10,7 @@ use crate::rsa::{
RsaMultiplication,
};
impl<'d, DM: crate::Mode> Rsa<'d, DM> {
impl<DM: crate::Mode> Rsa<'_, DM> {
/// After the RSA accelerator is released from reset, the memory blocks
/// needs to be initialized, only after that peripheral should be used.
/// This function would return without an error if the memory is
@ -248,7 +248,7 @@ pub mod operand_sizes {
);
}
impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'a, 'd, T, DM>
impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularExponentiation<'_, 'd, T, DM>
where
T: RsaMode<InputType = [u32; N]>,
{
@ -268,7 +268,7 @@ where
}
}
impl<'a, 'd, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'a, 'd, T, DM>
impl<'d, T: RsaMode, DM: crate::Mode, const N: usize> RsaModularMultiplication<'_, 'd, T, DM>
where
T: RsaMode<InputType = [u32; N]>,
{
@ -281,7 +281,7 @@ where
}
}
impl<'a, 'd, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'a, 'd, T, DM>
impl<'d, T: RsaMode + Multi, DM: crate::Mode, const N: usize> RsaMultiplication<'_, 'd, T, DM>
where
T: RsaMode<InputType = [u32; N]>,
{

2
esp-hal/src/rtc_cntl/sleep/esp32s3.rs
View File

@ -234,7 +234,7 @@ impl Drop for Ext1WakeupSource<'_, '_> {
}
}
impl<'a, 'b> RtcioWakeupSource<'a, 'b> {
impl RtcioWakeupSource<'_, '_> {
fn apply_pin(&self, pin: &mut dyn RtcPin, level: WakeupLevel) {
let rtcio = unsafe { &*crate::peripherals::RTC_IO::PTR };

3
esp-hal/src/soc/esp32/cpu_control.rs
View File

@ -127,7 +127,7 @@ pub struct AppCoreGuard<'a> {
phantom: PhantomData<&'a ()>,
}
impl<'a> Drop for AppCoreGuard<'a> {
impl Drop for AppCoreGuard<'_> {
fn drop(&mut self) {
unsafe {
internal_park_core(Cpu::AppCpu);
@ -323,6 +323,7 @@ impl<'d> CpuControl<'d> {
where
F: FnOnce(),
{
#[allow(static_mut_refs)] // FIXME
match START_CORE1_FUNCTION.take() {
Some(entry) => {
let entry = unsafe { ManuallyDrop::take(&mut *entry.cast::<ManuallyDrop<F>>()) };

3
esp-hal/src/soc/esp32s3/cpu_control.rs
View File

@ -127,7 +127,7 @@ pub struct AppCoreGuard<'a> {
phantom: PhantomData<&'a ()>,
}
impl<'a> Drop for AppCoreGuard<'a> {
impl Drop for AppCoreGuard<'_> {
fn drop(&mut self) {
unsafe {
internal_park_core(Cpu::AppCpu);
@ -259,6 +259,7 @@ impl<'d> CpuControl<'d> {
where
F: FnOnce(),
{
#[allow(static_mut_refs)] // FIXME
match START_CORE1_FUNCTION.take() {
Some(entry) => {
let entry = unsafe { ManuallyDrop::take(&mut *entry.cast::<ManuallyDrop<F>>()) };

1
esp-hal/src/soc/mod.rs
View File

@ -30,6 +30,7 @@ static mut MAPPED_PSRAM: MappedPsram = MappedPsram { memory_range: 0..0 };
pub(crate) fn psram_range() -> Range<usize> {
cfg_if::cfg_if! {
if #[cfg(any(feature = "quad-psram", feature = "octal-psram"))] {
#[allow(static_mut_refs)]
unsafe { MAPPED_PSRAM.memory_range.clone() }
} else {
0..0

2
esp-hal/src/spi/slave.rs
View File

@ -315,7 +315,7 @@ pub mod dma {
}
}
impl<'d, M, T> SpiDma<'d, M, T>
impl<M, T> SpiDma<'_, M, T>
where
M: Mode,
T: InstanceDma,

6
esp-hal/src/timer/mod.rs
View File

@ -155,7 +155,7 @@ where
}
}
impl<'d, T> OneShotTimer<'d, Async, T>
impl<T> OneShotTimer<'_, Async, T>
where
T: Timer,
{
@ -197,7 +197,7 @@ where
}
}
impl<'d, M, T> OneShotTimer<'d, M, T>
impl<M, T> OneShotTimer<'_, M, T>
where
M: Mode,
T: Timer,
@ -329,7 +329,7 @@ where
}
}
impl<'d, M, T> PeriodicTimer<'d, M, T>
impl<M, T> PeriodicTimer<'_, M, T>
where
M: Mode,
T: Timer,

2
esp-hal/src/touch.rs
View File

@ -90,7 +90,7 @@ pub struct Touch<'d, TOUCHMODE: TouchMode, MODE: Mode> {
_touch_mode: PhantomData<TOUCHMODE>,
_mode: PhantomData<MODE>,
}
impl<'d, TOUCHMODE: TouchMode, MODE: Mode> Touch<'d, TOUCHMODE, MODE> {
impl<TOUCHMODE: TouchMode, MODE: Mode> Touch<'_, TOUCHMODE, MODE> {
/// Common initialization of the touch peripheral.
fn initialize_common(config: Option<TouchConfig>) {
let rtccntl = unsafe { &*RTC_CNTL::ptr() };

3
esp-ieee802154/CHANGELOG.md
View File

@ -7,10 +7,13 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
## [Unreleased]
### Added
### Changed
- Bump MSRV to 1.83 (#2615)
### Fixed
### Removed

2
esp-ieee802154/Cargo.toml
View File

@ -2,7 +2,7 @@
name = "esp-ieee802154"
version = "0.4.0"
edition = "2021"
rust-version = "1.76.0"
rust-version = "1.83.0"
description = "Low-level IEEE 802.15.4 driver for the ESP32-C6 and ESP32-H2"
repository = "https://github.com/esp-rs/esp-hal"
license = "MIT OR Apache-2.0"

4
esp-ieee802154/README.md
View File

@ -2,7 +2,7 @@
[![Crates.io](https://img.shields.io/crates/v/esp-ieee802154?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-ieee802154)
[![docs.rs](https://img.shields.io/docsrs/esp-ieee802154?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp-ieee802154)
![MSRV](https://img.shields.io/badge/MSRV-1.76-blue?labelColor=1C2C2E&style=flat-square)
![MSRV](https://img.shields.io/badge/MSRV-1.83-blue?labelColor=1C2C2E&style=flat-square)
![Crates.io](https://img.shields.io/crates/l/esp-ieee802154?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
@ -16,7 +16,7 @@ Implements the PHY/MAC layers of the IEEE802.15.4 protocol stack, and supports s
## Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.76 and up. It _might_
This crate is guaranteed to compile on stable Rust 1.83 and up. It _might_
compile with older versions but that may change in any new patch release.
## License

2
esp-println/src/lib.rs
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@ -478,7 +478,7 @@ type LockInner<'a> = critical_section::CriticalSection<'a>;
#[derive(Clone, Copy)]
struct LockToken<'a>(LockInner<'a>);
impl<'a> LockToken<'a> {
impl LockToken<'_> {
#[allow(unused)]
unsafe fn conjure() -> Self {
#[cfg(feature = "critical-section")]

4
esp-wifi/CHANGELOG.md
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@ -7,11 +7,15 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
## [Unreleased]
### Added
### Changed
- Bump MSRV to 1.83 (#2615)
### Fixed
- Fixed triggering a debug-assertion during scan (#2612)
### Removed

2
esp-wifi/Cargo.toml
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@ -2,7 +2,7 @@
name = "esp-wifi"
version = "0.11.0"
edition = "2021"
rust-version = "1.79.0"
rust-version = "1.83.0"
authors = ["The ESP-RS team"]
description = "A WiFi, Bluetooth and ESP-NOW driver for use with Espressif chips and bare-metal Rust"
documentation = "https://docs.esp-rs.org/esp-hal/"

7
esp-wifi/README.md
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@ -2,7 +2,7 @@
[![Crates.io](https://img.shields.io/crates/v/esp-wifi?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp-wifi)
[![docs.rs](https://img.shields.io/docsrs/esp-wifi?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.esp-rs.org/esp-hal)
![MSRV](https://img.shields.io/badge/MSRV-1.76-blue?labelColor=1C2C2E&style=flat-square)
![MSRV](https://img.shields.io/badge/MSRV-1.83-blue?labelColor=1C2C2E&style=flat-square)
![Crates.io](https://img.shields.io/crates/l/esp-wifi?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
@ -24,7 +24,10 @@ If a cell contains an em dash (&mdash;) this means that the particular feature i
| ESP32-S2 | ✓ | &mdash; | &mdash; | ✓ |
| ESP32-S3 | ✓ | ✓ | ✓ | ✓ |
Minimum supported Rust compiler version: 1.79.0
## Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.83 and up. It _might_
compile with older versions but that may change in any new patch release.
## Missing / To be done

2
xtask/src/main.rs
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@ -790,7 +790,7 @@ fn lint_package(chip: &Chip, path: &Path, args: &[&str], fix: bool) -> Result<()
// build in release to reuse example artifacts
let cargo_args = builder.arg("--release");
let cargo_args = if fix {
cargo_args.arg("--fix").arg("--lib")
cargo_args.arg("--fix").arg("--lib").arg("--allow-dirty")
} else {
cargo_args.arg("--").arg("-D").arg("warnings")
};

1207
xtensa-lx-rt/src/exception/asm.rs
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File diff suppressed because it is too large Load Diff

292
xtensa-lx-rt/src/exception/context.rs
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@ -1,5 +1,3 @@
use core::arch::asm;
use super::ExceptionCause;
/// State of the CPU saved when entering exception or interrupt
@ -161,293 +159,3 @@ extern "C" fn __default_interrupt(level: u32, save_frame: &Context) {
extern "C" fn __default_double_exception(cause: ExceptionCause, save_frame: &Context) {
panic!("Double Exception: {:?}, {:08x?}", cause, save_frame)
}
// Raw vector handlers
//
// The interrupt handlers all use special return instructions.
// rust still generates a ret.w instruction, which will never be reached.
// generation of the ret.w can be prevented by using
// core::intrinsics::unreachable, but then a break 15,1 will be generated (which
// takes 3 bytes instead of 2) or a 'loop {}', but then a jump to own address
// will be generated which is also 3 bytes. No way found yet to prevent this
// generation altogether.
#[naked]
#[no_mangle]
#[link_section = ".KernelExceptionVector.text"]
unsafe extern "C" fn _KernelExceptionVector() {
asm!(
"
wsr a0, EXCSAVE1 // preserve a0
rsr a0, EXCCAUSE // get exception cause
beqi a0, 5, .AllocAException
call0 __naked_kernel_exception
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".UserExceptionVector.text"]
unsafe extern "C" fn _UserExceptionVector() {
asm!(
"
wsr a0, EXCSAVE1 // preserve a0
rsr a0, EXCCAUSE // get exception cause
beqi a0, 5, .AllocAException
call0 __naked_user_exception
.AllocAException:
call0 _AllocAException
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".DoubleExceptionVector.text"]
unsafe extern "C" fn _DoubleExceptionVector() {
asm!(
"
wsr a0, EXCSAVE1 // preserve a0 (EXCSAVE1 can be reused as long as there
// is no double exception in the first exception until
// EXCSAVE1 is stored to the stack.)
call0 __naked_double_exception // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".Level2InterruptVector.text"]
unsafe extern "C" fn _Level2InterruptVector() {
asm!(
"
wsr a0, EXCSAVE2 // preserve a0
call0 __naked_level_2_interrupt // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".Level3InterruptVector.text"]
unsafe extern "C" fn _Level3InterruptVector() {
asm!(
"
wsr a0, EXCSAVE3 // preserve a0
call0 __naked_level_3_interrupt // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".Level4InterruptVector.text"]
unsafe extern "C" fn _Level4InterruptVector() {
asm!(
"
wsr a0, EXCSAVE4 // preserve a0
call0 __naked_level_4_interrupt // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".Level5InterruptVector.text"]
unsafe extern "C" fn _Level5InterruptVector() {
asm!(
"
wsr a0, EXCSAVE5 // preserve a0
call0 __naked_level_5_interrupt // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".DebugExceptionVector.text"]
unsafe extern "C" fn _Level6InterruptVector() {
asm!(
"
wsr a0, EXCSAVE6 // preserve a0
call0 __naked_level_6_interrupt // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".NMIExceptionVector.text"]
unsafe extern "C" fn _Level7InterruptVector() {
asm!(
"
wsr a0, EXCSAVE7 // preserve a0
call0 __naked_level_7_interrupt // used as long jump
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".WindowOverflow4.text"]
unsafe extern "C" fn _WindowOverflow4() {
asm!(
"
s32e a0, a5, -16
s32e a1, a5, -12
s32e a2, a5, -8
s32e a3, a5, -4
rfwo
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".WindowUnderflow4.text"]
unsafe extern "C" fn _WindowUnderflow4() {
asm!(
"
l32e a0, a5, -16
l32e a1, a5, -12
l32e a2, a5, -8
l32e a3, a5, -4
rfwu
// inline the _AllocAException saves on the ret.w for WindowUnderflow4
// this makes that it just fits, which is needed for the bbci instructions
.align 4
_AllocAException:
rsr a0, WINDOWBASE // grab WINDOWBASE before rotw changes it
rotw -1 // WINDOWBASE goes to a4, new a0-a3 are scratch
rsr a2, PS
extui a3, a2, 8, 4 // XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
xor a3, a3, a4 // bits changed from old to current windowbase
rsr a4, EXCSAVE1 // restore original a0 (now in a4)
slli a3, a3, 8 // XCHAL_PS_OWB_SHIFT
xor a2, a2, a3 // flip changed bits in old window base
wsr a2, PS // update PS.OWB to new window base
rsync
bbci a4, 31, _WindowUnderflow4
rotw -1 // original a0 goes to a8
bbci a8, 30, _WindowUnderflow8
rotw -1
j _WindowUnderflow12
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".WindowOverflow8.text"]
unsafe extern "C" fn _WindowOverflow8() {
asm!(
"
s32e a0, a9, -16
l32e a0, a1, -12
s32e a1, a9, -12
s32e a2, a9, -8
s32e a3, a9, -4
s32e a4, a0, -32
s32e a5, a0, -28
s32e a6, a0, -24
s32e a7, a0, -20
rfwo
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".WindowUnderflow8.text"]
unsafe extern "C" fn _WindowUnderflow8() {
asm!(
"
l32e a0, a9, -16
l32e a1, a9, -12
l32e a2, a9, -8
l32e a7, a1, -12
l32e a3, a9, -4
l32e a4, a7, -32
l32e a5, a7, -28
l32e a6, a7, -24
l32e a7, a7, -20
rfwu
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".WindowOverflow12.text"]
unsafe extern "C" fn _WindowOverflow12() {
asm!(
"
s32e a0, a13, -16
l32e a0, a1, -12
s32e a1, a13, -12
s32e a2, a13, -8
s32e a3, a13, -4
s32e a4, a0, -48
s32e a5, a0, -44
s32e a6, a0, -40
s32e a7, a0, -36
s32e a8, a0, -32
s32e a9, a0, -28
s32e a10, a0, -24
s32e a11, a0, -20
rfwo
",
options(noreturn)
);
}
#[naked]
#[no_mangle]
#[link_section = ".WindowUnderflow12.text"]
unsafe extern "C" fn _WindowUnderflow12() {
asm!(
"
l32e a0, a13, -16
l32e a1, a13, -12
l32e a2, a13, -8
l32e a11, a1, -12
l32e a3, a13, -4
l32e a4, a11, -48
l32e a5, a11, -44
l32e a6, a11, -40
l32e a7, a11, -36
l32e a8, a11, -32
l32e a9, a11, -28
l32e a10, a11, -24
l32e a11, a11, -20
rfwu
",
options(noreturn)
);
}

20
xtensa-lx-rt/src/lib.rs
View File

@ -170,3 +170,23 @@ macro_rules! cfg_asm {
cfg_asm!(@inner, [], [$($opts)*], $($asms)*)
};
}
#[doc(hidden)]
#[macro_export]
macro_rules! cfg_global_asm {
{@inner, [$($x:tt)*], } => {
global_asm!{$($x)*}
};
(@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
#[cfg($meta)]
cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
#[cfg(not($meta))]
cfg_global_asm!{@inner, [$($x)*], $($rest)*}
};
{@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
};
{$($asms:tt)*} => {
cfg_global_asm!{@inner, [], $($asms)*}
};
}