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Enable C2 HIL (#1680)

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* ci: Enable c2 hil

* docs: Update pins and add C2

* feat: Update C2 probe-rs args

* test: Update pins and disable failing tests

* docs: Update S3 wires

* ci: Enable C2 hil tests
This commit is contained in:
Sergio Gasquez Arcos 2024-06-26 16:17:40 +02:00 committed by GitHub
parent c9925b7f6d
commit e46e80b8c1
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
15 changed files with 120 additions and 98 deletions
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4
.github/workflows/ci.yml vendored
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@ -333,6 +333,8 @@ jobs:
matrix:
target:
# RISC-V devices:
- soc: esp32c2
rust-target: riscv32imc-unknown-none-elf
- soc: esp32c3
rust-target: riscv32imc-unknown-none-elf
- soc: esp32c6
@ -362,4 +364,4 @@ jobs:
ldproxy: false
- uses: Swatinem/rust-cache@v2
- run: cargo xtask build-tests ${{ matrix.target.soc }}
- run: cargo xtask build-tests ${{ matrix.target.soc }}

4
.github/workflows/hil.yml vendored
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@ -27,6 +27,8 @@ jobs:
matrix:
target:
# RISC-V devices:
- soc: esp32c2
rust-target: riscv32imc-unknown-none-elf
- soc: esp32c3
rust-target: riscv32imc-unknown-none-elf
- soc: esp32c6
@ -99,6 +101,8 @@ jobs:
matrix:
target:
# RISC-V devices:
- soc: esp32c2
runner: esp32c2-jtag
- soc: esp32c3
runner: esp32c3-usb
- soc: esp32c6

19
hil-test/README.md
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@ -55,32 +55,39 @@ Some tests will require physical connections, please see the current [configurat
### Running Tests Remotes (ie. On Self-Hosted Runners)
The [`hil.yml`] workflow builds the test suite for all our available targets and executes them.
Our Virtual Machines have the following setup:
Our self hosted runners have the following setup:
- ESP32-C2 (`esp32c2-jtag`):
- Devkit: `ESP8684-DevKitM-1` connected via UART.
- `GPIO2` and `GPIO3` are connected.
- Probe: `ESP-Prog` connected with the [following connections](https://docs.espressif.com/projects/esp-idf/en/stable/esp32c2/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware)
- RPi: Raspbian 12 configured with the following [setup](#vm-setup)
- ESP32-C3 (`rustboard`):
- Devkit: `ESP32-C3-DevKit-RUST-1` connected via USB-Serial-JTAG.
- `GPIO2` and `GPIO4` are connected.
- `GPIO2` and `GPIO3` are connected.
- `GPIO5` and `GPIO6` are connected.
- RPi: Raspbian 12 configured with the following [setup](#vm-setup)
- ESP32-C6 (`esp32c6-usb`):
- Devkit: `ESP32-C6-DevKitC-1 V1.2` connected via USB-Serial-JTAG (`USB` port).
- `GPIO2` and `GPIO4` are connected.
- `GPIO2` and `GPIO3` are connected.
- `GPIO5` and `GPIO6` are connected.
- RPi: Raspbian 12 configured with the following [setup](#vm-setup)
- ESP32-H2 (`esp32h2-usb`):
- Devkit: `ESP32-H2-DevKitM-1` connected via USB-Serial-JTAG (`USB` port).
- `GPIO2` and `GPIO4` are connected.
- `GPIO2` and `GPIO3` are connected.
- `GPIO5` and `GPIO8` are connected.
- RPi: Raspbian 12 configured with the following [setup](#vm-setup)
- ESP32-S2 (`esp32s2-jtag`):
- Devkit: `ESP32-S2-Saola-1` connected via UART.
- `GPIO2` and `GPIO4` are connected.
- `GPIO2` and `GPIO3` are connected.
- `GPIO5` and `GPIO6` are connected.
- Probe: `ESP-Prog` connected with the [following connections](https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/configure-other-jtag.html#configure-hardware)
- RPi: Raspbian 12 configured with the following [setup](#vm-setup)
- ESP32-S3 (`esp32s3-usb`):
- Devkit: `ESP32-S3-DevKitC-1` connected via USB-Serial-JTAG.
- `GPIO2` and `GPIO4` are connected.
- `GPIO2` and `GPIO3` are connected.
- `GPIO5` and `GPIO6` are connected.
- `GPIO1` and `GPIO21` are connected.
- `GPIO43 (TX)` and `GPIO45` are connected.
- RPi: Raspbian 12 configured with the following [setup](#vm-setup)
[`hil.yml`]: https://github.com/esp-rs/esp-hal/blob/main/.github/workflows/hil.yml

3
hil-test/tests/delay.rs
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@ -1,6 +1,7 @@
//! Delay Test
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32s3
// esp32c2 is disabled currently as it fails
//% CHIPS: esp32 esp32c3 esp32c6 esp32s3
#![no_std]
#![no_main]

3
hil-test/tests/get_time.rs
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@ -1,6 +1,7 @@
//! current_time Test
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
// esp32c2 is disabled currently as it fails
//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
#![no_std]
#![no_main]

100
hil-test/tests/gpio.rs
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@ -2,7 +2,7 @@
//!
//! Folowing pins are used:
//! GPIO2
//! GPIO4
//! GPIO3
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -17,7 +17,7 @@ use esp_backtrace as _;
use esp_hal::{
clock::ClockControl,
delay::Delay,
gpio::{Gpio2, Gpio4, GpioPin, Input, Io, Level, Output, Pull},
gpio::{Gpio2, Gpio3, GpioPin, Input, Io, Level, Output, Pull},
macros::handler,
peripherals::Peripherals,
system::SystemControl,
@ -29,7 +29,7 @@ static INPUT_PIN: Mutex<RefCell<Option<Input<'static, Gpio2>>>> = Mutex::new(Ref
struct Context<'d> {
io2: Input<'d, Gpio2>,
io4: Output<'d, Gpio4>,
io3: Output<'d, Gpio3>,
delay: Delay,
}
@ -49,7 +49,7 @@ impl<'d> Context<'d> {
Context {
io2: Input::new(io.pins.gpio2, Pull::Down),
io4: Output::new(io.pins.gpio4, Level::Low),
io3: Output::new(io.pins.gpio3, Level::Low),
delay,
}
}
@ -80,7 +80,7 @@ mod tests {
fn init() -> Context<'static> {
let mut ctx = Context::init();
// make sure tests don't interfere with each other
ctx.io4.set_low();
ctx.io3.set_low();
ctx
}
@ -88,7 +88,7 @@ mod tests {
async fn test_async_edge(ctx: Context<'static>) {
let counter = AtomicUsize::new(0);
let Context {
mut io2, mut io4, ..
mut io2, mut io3, ..
} = ctx;
embassy_futures::select::select(
async {
@ -99,9 +99,9 @@ mod tests {
},
async {
for _ in 0..5 {
io4.set_high();
io3.set_high();
Timer::after(Duration::from_millis(25)).await;
io4.set_low();
io3.set_low();
Timer::after(Duration::from_millis(25)).await;
}
},
@ -133,19 +133,19 @@ mod tests {
#[test]
fn test_gpio_output(mut ctx: Context<'static>) {
// `StatefulOutputPin`:
assert_eq!(ctx.io4.is_set_low(), true);
assert_eq!(ctx.io4.is_set_high(), false);
ctx.io4.set_high();
assert_eq!(ctx.io4.is_set_low(), false);
assert_eq!(ctx.io4.is_set_high(), true);
assert_eq!(ctx.io3.is_set_low(), true);
assert_eq!(ctx.io3.is_set_high(), false);
ctx.io3.set_high();
assert_eq!(ctx.io3.is_set_low(), false);
assert_eq!(ctx.io3.is_set_high(), true);
// `ToggleableOutputPin`:
ctx.io4.toggle();
assert_eq!(ctx.io4.is_set_low(), true);
assert_eq!(ctx.io4.is_set_high(), false);
ctx.io4.toggle();
assert_eq!(ctx.io4.is_set_low(), false);
assert_eq!(ctx.io4.is_set_high(), true);
ctx.io3.toggle();
assert_eq!(ctx.io3.is_set_low(), true);
assert_eq!(ctx.io3.is_set_high(), false);
ctx.io3.toggle();
assert_eq!(ctx.io3.is_set_low(), false);
assert_eq!(ctx.io3.is_set_high(), true);
}
#[test]
@ -155,23 +155,23 @@ mod tests {
ctx.io2.listen(Event::AnyEdge);
INPUT_PIN.borrow_ref_mut(cs).replace(ctx.io2);
});
ctx.io4.set_high();
ctx.io3.set_high();
ctx.delay.delay_millis(1);
ctx.io4.set_low();
ctx.io3.set_low();
ctx.delay.delay_millis(1);
ctx.io4.set_high();
ctx.io3.set_high();
ctx.delay.delay_millis(1);
ctx.io4.set_low();
ctx.io3.set_low();
ctx.delay.delay_millis(1);
ctx.io4.set_high();
ctx.io3.set_high();
ctx.delay.delay_millis(1);
ctx.io4.set_low();
ctx.io3.set_low();
ctx.delay.delay_millis(1);
ctx.io4.set_high();
ctx.io3.set_high();
ctx.delay.delay_millis(1);
ctx.io4.set_low();
ctx.io3.set_low();
ctx.delay.delay_millis(1);
ctx.io4.set_high();
ctx.io3.set_high();
ctx.delay.delay_millis(1);
let count = critical_section::with(|cs| *COUNTER.borrow_ref(cs));
@ -184,86 +184,86 @@ mod tests {
#[test]
fn test_gpio_od(ctx: Context<'static>) {
let mut io2 = OutputOpenDrain::new(unsafe { GpioPin::<2>::steal() }, Level::High, Pull::Up);
let mut io4 = OutputOpenDrain::new(unsafe { GpioPin::<4>::steal() }, Level::High, Pull::Up);
let mut io3 = OutputOpenDrain::new(unsafe { GpioPin::<3>::steal() }, Level::High, Pull::Up);
ctx.delay.delay_millis(1);
assert_eq!(io2.is_high(), true);
assert_eq!(io4.is_high(), true);
assert_eq!(io3.is_high(), true);
io2.set_low();
io4.set_high();
io3.set_high();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_low(), true);
assert_eq!(io4.is_low(), true);
assert_eq!(io3.is_low(), true);
io2.set_high();
io4.set_high();
io3.set_high();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_high(), true);
assert_eq!(io4.is_high(), true);
assert_eq!(io3.is_high(), true);
io2.set_high();
io4.set_low();
io3.set_low();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_low(), true);
assert_eq!(io4.is_low(), true);
assert_eq!(io3.is_low(), true);
io2.set_high();
io4.set_high();
io3.set_high();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_high(), true);
assert_eq!(io4.is_high(), true);
assert_eq!(io3.is_high(), true);
io2.set_low();
io4.set_low();
io3.set_low();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_low(), true);
assert_eq!(io4.is_low(), true);
assert_eq!(io3.is_low(), true);
}
#[test]
fn test_gpio_flex(ctx: Context<'static>) {
let mut io2 = Flex::new(unsafe { GpioPin::<2>::steal() });
let mut io4 = Flex::new(unsafe { GpioPin::<4>::steal() });
let mut io3 = Flex::new(unsafe { GpioPin::<3>::steal() });
io2.set_high();
io2.set_as_output();
io4.set_as_input(Pull::None);
io3.set_as_input(Pull::None);
ctx.delay.delay_millis(1);
assert_eq!(io2.is_set_high(), true);
assert_eq!(io4.is_high(), true);
assert_eq!(io3.is_high(), true);
io2.set_low();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_set_high(), false);
assert_eq!(io4.is_high(), false);
assert_eq!(io3.is_high(), false);
io2.set_as_input(Pull::None);
io4.set_as_output();
io3.set_as_output();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_high(), false);
assert_eq!(io4.is_set_high(), false);
assert_eq!(io3.is_set_high(), false);
io4.set_high();
io3.set_high();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_high(), true);
assert_eq!(io4.is_set_high(), true);
assert_eq!(io3.is_set_high(), true);
io4.set_low();
io3.set_low();
ctx.delay.delay_millis(1);
assert_eq!(io2.is_low(), true);
assert_eq!(io4.is_set_low(), true);
assert_eq!(io3.is_set_low(), true);
}
}

4
hil-test/tests/i2s.rs
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@ -1,6 +1,6 @@
//! I2S Loopback Test
//!
//! It's assumed GPIO2 is connected to GPIO4
//! It's assumed GPIO2 is connected to GPIO3
//!
//! This test uses I2S TX to transmit known data to I2S RX (forced to slave mode
//! with loopback mode enabled). It's using circular DMA mode
@ -81,7 +81,7 @@ mod tests {
.i2s_rx
.with_bclk(io.pins.gpio0)
.with_ws(io.pins.gpio1)
.with_din(io.pins.gpio4)
.with_din(io.pins.gpio3)
.build();
// enable loopback testing

8
hil-test/tests/rmt.rs
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@ -1,6 +1,6 @@
//! RMT Loopback Test
//!
//! It's assumed GPIO2 is connected to GPIO4
//! It's assumed GPIO2 is connected to GPIO3
//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -65,17 +65,17 @@ mod tests {
if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
let rx_channel = {
use esp_hal::rmt::RxChannelCreator;
rmt.channel1.configure(io.pins.gpio4, rx_config).unwrap()
rmt.channel1.configure(io.pins.gpio3, rx_config).unwrap()
};
} else if #[cfg(feature = "esp32s3")] {
let rx_channel = {
use esp_hal::rmt::RxChannelCreator;
rmt.channel7.configure(io.pins.gpio4, rx_config).unwrap()
rmt.channel7.configure(io.pins.gpio3, rx_config).unwrap()
};
} else {
let rx_channel = {
use esp_hal::rmt::RxChannelCreator;
rmt.channel2.configure(io.pins.gpio4, rx_config).unwrap()
rmt.channel2.configure(io.pins.gpio3, rx_config).unwrap()
};
}
}

10
hil-test/tests/spi_full_duplex.rs
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@ -3,10 +3,10 @@
//! Folowing pins are used:
//! SCLK GPIO0
//! MISO GPIO2
//! MOSI GPIO4
//! CS GPIO5
//! MOSI GPIO3
//! CS GPIO8
//!
//! Connect MISO (GPIO2) and MOSI (GPIO4) pins.
//! Connect MISO (GPIO2) and MOSI (GPIO3) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -38,8 +38,8 @@ impl Context {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0, &clocks).with_pins(
Some(sclk),

30
hil-test/tests/spi_full_duplex_dma.rs
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@ -3,10 +3,10 @@
//! Folowing pins are used:
//! SCLK GPIO0
//! MISO GPIO2
//! MOSI GPIO4
//! CS GPIO5
//! MOSI GPIO3
//! CS GPIO8
//!
//! Connect MISO (GPIO2) and MOSI (GPIO4) pins.
//! Connect MISO (GPIO2) and MOSI (GPIO3) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s3
@ -48,8 +48,8 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let dma = Dma::new(peripherals.DMA);
@ -91,8 +91,8 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let dma = Dma::new(peripherals.DMA);
@ -135,8 +135,8 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let dma = Dma::new(peripherals.DMA);
@ -183,8 +183,8 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let dma = Dma::new(peripherals.DMA);
@ -232,8 +232,8 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let dma = Dma::new(peripherals.DMA);
@ -280,8 +280,8 @@ mod tests {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let mosi = io.pins.gpio3;
let cs = io.pins.gpio8;
let dma = Dma::new(peripherals.DMA);

8
hil-test/tests/uart.rs
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@ -2,9 +2,9 @@
//!
//! Folowing pins are used:
//! TX GPIP2
//! RX GPIO4
//! RX GPIO3
//!
//! Connect TX (GPIO2) and RX (GPIO4) pins.
//! Connect TX (GPIO2) and RX (GPIO3) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -38,7 +38,7 @@ impl Context {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let uart = Uart::new(peripherals.UART1, &clocks, io.pins.gpio2, io.pins.gpio4).unwrap();
let uart = Uart::new(peripherals.UART1, &clocks, io.pins.gpio2, io.pins.gpio3).unwrap();
Context { clocks, uart }
}
@ -100,7 +100,7 @@ mod tests {
#[cfg(not(feature = "esp32s2"))]
{
#[cfg(not(feature = "esp32c3"))]
#[cfg(not(any(feature = "esp32c3", feature = "esp32c2")))]
{
// 9600 baud, RC FAST clock source:
ctx.uart.change_baud(9600, ClockSource::RcFast, &ctx.clocks);

6
hil-test/tests/uart_async.rs
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@ -2,9 +2,9 @@
//!
//! Folowing pins are used:
//! TX GPIP2
//! RX GPIO4
//! RX GPIO3
//!
//! Connect TX (GPIO2) and RX (GPIO4) pins.
//! Connect TX (GPIO2) and RX (GPIO3) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -34,7 +34,7 @@ impl Context {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let uart =
Uart::new_async(peripherals.UART0, &clocks, io.pins.gpio2, io.pins.gpio4).unwrap();
Uart::new_async(peripherals.UART0, &clocks, io.pins.gpio2, io.pins.gpio3).unwrap();
Context { uart }
}

6
hil-test/tests/uart_tx_rx.rs
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@ -2,9 +2,9 @@
//!
//! Folowing pins are used:
//! TX GPIP2
//! RX GPIO4
//! RX GPIO3
//!
//! Connect TX (GPIO2) and RX (GPIO4) pins.
//! Connect TX (GPIO2) and RX (GPIO3) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -38,7 +38,7 @@ impl Context {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let tx = UartTx::new(peripherals.UART0, &clocks, None, io.pins.gpio2).unwrap();
let rx = UartRx::new(peripherals.UART1, &clocks, None, io.pins.gpio4).unwrap();
let rx = UartRx::new(peripherals.UART1, &clocks, None, io.pins.gpio3).unwrap();
Context { tx, rx }
}

6
hil-test/tests/uart_tx_rx_async.rs
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@ -2,9 +2,9 @@
//!
//! Folowing pins are used:
//! TX GPIP2
//! RX GPIO4
//! RX GPIO3
//!
//! Connect TX (GPIO2) and RX (GPIO4) pins.
//! Connect TX (GPIO2) and RX (GPIO3) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
@ -36,7 +36,7 @@ impl Context {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let tx = UartTx::new_async(peripherals.UART0, &clocks, io.pins.gpio2).unwrap();
let rx = UartRx::new_async(peripherals.UART1, &clocks, io.pins.gpio4).unwrap();
let rx = UartRx::new_async(peripherals.UART1, &clocks, io.pins.gpio3).unwrap();
Context { tx, rx }
}

7
xtask/src/lib.rs
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@ -306,6 +306,13 @@ pub fn execute_app(
if subcommand == "test" {
if chip == Chip::Esp32 {
builder = builder.arg("--").arg("--chip").arg("esp32-3.3v");
} else if chip == Chip::Esp32c2 {
builder = builder
.arg("--")
.arg("--chip")
.arg("esp32c2")
.arg("--speed")
.arg("15000");
} else {
builder = builder.arg("--").arg("--chip").arg(format!("{}", chip));
}