e46e80b8c1
* ci: Enable c2 hil * docs: Update pins and add C2 * feat: Update C2 probe-rs args * test: Update pins and disable failing tests * docs: Update S3 wires * ci: Enable C2 hil tests
71 lines
1.5 KiB
Rust
71 lines
1.5 KiB
Rust
//! UART TX/RX Test
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//!
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//! Folowing pins are used:
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//! TX GPIP2
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//! RX GPIO3
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//!
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//! Connect TX (GPIO2) and RX (GPIO3) pins.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use defmt_rtt as _;
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use esp_backtrace as _;
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use esp_hal::{
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clock::ClockControl,
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gpio::Io,
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peripherals::{Peripherals, UART0, UART1},
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prelude::*,
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system::SystemControl,
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uart::{UartRx, UartTx},
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Blocking,
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};
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use nb::block;
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struct Context {
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tx: UartTx<'static, UART0, Blocking>,
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rx: UartRx<'static, UART1, Blocking>,
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}
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impl Context {
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pub fn init() -> Self {
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let peripherals = Peripherals::take();
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let system = SystemControl::new(peripherals.SYSTEM);
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let tx = UartTx::new(peripherals.UART0, &clocks, None, io.pins.gpio2).unwrap();
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let rx = UartRx::new(peripherals.UART1, &clocks, None, io.pins.gpio3).unwrap();
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Context { tx, rx }
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}
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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Context::init()
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}
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#[test]
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#[timeout(3)]
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fn test_send_receive(mut ctx: Context) {
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let byte = [0x42];
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ctx.tx.flush_tx().unwrap();
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ctx.tx.write_bytes(&byte).unwrap();
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let read = block!(ctx.rx.read_byte());
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assert_eq!(read, Ok(0x42));
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}
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}
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