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Clean up a bit (#2275)

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Dániel Buga 2024-10-04 14:18:11 +02:00 committed by GitHub
parent a4fe5e6e63
commit d3f03042f3
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GPG Key ID: B5690EEEBB952194
7 changed files with 298 additions and 611 deletions
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105
esp-hal/src/dma/gdma.rs
View File

@ -135,30 +135,6 @@ impl<C: GdmaChannel> RegisterAccess for ChannelTxImpl<C> {
.modify(|_, w| w.outlink_restart().set_bit());
}
fn clear_interrupts(&self) {
#[cfg(not(esp32s3))]
self.int().clr().write(|w| {
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf().clear_bit_by_one();
w.outfifo_udf().clear_bit_by_one()
});
#[cfg(esp32s3)]
self.int().clr().write(|w| {
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf_l1().clear_bit_by_one();
w.outfifo_ovf_l3().clear_bit_by_one();
w.outfifo_udf_l1().clear_bit_by_one();
w.outfifo_udf_l3().clear_bit_by_one()
});
}
#[cfg(esp32s3)]
fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) {
self.ch()
@ -178,28 +154,14 @@ impl<C: GdmaChannel> TxRegisterAccess for ChannelTxImpl<C> {
}
impl<C: GdmaChannel> InterruptAccess<DmaTxInterrupt> for ChannelTxImpl<C> {
fn listen(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaTxInterrupt>, enable: bool) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().set_bit(),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().set_bit(),
DmaTxInterrupt::Eof => w.out_eof().set_bit(),
DmaTxInterrupt::Done => w.out_done().set_bit(),
};
}
w
})
}
fn unlisten(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit(),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().clear_bit(),
DmaTxInterrupt::Eof => w.out_eof().clear_bit(),
DmaTxInterrupt::Done => w.out_done().clear_bit(),
DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().bit(enable),
DmaTxInterrupt::Eof => w.out_eof().bit(enable),
DmaTxInterrupt::Done => w.out_done().bit(enable),
};
}
w
@ -352,32 +314,6 @@ impl<C: GdmaChannel> RegisterAccess for ChannelRxImpl<C> {
.modify(|_, w| w.inlink_restart().set_bit());
}
fn clear_interrupts(&self) {
#[cfg(not(esp32s3))]
self.int().clr().write(|w| {
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf().clear_bit_by_one();
w.infifo_udf().clear_bit_by_one()
});
#[cfg(esp32s3)]
self.int().clr().write(|w| {
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf_l1().clear_bit_by_one();
w.infifo_ovf_l3().clear_bit_by_one();
w.infifo_udf_l1().clear_bit_by_one();
w.infifo_udf_l3().clear_bit_by_one()
});
}
#[cfg(esp32s3)]
fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize) {
self.ch()
@ -395,36 +331,21 @@ impl<C: GdmaChannel> RxRegisterAccess for ChannelRxImpl<C> {
}
impl<C: GdmaChannel> InterruptAccess<DmaRxInterrupt> for ChannelRxImpl<C> {
fn listen(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaRxInterrupt>, enable: bool) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().set_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().set_bit(),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().set_bit(),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().set_bit(),
DmaRxInterrupt::Done => w.in_done().set_bit(),
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable),
DmaRxInterrupt::ErrorEof => w.in_err_eof().bit(enable),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().bit(enable),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().bit(enable),
DmaRxInterrupt::Done => w.in_done().bit(enable),
};
}
w
});
}
fn unlisten(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
self.int().ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().clear_bit(),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().clear_bit(),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().clear_bit(),
DmaRxInterrupt::Done => w.in_done().clear_bit(),
};
}
w
})
}
fn is_listening(&self) -> EnumSet<DmaRxInterrupt> {
let mut result = EnumSet::new();

29
esp-hal/src/dma/mod.rs
View File

@ -1684,7 +1684,7 @@ where
compiler_fence(core::sync::atomic::Ordering::SeqCst);
self.rx_impl.clear_interrupts();
self.rx_impl.clear_all();
self.rx_impl.reset();
self.rx_impl.set_link_addr(chain.first() as u32);
self.rx_impl.set_peripheral(peri as u8);
@ -1706,7 +1706,7 @@ where
compiler_fence(core::sync::atomic::Ordering::SeqCst);
self.rx_impl.clear_interrupts();
self.rx_impl.clear_all();
self.rx_impl.reset();
self.rx_impl.set_link_addr(preparation.start as u32);
self.rx_impl.set_peripheral(peri as u8);
@ -1767,7 +1767,7 @@ where
}
fn clear_interrupts(&self) {
self.rx_impl.clear_interrupts();
self.rx_impl.clear_all();
}
fn waker(&self) -> &'static embassy_sync::waitqueue::AtomicWaker {
@ -1891,7 +1891,7 @@ where
compiler_fence(core::sync::atomic::Ordering::SeqCst);
self.tx_impl.clear_interrupts();
self.tx_impl.clear_all();
self.tx_impl.reset();
self.tx_impl.set_link_addr(chain.first() as u32);
self.tx_impl.set_peripheral(peri as u8);
@ -1921,7 +1921,7 @@ where
compiler_fence(core::sync::atomic::Ordering::SeqCst);
self.tx_impl.clear_interrupts();
self.tx_impl.clear_all();
self.tx_impl.reset();
self.tx_impl.set_link_addr(preparation.start as u32);
self.tx_impl.set_peripheral(peri as u8);
@ -1976,7 +1976,7 @@ where
}
fn clear_interrupts(&self) {
self.tx_impl.clear_interrupts();
self.tx_impl.clear_all();
}
fn last_out_dscr_address(&self) -> usize {
@ -2012,9 +2012,6 @@ pub trait RegisterAccess: crate::private::Sealed {
/// Mount a new descriptor.
fn restart(&self);
/// Clear all interrupt bits
fn clear_interrupts(&self);
#[cfg(esp32s3)]
fn set_ext_mem_block_size(&self, size: DmaExtMemBKSize);
}
@ -2033,8 +2030,18 @@ pub trait TxRegisterAccess: RegisterAccess {
#[doc(hidden)]
pub trait InterruptAccess<T: EnumSetType>: crate::private::Sealed {
fn listen(&self, interrupts: impl Into<EnumSet<T>>);
fn unlisten(&self, interrupts: impl Into<EnumSet<T>>);
fn listen(&self, interrupts: impl Into<EnumSet<T>>) {
self.enable_listen(interrupts.into(), true)
}
fn unlisten(&self, interrupts: impl Into<EnumSet<T>>) {
self.enable_listen(interrupts.into(), false)
}
fn clear_all(&self) {
self.clear(EnumSet::all());
}
fn enable_listen(&self, interrupts: EnumSet<T>, enable: bool);
fn is_listening(&self) -> EnumSet<T>;
fn clear(&self, interrupts: impl Into<EnumSet<T>>);
fn pending_interrupts(&self) -> EnumSet<T>;

162
esp-hal/src/dma/pdma.rs
View File

@ -80,16 +80,6 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> RegisterAccess for SpiDma
spi.dma_out_link()
.modify(|_, w| w.outlink_restart().set_bit());
}
fn clear_interrupts(&self) {
let spi = C::register_block();
spi.dma_int_clr().write(|w| {
w.out_done().clear_bit_by_one();
w.out_eof().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outlink_dscr_error().clear_bit_by_one()
});
}
}
impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> TxRegisterAccess for SpiDmaTxChannelImpl<C> {
@ -102,30 +92,15 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> TxRegisterAccess for SpiD
impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaTxInterrupt>
for SpiDmaTxChannelImpl<C>
{
fn listen(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaTxInterrupt>, enable: bool) {
let spi = C::register_block();
spi.dma_int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().set_bit(),
DmaTxInterrupt::DescriptorError => w.outlink_dscr_error().set_bit(),
DmaTxInterrupt::Eof => w.out_eof().set_bit(),
DmaTxInterrupt::Done => w.out_done().set_bit(),
};
}
w
})
}
fn unlisten(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
let spi = C::register_block();
spi.dma_int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit(),
DmaTxInterrupt::DescriptorError => w.outlink_dscr_error().clear_bit(),
DmaTxInterrupt::Eof => w.out_eof().clear_bit(),
DmaTxInterrupt::Done => w.out_done().clear_bit(),
DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable),
DmaTxInterrupt::DescriptorError => w.outlink_dscr_error().bit(enable),
DmaTxInterrupt::Eof => w.out_eof().bit(enable),
DmaTxInterrupt::Done => w.out_done().bit(enable),
};
}
w
@ -234,16 +209,6 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> RegisterAccess for SpiDma
spi.dma_in_link()
.modify(|_, w| w.inlink_restart().set_bit());
}
fn clear_interrupts(&self) {
let spi = C::register_block();
spi.dma_int_clr().write(|w| {
w.in_done().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_suc_eof().clear_bit_by_one();
w.inlink_dscr_error().clear_bit_by_one()
});
}
}
impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> RxRegisterAccess for SpiDmaRxChannelImpl<C> {}
@ -251,32 +216,16 @@ impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> RxRegisterAccess for SpiD
impl<C: PdmaChannel<RegisterBlock = SpiRegisterBlock>> InterruptAccess<DmaRxInterrupt>
for SpiDmaRxChannelImpl<C>
{
fn listen(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaRxInterrupt>, enable: bool) {
let spi = C::register_block();
spi.dma_int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().set_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().set_bit(),
DmaRxInterrupt::DescriptorError => w.inlink_dscr_error().set_bit(),
DmaRxInterrupt::DescriptorEmpty => w.inlink_dscr_empty().set_bit(),
DmaRxInterrupt::Done => w.in_done().set_bit(),
};
}
w
})
}
fn unlisten(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
let spi = C::register_block();
spi.dma_int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().clear_bit(),
DmaRxInterrupt::DescriptorError => w.inlink_dscr_error().clear_bit(),
DmaRxInterrupt::DescriptorEmpty => w.inlink_dscr_empty().clear_bit(),
DmaRxInterrupt::Done => w.in_done().clear_bit(),
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable),
DmaRxInterrupt::ErrorEof => w.in_err_eof().bit(enable),
DmaRxInterrupt::DescriptorError => w.inlink_dscr_error().bit(enable),
DmaRxInterrupt::DescriptorEmpty => w.inlink_dscr_empty().bit(enable),
DmaRxInterrupt::Done => w.in_done().bit(enable),
};
}
w
@ -498,20 +447,6 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> RegisterAccess for I2sDma
fn set_priority(&self, _priority: DmaPriority) {}
fn clear_interrupts(&self) {
let reg_block = C::register_block();
reg_block.int_clr().write(|w| {
w.out_done()
.clear_bit_by_one()
.out_eof()
.clear_bit_by_one()
.out_total_eof()
.clear_bit_by_one()
.out_dscr_err()
.clear_bit_by_one()
});
}
fn reset(&self) {
let reg_block = C::register_block();
reg_block.lc_conf().modify(|_, w| w.out_rst().set_bit());
@ -565,30 +500,15 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> TxRegisterAccess for I2sD
impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaTxInterrupt>
for I2sDmaTxChannelImpl<C>
{
fn listen(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaTxInterrupt>, enable: bool) {
let reg_block = C::register_block();
reg_block.int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().set_bit(),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().set_bit(),
DmaTxInterrupt::Eof => w.out_eof().set_bit(),
DmaTxInterrupt::Done => w.out_done().set_bit(),
};
}
w
})
}
fn unlisten(&self, interrupts: impl Into<EnumSet<DmaTxInterrupt>>) {
let reg_block = C::register_block();
reg_block.int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaTxInterrupt::TotalEof => w.out_total_eof().clear_bit(),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().clear_bit(),
DmaTxInterrupt::Eof => w.out_eof().clear_bit(),
DmaTxInterrupt::Done => w.out_done().clear_bit(),
DmaTxInterrupt::TotalEof => w.out_total_eof().bit(enable),
DmaTxInterrupt::DescriptorError => w.out_dscr_err().bit(enable),
DmaTxInterrupt::Eof => w.out_eof().bit(enable),
DmaTxInterrupt::Done => w.out_done().bit(enable),
};
}
w
@ -667,20 +587,6 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> RegisterAccess for I2sDma
fn set_priority(&self, _priority: DmaPriority) {}
fn clear_interrupts(&self) {
let reg_block = C::register_block();
reg_block.int_clr().write(|w| {
w.in_done()
.clear_bit_by_one()
.in_err_eof()
.clear_bit_by_one()
.in_suc_eof()
.clear_bit_by_one()
.in_dscr_err()
.clear_bit_by_one()
});
}
fn reset(&self) {
let reg_block = C::register_block();
reg_block.lc_conf().modify(|_, w| w.in_rst().set_bit());
@ -723,32 +629,16 @@ impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> RxRegisterAccess for I2sD
impl<C: PdmaChannel<RegisterBlock = I2sRegisterBlock>> InterruptAccess<DmaRxInterrupt>
for I2sDmaRxChannelImpl<C>
{
fn listen(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
fn enable_listen(&self, interrupts: EnumSet<DmaRxInterrupt>, enable: bool) {
let reg_block = C::register_block();
reg_block.int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
for interrupt in interrupts {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().set_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().set_bit(),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().set_bit(),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().set_bit(),
DmaRxInterrupt::Done => w.in_done().set_bit(),
};
}
w
})
}
fn unlisten(&self, interrupts: impl Into<EnumSet<DmaRxInterrupt>>) {
let reg_block = C::register_block();
reg_block.int_ena().modify(|_, w| {
for interrupt in interrupts.into() {
match interrupt {
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().clear_bit(),
DmaRxInterrupt::ErrorEof => w.in_err_eof().clear_bit(),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().clear_bit(),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().clear_bit(),
DmaRxInterrupt::Done => w.in_done().clear_bit(),
DmaRxInterrupt::SuccessfulEof => w.in_suc_eof().bit(enable),
DmaRxInterrupt::ErrorEof => w.in_err_eof().bit(enable),
DmaRxInterrupt::DescriptorError => w.in_dscr_err().bit(enable),
DmaRxInterrupt::DescriptorEmpty => w.in_dscr_empty().bit(enable),
DmaRxInterrupt::Done => w.in_done().bit(enable),
};
}
w

111
esp-hal/src/i2s.rs
View File

@ -1025,34 +1025,26 @@ mod private {
pub trait RegisterAccessPrivate: Signals + RegBlock {
fn set_interrupt_handler(handler: InterruptHandler);
fn listen(interrupts: EnumSet<I2sInterrupt>) {
fn enable_listen(interrupts: EnumSet<I2sInterrupt>, enable: bool) {
let reg_block = Self::register_block();
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().set_bit())
}
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
}
reg_block.int_ena().modify(|_, w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().bit(enable),
I2sInterrupt::TxHung => w.tx_hung().bit(enable),
};
}
}
w
});
}
fn unlisten(interrupts: EnumSet<I2sInterrupt>) {
let reg_block = Self::register_block();
fn listen(interrupts: impl Into<EnumSet<I2sInterrupt>>) {
Self::enable_listen(interrupts.into(), true);
}
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().clear_bit())
}
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
}
}
}
fn unlisten(interrupts: impl Into<EnumSet<I2sInterrupt>>) {
Self::enable_listen(interrupts.into(), false);
}
fn interrupts() -> EnumSet<I2sInterrupt> {
@ -1287,46 +1279,28 @@ mod private {
pub trait RegisterAccessPrivate: Signals + RegBlock {
fn set_interrupt_handler(handler: InterruptHandler);
fn listen(interrupts: EnumSet<I2sInterrupt>) {
fn enable_listen(interrupts: EnumSet<I2sInterrupt>, enable: bool) {
let reg_block = Self::register_block();
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().set_bit())
}
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
}
I2sInterrupt::RxDone => {
reg_block.int_ena().modify(|_, w| w.rx_done().set_bit())
}
I2sInterrupt::TxDone => {
reg_block.int_ena().modify(|_, w| w.tx_done().set_bit())
}
reg_block.int_ena().modify(|_, w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().bit(enable),
I2sInterrupt::TxHung => w.tx_hung().bit(enable),
I2sInterrupt::RxDone => w.rx_done().bit(enable),
I2sInterrupt::TxDone => w.tx_done().bit(enable),
};
}
}
w
});
}
fn unlisten(interrupts: EnumSet<I2sInterrupt>) {
let reg_block = Self::register_block();
fn listen(interrupts: impl Into<EnumSet<I2sInterrupt>>) {
Self::enable_listen(interrupts.into(), true);
}
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => {
reg_block.int_ena().modify(|_, w| w.rx_hung().clear_bit())
}
I2sInterrupt::TxHung => {
reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
}
I2sInterrupt::RxDone => {
reg_block.int_ena().modify(|_, w| w.rx_done().clear_bit())
}
I2sInterrupt::TxDone => {
reg_block.int_ena().modify(|_, w| w.tx_done().clear_bit())
}
}
}
fn unlisten(interrupts: impl Into<EnumSet<I2sInterrupt>>) {
Self::enable_listen(interrupts.into(), false);
}
fn interrupts() -> EnumSet<I2sInterrupt> {
@ -1353,22 +1327,17 @@ mod private {
fn clear_interrupts(interrupts: EnumSet<I2sInterrupt>) {
let reg_block = Self::register_block();
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => reg_block
.int_clr()
.write(|w| w.rx_hung().clear_bit_by_one()),
I2sInterrupt::TxHung => reg_block
.int_clr()
.write(|w| w.tx_hung().clear_bit_by_one()),
I2sInterrupt::RxDone => reg_block
.int_clr()
.write(|w| w.rx_done().clear_bit_by_one()),
I2sInterrupt::TxDone => reg_block
.int_clr()
.write(|w| w.tx_done().clear_bit_by_one()),
reg_block.int_clr().write(|w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().clear_bit_by_one(),
I2sInterrupt::TxHung => w.tx_hung().clear_bit_by_one(),
I2sInterrupt::RxDone => w.rx_done().clear_bit_by_one(),
I2sInterrupt::TxDone => w.tx_done().clear_bit_by_one(),
};
}
}
w
});
}
#[cfg(any(esp32c3, esp32s3))]

39
esp-hal/src/parl_io.rs
View File

@ -1033,32 +1033,17 @@ fn internal_set_interrupt_handler(handler: InterruptHandler) {
}
}
fn internal_listen(interrupts: EnumSet<ParlIoInterrupt>) {
fn internal_listen(interrupts: EnumSet<ParlIoInterrupt>, enable: bool) {
let parl_io = unsafe { crate::peripherals::PARL_IO::steal() };
for interrupt in interrupts {
match interrupt {
ParlIoInterrupt::TxFifoReEmpty => parl_io
.int_ena()
.modify(|_, w| w.tx_fifo_rempty().set_bit()),
ParlIoInterrupt::RxFifoWOvf => {
parl_io.int_ena().modify(|_, w| w.rx_fifo_wovf().set_bit())
}
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof().set_bit()),
}
}
}
fn internal_unlisten(interrupts: EnumSet<ParlIoInterrupt>) {
let parl_io = unsafe { crate::peripherals::PARL_IO::steal() };
for interrupt in interrupts {
match interrupt {
ParlIoInterrupt::TxFifoReEmpty => parl_io
.int_ena()
.modify(|_, w| w.tx_fifo_rempty().clear_bit()),
.modify(|_, w| w.tx_fifo_rempty().bit(enable)),
ParlIoInterrupt::RxFifoWOvf => parl_io
.int_ena()
.modify(|_, w| w.rx_fifo_wovf().clear_bit()),
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof().clear_bit()),
.modify(|_, w| w.rx_fifo_wovf().bit(enable)),
ParlIoInterrupt::TxEof => parl_io.int_ena().write(|w| w.tx_eof().bit(enable)),
}
}
}
@ -1157,13 +1142,13 @@ where
}
/// Listen for the given interrupts
pub fn listen(&mut self, interrupts: EnumSet<ParlIoInterrupt>) {
internal_listen(interrupts);
pub fn listen(&mut self, interrupts: impl Into<EnumSet<ParlIoInterrupt>>) {
internal_listen(interrupts.into(), true);
}
/// Unlisten the given interrupts
pub fn unlisten(&mut self, interrupts: EnumSet<ParlIoInterrupt>) {
internal_unlisten(interrupts);
pub fn unlisten(&mut self, interrupts: impl Into<EnumSet<ParlIoInterrupt>>) {
internal_listen(interrupts.into(), false);
}
/// Gets asserted interrupts
@ -1246,12 +1231,12 @@ where
/// Listen for the given interrupts
pub fn listen(&mut self, interrupts: EnumSet<ParlIoInterrupt>) {
internal_listen(interrupts);
internal_listen(interrupts, true);
}
/// Unlisten the given interrupts
pub fn unlisten(&mut self, interrupts: EnumSet<ParlIoInterrupt>) {
internal_unlisten(interrupts);
internal_listen(interrupts, false);
}
/// Gets asserted interrupts
@ -1334,12 +1319,12 @@ where
/// Listen for the given interrupts
pub fn listen(&mut self, interrupts: EnumSet<ParlIoInterrupt>) {
internal_listen(interrupts);
internal_listen(interrupts, true);
}
/// Unlisten the given interrupts
pub fn unlisten(&mut self, interrupts: EnumSet<ParlIoInterrupt>) {
internal_unlisten(interrupts);
internal_listen(interrupts, false);
}
/// Gets asserted interrupts

409
esp-hal/src/rmt.rs
View File

@ -459,38 +459,34 @@ where
return Err((Error::TransmissionError, self.channel));
}
if self.index < self.data.len() {
// wait for TX-THR
loop {
if <C as private::TxChannelInternal<crate::Blocking>>::is_threshold_set() {
break;
}
}
<C as private::TxChannelInternal<crate::Blocking>>::reset_threshold_set();
// re-fill TX RAM
let ram_index = (((self.index - constants::RMT_CHANNEL_RAM_SIZE)
/ (constants::RMT_CHANNEL_RAM_SIZE / 2))
% 2)
* (constants::RMT_CHANNEL_RAM_SIZE / 2);
let ptr = (constants::RMT_RAM_START
+ C::CHANNEL as usize * constants::RMT_CHANNEL_RAM_SIZE * 4
+ ram_index * 4) as *mut u32;
for (idx, entry) in self.data[self.index..]
.iter()
.take(constants::RMT_CHANNEL_RAM_SIZE / 2)
.enumerate()
{
unsafe {
ptr.add(idx).write_volatile((*entry).into());
}
}
self.index += constants::RMT_CHANNEL_RAM_SIZE / 2;
} else {
if self.index >= self.data.len() {
break;
}
// wait for TX-THR
while !<C as private::TxChannelInternal<crate::Blocking>>::is_threshold_set() {}
<C as private::TxChannelInternal<crate::Blocking>>::reset_threshold_set();
// re-fill TX RAM
let ram_index = (((self.index - constants::RMT_CHANNEL_RAM_SIZE)
/ (constants::RMT_CHANNEL_RAM_SIZE / 2))
% 2)
* (constants::RMT_CHANNEL_RAM_SIZE / 2);
let ptr = (constants::RMT_RAM_START
+ C::CHANNEL as usize * constants::RMT_CHANNEL_RAM_SIZE * 4
+ ram_index * 4) as *mut u32;
for (idx, entry) in self.data[self.index..]
.iter()
.take(constants::RMT_CHANNEL_RAM_SIZE / 2)
.enumerate()
{
unsafe {
ptr.add(idx).write_volatile((*entry).into());
}
}
self.index += constants::RMT_CHANNEL_RAM_SIZE / 2;
}
loop {
@ -1536,9 +1532,15 @@ mod private {
fn stop();
fn listen_interrupt(event: Event);
fn enable_listen_interrupt(event: Event, enable: bool);
fn unlisten_interrupt(event: Event);
fn listen_interrupt(event: Event) {
Self::enable_listen_interrupt(event, true);
}
fn unlisten_interrupt(event: Event) {
Self::enable_listen_interrupt(event, false);
}
}
pub trait RxChannelInternal<M>
@ -1583,9 +1585,15 @@ mod private {
fn set_idle_threshold(value: u16);
fn listen_interrupt(event: Event);
fn enable_listen_interrupt(event: Event, enable: bool);
fn unlisten_interrupt(event: Event);
fn listen_interrupt(event: Event) {
Self::enable_listen_interrupt(event, true);
}
fn unlisten_interrupt(event: Event) {
Self::enable_listen_interrupt(event, false);
}
}
}
@ -1596,18 +1604,12 @@ mod chip_specific {
{
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.sys_conf().modify(|_, w| unsafe {
w.clk_en()
.clear_bit()
.sclk_sel()
.bits(crate::soc::constants::RMT_CLOCK_SRC)
.sclk_div_num()
.bits(div as u8)
.sclk_div_a()
.bits(0)
.sclk_div_b()
.bits(0)
.apb_fifo_mask()
.set_bit()
w.clk_en().clear_bit();
w.sclk_sel().bits(crate::soc::constants::RMT_CLOCK_SRC);
w.sclk_div_num().bits(div as u8);
w.sclk_div_a().bits(0);
w.sclk_div_b().bits(0);
w.apb_fifo_mask().set_bit()
});
}
@ -1615,12 +1617,9 @@ mod chip_specific {
{
let pcr = unsafe { &*crate::peripherals::PCR::PTR };
pcr.rmt_sclk_conf().modify(|_, w| unsafe {
w.sclk_div_num()
.bits(div as u8)
.sclk_div_a()
.bits(0)
.sclk_div_b()
.bits(0)
w.sclk_div_num().bits(div as u8);
w.sclk_div_a().bits(0);
w.sclk_div_b().bits(0)
});
#[cfg(esp32c6)]
@ -1711,21 +1710,15 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
if repeats > 1 {
rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe {
w.loop_count_reset()
.set_bit()
.tx_loop_cnt_en()
.set_bit()
.tx_loop_num()
.bits(repeats)
w.loop_count_reset().set_bit();
w.tx_loop_cnt_en().set_bit();
w.tx_loop_num().bits(repeats)
});
} else {
rmt.ch_tx_lim($ch_num).modify(|_, w| unsafe {
w.loop_count_reset()
.set_bit()
.tx_loop_cnt_en()
.clear_bit()
.tx_loop_num()
.bits(0)
w.loop_count_reset().set_bit();
w.tx_loop_cnt_en().clear_bit();
w.tx_loop_num().bits(0)
});
}
@ -1736,14 +1729,10 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.int_clr().write(|w| {
w.[< ch $ch_num _tx_end >]()
.set_bit()
.[< ch $ch_num _tx_err >]()
.set_bit()
.[< ch $ch_num _tx_loop >]()
.set_bit()
.[< ch $ch_num _tx_thr_event >]()
.set_bit()
w.[< ch $ch_num _tx_end >]().set_bit();
w.[< ch $ch_num _tx_err >]().set_bit();
w.[< ch $ch_num _tx_loop >]().set_bit();
w.[< ch $ch_num _tx_thr_event >]().set_bit()
});
}
@ -1766,12 +1755,9 @@ mod chip_specific {
.write(|w| unsafe { w.carrier_high().bits(high).carrier_low().bits(low) });
rmt.ch_tx_conf0($ch_num).modify(|_, w| {
w.carrier_en()
.bit(carrier)
.carrier_eff_en()
.set_bit()
.carrier_out_lv()
.bit(level)
w.carrier_en().bit(carrier);
w.carrier_eff_en().set_bit();
w.carrier_out_lv().bit(level)
});
}
@ -1793,12 +1779,9 @@ mod chip_specific {
Self::update();
rmt.ch_tx_conf0($ch_num).modify(|_, w| {
w.mem_rd_rst()
.set_bit()
.apb_mem_rst()
.set_bit()
.tx_start()
.set_bit()
w.mem_rd_rst().set_bit();
w.apb_mem_rst().set_bit();
w.tx_start().set_bit()
});
Self::update();
}
@ -1840,34 +1823,22 @@ mod chip_specific {
Self::update();
}
fn listen_interrupt(event: $crate::rmt::private::Event) {
fn enable_listen_interrupt(event: $crate::rmt::private::Event, enable: bool) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_err >]().set_bit());
rmt.int_ena().modify(|_, w| {
match event {
$crate::rmt::private::Event::Error => {
w.[< ch $ch_num _tx_err >]().bit(enable);
}
$crate::rmt::private::Event::End => {
w.[< ch $ch_num _tx_end >]().bit(enable);
}
$crate::rmt::private::Event::Threshold => {
w.[< ch $ch_num _tx_thr_event >]().bit(enable);
}
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_end >]().set_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_thr_event >]().set_bit());
}
}
}
fn unlisten_interrupt(event: $crate::rmt::private::Event) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_err >]().clear_bit());
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_end >]().clear_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_thr_event >]().clear_bit());
}
}
w
});
}
}
}
@ -1904,12 +1875,9 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.int_clr().write(|w| {
w.[< ch $ch_num _rx_end >]()
.set_bit()
.[< ch $ch_num _rx_err >]()
.set_bit()
.[< ch $ch_num _rx_thr_event >]()
.set_bit()
w.[< ch $ch_num _rx_end >]().set_bit();
w.[< ch $ch_num _rx_err >]().set_bit();
w.[< ch $ch_num _rx_thr_event >]().set_bit()
});
}
@ -1922,10 +1890,8 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.ch_rx_carrier_rm($ch_index).write(|w| unsafe {
w.carrier_high_thres()
.bits(high)
.carrier_low_thres()
.bits(low)
w.carrier_high_thres().bits(high);
w.carrier_low_thres().bits(low)
});
rmt.[< ch $ch_num _rx_conf0 >]()
@ -1940,14 +1906,10 @@ mod chip_specific {
fn start_rx() {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| {
w.mem_wr_rst()
.set_bit()
.apb_mem_rst()
.set_bit()
.mem_owner()
.set_bit()
.rx_en()
.set_bit()
w.mem_wr_rst().set_bit();
w.apb_mem_rst().set_bit();
w.mem_owner().set_bit();
w.rx_en().set_bit()
});
}
@ -1970,10 +1932,8 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| unsafe {
w.rx_filter_en()
.bit(value > 0)
.rx_filter_thres()
.bits(value)
w.rx_filter_en().bit(value > 0);
w.rx_filter_thres().bits(value)
});
}
@ -1983,34 +1943,22 @@ mod chip_specific {
rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.idle_thres().bits(value) });
}
fn listen_interrupt(event: $crate::rmt::private::Event) {
fn enable_listen_interrupt(event: $crate::rmt::private::Event, enable: bool) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_err >]().set_bit());
rmt.int_ena().modify(|_, w| {
match event {
$crate::rmt::private::Event::Error => {
w.[< ch $ch_num _rx_err >]().bit(enable);
}
$crate::rmt::private::Event::End => {
w.[< ch $ch_num _rx_end >]().bit(enable);
}
$crate::rmt::private::Event::Threshold => {
w.[< ch $ch_num _rx_thr_event >]().bit(enable);
}
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_end >]().set_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_thr_event >]().set_bit());
}
}
}
fn unlisten_interrupt(event: $crate::rmt::private::Event) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_err >]().clear_bit());
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_end >]().clear_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_thr_event >]().clear_bit());
}
}
w
});
}
}
}
@ -2134,12 +2082,9 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.int_clr().write(|w| {
w.[< ch $ch_num _tx_end >]()
.set_bit()
.[< ch $ch_num _err >]()
.set_bit()
.[< ch $ch_num _tx_thr_event >]()
.set_bit()
w.[< ch $ch_num _err >]().set_bit();
w.[< ch $ch_num _tx_end >]().set_bit();
w.[< ch $ch_num _tx_thr_event >]().set_bit()
});
}
@ -2181,12 +2126,9 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.[< ch $ch_num conf1 >]().modify(|_, w| {
w.mem_rd_rst()
.set_bit()
.apb_mem_rst()
.set_bit()
.tx_start()
.set_bit()
w.mem_rd_rst().set_bit();
w.apb_mem_rst().set_bit();
w.tx_start().set_bit()
});
}
@ -2229,34 +2171,30 @@ mod chip_specific {
}
}
fn listen_interrupt(event: $crate::rmt::private::Event) {
fn enable_listen_interrupt(event: $crate::rmt::private::Event, enable: bool) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _err >]().set_bit());
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_end >]().set_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_thr_event >]().set_bit());
}
}
rmt.int_ena().modify(|_,w| {
match event {
$crate::rmt::private::Event::Error => {
w.[< ch $ch_num _err >]().bit(enable)
}
$crate::rmt::private::Event::End => {
w.[< ch $ch_num _tx_end >]().bit(enable)
}
$crate::rmt::private::Event::Threshold => {
w.[< ch $ch_num _tx_thr_event >]().bit(enable)
}
};
w
});
}
fn listen_interrupt(event: $crate::rmt::private::Event) {
Self::enable_listen_interrupt(event, true)
}
fn unlisten_interrupt(event: $crate::rmt::private::Event) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _err >]().clear_bit());
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_end >]().clear_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_thr_event >]().clear_bit());
}
}
Self::enable_listen_interrupt(event, false)
}
}
}
@ -2292,24 +2230,17 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.[< ch $ch_num conf1 >]().modify(|_, w| {
w.mem_wr_rst()
.set_bit()
.apb_mem_rst()
.set_bit()
.mem_owner()
.set_bit()
.rx_en()
.clear_bit()
w.mem_wr_rst().set_bit();
w.apb_mem_rst().set_bit();
w.mem_owner().set_bit();
w.rx_en().clear_bit()
});
Self::update();
rmt.int_clr().write(|w| {
w.[< ch $ch_num _rx_end >]()
.set_bit()
.[< ch $ch_num _err >]()
.set_bit()
.[< ch $ch_num _tx_thr_event >]()
.set_bit()
w.[< ch $ch_num _rx_end >]().set_bit();
w.[< ch $ch_num _err >]().set_bit();
w.[< ch $ch_num _tx_thr_event >]().set_bit()
});
}
@ -2337,14 +2268,10 @@ mod chip_specific {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.[< ch $ch_num conf1 >]().modify(|_, w| {
w.mem_wr_rst()
.set_bit()
.apb_mem_rst()
.set_bit()
.mem_owner()
.set_bit()
.rx_en()
.set_bit()
w.mem_wr_rst().set_bit();
w.apb_mem_rst().set_bit();
w.mem_owner().set_bit();
w.rx_en().set_bit()
});
}
@ -2366,10 +2293,8 @@ mod chip_specific {
fn set_filter_threshold(value: u8) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
rmt.[< ch $ch_num conf1 >]().modify(|_, w| unsafe {
w.rx_filter_en()
.bit(value > 0)
.rx_filter_thres()
.bits(value)
w.rx_filter_en().bit(value > 0);
w.rx_filter_thres().bits(value)
});
}
@ -2379,34 +2304,30 @@ mod chip_specific {
rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.idle_thres().bits(value) });
}
fn listen_interrupt(event: $crate::rmt::private::Event) {
fn enable_listen_interrupt(event: $crate::rmt::private::Event, enable: bool) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _err >]().set_bit());
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_end >]().set_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_thr_event >]().set_bit());
}
}
rmt.int_ena().modify(|_, w| {
match event {
$crate::rmt::private::Event::Error => {
w.[< ch $ch_num _err >]().bit(enable)
}
$crate::rmt::private::Event::End => {
w.[< ch $ch_num _rx_end >]().bit(enable)
}
$crate::rmt::private::Event::Threshold => {
w.[< ch $ch_num _tx_thr_event >]().bit(enable)
}
};
w
});
}
fn listen_interrupt(event: $crate::rmt::private::Event) {
Self::enable_listen_interrupt(event, true)
}
fn unlisten_interrupt(event: $crate::rmt::private::Event) {
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
match event {
$crate::rmt::private::Event::Error => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _err >]().clear_bit());
}
$crate::rmt::private::Event::End => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _rx_end >]().clear_bit());
}
$crate::rmt::private::Event::Threshold => {
rmt.int_ena().modify(|_,w| w.[< ch $ch_num _tx_thr_event >]().clear_bit());
}
}
Self::enable_listen_interrupt(event, false)
}
}
}

54
esp-hal/src/spi/master.rs
View File

@ -2703,36 +2703,31 @@ pub trait Instance: private::Sealed {
/// Set the interrupt handler
fn set_interrupt_handler(&mut self, handler: InterruptHandler);
/// Listen for the given interrupts
/// Enable or disable listening for the given interrupts.
#[cfg(gdma)]
fn listen(&mut self, interrupts: EnumSet<SpiInterrupt>) {
fn enable_listen(&mut self, interrupts: EnumSet<SpiInterrupt>, enable: bool) {
let reg_block = self.register_block();
for interrupt in interrupts {
match interrupt {
SpiInterrupt::TransDone => {
reg_block
.dma_int_ena()
.modify(|_, w| w.trans_done().set_bit());
}
reg_block.dma_int_ena().modify(|_, w| {
for interrupt in interrupts {
match interrupt {
SpiInterrupt::TransDone => w.trans_done().bit(enable),
};
}
}
w
});
}
/// Listen for the given interrupts
#[cfg(gdma)]
fn listen(&mut self, interrupts: impl Into<EnumSet<SpiInterrupt>>) {
self.enable_listen(interrupts.into(), true);
}
/// Unlisten the given interrupts
#[cfg(gdma)]
fn unlisten(&mut self, interrupts: EnumSet<SpiInterrupt>) {
let reg_block = self.register_block();
for interrupt in interrupts {
match interrupt {
SpiInterrupt::TransDone => {
reg_block
.dma_int_ena()
.modify(|_, w| w.trans_done().clear_bit());
}
}
}
fn unlisten(&mut self, interrupts: impl Into<EnumSet<SpiInterrupt>>) {
self.enable_listen(interrupts.into(), false);
}
/// Gets asserted interrupts
@ -2755,15 +2750,14 @@ pub trait Instance: private::Sealed {
fn clear_interrupts(&mut self, interrupts: EnumSet<SpiInterrupt>) {
let reg_block = self.register_block();
for interrupt in interrupts {
match interrupt {
SpiInterrupt::TransDone => {
reg_block
.dma_int_clr()
.write(|w| w.trans_done().clear_bit_by_one());
}
reg_block.dma_int_clr().write(|w| {
for interrupt in interrupts {
match interrupt {
SpiInterrupt::TransDone => w.trans_done().clear_bit_by_one(),
};
}
}
w
});
}
fn set_data_mode(&mut self, data_mode: SpiMode) -> &mut Self {