Clean up (#2266)
This commit is contained in:
Dániel Buga
GitHub
parent
30aef580e3
commit
e033162ffd
@ -243,7 +243,7 @@ pub mod dma {
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impl<'d, T, C, DmaMode> DmaSupport for SpiDma<'d, T, C, DmaMode>
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where
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T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
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T: InstanceDma,
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C: DmaChannel,
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C::P: SpiPeripheral,
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DmaMode: Mode,
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@ -264,7 +264,7 @@ pub mod dma {
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impl<'d, T, C, DmaMode> DmaSupportTx for SpiDma<'d, T, C, DmaMode>
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where
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T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
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T: InstanceDma,
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C: DmaChannel,
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C::P: SpiPeripheral,
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DmaMode: Mode,
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@ -282,7 +282,7 @@ pub mod dma {
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impl<'d, T, C, DmaMode> DmaSupportRx for SpiDma<'d, T, C, DmaMode>
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where
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T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
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T: InstanceDma,
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C: DmaChannel,
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C::P: SpiPeripheral,
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DmaMode: Mode,
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@ -300,7 +300,7 @@ pub mod dma {
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impl<'d, T, C, DmaMode> SpiDma<'d, T, C, DmaMode>
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where
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T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
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T: InstanceDma,
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C: DmaChannel,
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C::P: SpiPeripheral,
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DmaMode: Mode,
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@ -399,13 +399,11 @@ pub mod dma {
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}
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#[doc(hidden)]
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pub trait InstanceDma<RX, TX>: Instance
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where
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RX: Rx,
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TX: Tx,
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{
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pub trait InstanceDma: Instance {
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fn dma_peripheral(&self) -> DmaPeripheral;
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#[allow(clippy::too_many_arguments)]
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unsafe fn start_transfer_dma(
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unsafe fn start_transfer_dma<RX, TX>(
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&mut self,
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rx_chain: &mut DescriptorChain,
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tx_chain: &mut DescriptorChain,
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@ -415,7 +413,11 @@ where
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write_buffer_len: usize,
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rx: &mut RX,
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tx: &mut TX,
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) -> Result<(), Error> {
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) -> Result<(), Error>
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where
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RX: Rx,
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TX: Tx,
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{
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let reg_block = self.register_block();
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rx.is_done();
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@ -447,13 +449,16 @@ where
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Ok(())
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}
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unsafe fn start_write_bytes_dma(
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unsafe fn start_write_bytes_dma<TX>(
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&mut self,
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tx_chain: &mut DescriptorChain,
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ptr: *const u8,
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len: usize,
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tx: &mut TX,
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) -> Result<(), Error> {
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) -> Result<(), Error>
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where
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TX: Tx,
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{
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let reg_block = self.register_block();
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tx.is_done();
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@ -480,13 +485,16 @@ where
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Ok(())
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}
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unsafe fn start_read_bytes_dma(
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unsafe fn start_read_bytes_dma<RX>(
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&mut self,
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rx_chain: &mut DescriptorChain,
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ptr: *mut u8,
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len: usize,
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rx: &mut RX,
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) -> Result<(), Error> {
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) -> Result<(), Error>
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where
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RX: Rx,
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{
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let reg_block = self.register_block();
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rx.is_done();
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@ -512,25 +520,13 @@ where
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Ok(())
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}
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fn dma_peripheral(&self) -> DmaPeripheral {
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match self.spi_num() {
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2 => DmaPeripheral::Spi2,
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#[cfg(spi3)]
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3 => DmaPeripheral::Spi3,
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_ => panic!("Illegal SPI instance"),
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}
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}
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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fn enable_dma(&self) {
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let reg_block = self.register_block();
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reg_block.dma_conf().modify(|_, w| {
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w.dma_tx_ena()
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.set_bit()
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.dma_rx_ena()
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.set_bit()
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.rx_eof_en()
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.clear_bit()
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w.dma_tx_ena().set_bit();
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w.dma_rx_ena().set_bit();
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w.rx_eof_en().clear_bit()
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});
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}
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@ -543,16 +539,11 @@ where
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fn clear_dma_interrupts(&self) {
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let reg_block = self.register_block();
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reg_block.dma_int_clr().write(|w| {
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w.dma_infifo_full_err()
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.clear_bit_by_one()
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.dma_outfifo_empty_err()
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.clear_bit_by_one()
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.trans_done()
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.clear_bit_by_one()
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.mst_rx_afifo_wfull_err()
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.clear_bit_by_one()
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.mst_tx_afifo_rempty_err()
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.clear_bit_by_one()
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w.dma_infifo_full_err().clear_bit_by_one();
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w.dma_outfifo_empty_err().clear_bit_by_one();
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w.trans_done().clear_bit_by_one();
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w.mst_rx_afifo_wfull_err().clear_bit_by_one();
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w.mst_tx_afifo_rempty_err().clear_bit_by_one()
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});
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}
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@ -560,24 +551,15 @@ where
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fn clear_dma_interrupts(&self) {
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let reg_block = self.register_block();
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reg_block.dma_int_clr().write(|w| {
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w.inlink_dscr_empty()
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.clear_bit_by_one()
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.outlink_dscr_error()
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.clear_bit_by_one()
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.inlink_dscr_error()
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.clear_bit_by_one()
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.in_done()
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.clear_bit_by_one()
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.in_err_eof()
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.clear_bit_by_one()
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.in_suc_eof()
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.clear_bit_by_one()
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.out_done()
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.clear_bit_by_one()
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.out_eof()
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.clear_bit_by_one()
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.out_total_eof()
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.clear_bit_by_one()
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w.inlink_dscr_empty().clear_bit_by_one();
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w.outlink_dscr_error().clear_bit_by_one();
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w.inlink_dscr_error().clear_bit_by_one();
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w.in_done().clear_bit_by_one();
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w.in_err_eof().clear_bit_by_one();
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w.in_suc_eof().clear_bit_by_one();
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w.out_done().clear_bit_by_one();
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w.out_eof().clear_bit_by_one();
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w.out_total_eof().clear_bit_by_one()
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});
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}
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}
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@ -585,12 +567,9 @@ where
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#[cfg(not(esp32s2))]
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fn reset_dma_before_usr_cmd(reg_block: &RegisterBlock) {
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reg_block.dma_conf().modify(|_, w| {
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w.rx_afifo_rst()
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.set_bit()
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.buf_afifo_rst()
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.set_bit()
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.dma_afifo_rst()
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.set_bit()
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w.rx_afifo_rst().set_bit();
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w.buf_afifo_rst().set_bit();
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w.dma_afifo_rst().set_bit()
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});
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}
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@ -606,14 +585,10 @@ fn reset_dma_before_load_dma_dscr(_reg_block: &RegisterBlock) {}
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#[cfg(esp32s2)]
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fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
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reg_block.dma_conf().modify(|_, w| {
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w.out_rst()
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.set_bit()
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.in_rst()
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.set_bit()
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.ahbm_fifo_rst()
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.set_bit()
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.ahbm_rst()
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.set_bit()
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w.out_rst().set_bit();
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w.in_rst().set_bit();
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w.ahbm_fifo_rst().set_bit();
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w.ahbm_rst().set_bit()
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});
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#[cfg(esp32s2)]
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@ -622,14 +597,10 @@ fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
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.modify(|_, w| w.dma_infifo_full_clr().set_bit());
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reg_block.dma_conf().modify(|_, w| {
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w.out_rst()
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.clear_bit()
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.in_rst()
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.clear_bit()
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.ahbm_fifo_rst()
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.clear_bit()
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.ahbm_rst()
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.clear_bit()
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w.out_rst().clear_bit();
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w.in_rst().clear_bit();
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w.ahbm_fifo_rst().clear_bit();
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w.ahbm_rst().clear_bit()
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});
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#[cfg(esp32s2)]
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@ -638,19 +609,16 @@ fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
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.modify(|_, w| w.dma_infifo_full_clr().clear_bit());
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}
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impl<TX, RX> InstanceDma<RX, TX> for crate::peripherals::SPI2
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where
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RX: Rx,
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TX: Tx,
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{
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impl InstanceDma for crate::peripherals::SPI2 {
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fn dma_peripheral(&self) -> DmaPeripheral {
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DmaPeripheral::Spi2
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}
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}
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#[cfg(spi3)]
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impl<TX, RX> InstanceDma<RX, TX> for crate::peripherals::SPI3
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where
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RX: Rx,
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TX: Tx,
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{
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impl InstanceDma for crate::peripherals::SPI3 {
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fn dma_peripheral(&self) -> DmaPeripheral {
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DmaPeripheral::Spi3
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}
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}
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#[doc(hidden)]
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@ -680,93 +648,57 @@ pub trait Instance: private::Sealed {
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reg_block.slave().write(|w| w.mode().set_bit());
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reg_block.user().modify(|_, w| {
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w.usr_miso_highpart()
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.clear_bit()
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.doutdin()
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.set_bit()
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.usr_miso()
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.clear_bit()
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.usr_mosi()
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.clear_bit()
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.usr_dummy_idle()
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.clear_bit()
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.usr_addr()
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.clear_bit()
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.usr_command()
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.clear_bit()
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.sio()
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.clear_bit()
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w.usr_miso_highpart().clear_bit();
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w.doutdin().set_bit();
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w.usr_miso().clear_bit();
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w.usr_mosi().clear_bit();
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w.usr_dummy_idle().clear_bit();
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w.usr_addr().clear_bit();
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w.usr_command().clear_bit();
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w.sio().clear_bit()
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});
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#[cfg(not(esp32s2))]
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reg_block.clk_gate().modify(|_, w| {
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w.clk_en()
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.clear_bit()
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.mst_clk_active()
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.clear_bit()
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.mst_clk_sel()
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.clear_bit()
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w.clk_en().clear_bit();
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w.mst_clk_active().clear_bit();
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w.mst_clk_sel().clear_bit()
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});
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#[cfg(not(esp32s2))]
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reg_block.ctrl().modify(|_, w| {
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w.q_pol()
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.clear_bit()
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.d_pol()
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.clear_bit()
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.hold_pol()
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.clear_bit()
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w.q_pol().clear_bit();
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w.d_pol().clear_bit();
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#[cfg(not(esp32s2))]
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w.hold_pol().clear_bit();
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#[cfg(esp32s2)]
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w.wp().clear_bit();
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w
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});
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#[cfg(esp32s2)]
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reg_block
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.ctrl()
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.modify(|_, w| w.q_pol().clear_bit().d_pol().clear_bit().wp().clear_bit());
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reg_block.misc().write(|w| unsafe { w.bits(0) });
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}
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fn set_data_mode(&mut self, data_mode: SpiMode) -> &mut Self {
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let reg_block = self.register_block();
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match data_mode {
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SpiMode::Mode0 => {
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reg_block
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.user()
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.modify(|_, w| w.tsck_i_edge().clear_bit().rsck_i_edge().clear_bit());
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#[cfg(esp32s2)]
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reg_block.ctrl1().modify(|_, w| w.clk_mode_13().clear_bit());
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#[cfg(not(esp32s2))]
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reg_block.slave().modify(|_, w| w.clk_mode_13().clear_bit());
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}
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SpiMode::Mode1 => {
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reg_block
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.user()
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.modify(|_, w| w.tsck_i_edge().set_bit().rsck_i_edge().set_bit());
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#[cfg(esp32s2)]
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reg_block.ctrl1().modify(|_, w| w.clk_mode_13().set_bit());
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#[cfg(not(esp32s2))]
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reg_block.slave().modify(|_, w| w.clk_mode_13().set_bit());
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}
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SpiMode::Mode2 => {
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reg_block
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.user()
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.modify(|_, w| w.tsck_i_edge().set_bit().rsck_i_edge().set_bit());
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#[cfg(esp32s2)]
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reg_block.ctrl1().modify(|_, w| w.clk_mode_13().clear_bit());
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#[cfg(not(esp32s2))]
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reg_block.slave().modify(|_, w| w.clk_mode_13().clear_bit());
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}
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SpiMode::Mode3 => {
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reg_block
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.user()
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.modify(|_, w| w.tsck_i_edge().clear_bit().rsck_i_edge().clear_bit());
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#[cfg(esp32s2)]
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reg_block.ctrl1().modify(|_, w| w.clk_mode_13().set_bit());
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#[cfg(not(esp32s2))]
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reg_block.slave().modify(|_, w| w.clk_mode_13().set_bit());
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reg_block.user().modify(|_, w| {
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w.tsck_i_edge()
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.bit(matches!(data_mode, SpiMode::Mode1 | SpiMode::Mode2));
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w.rsck_i_edge()
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.bit(matches!(data_mode, SpiMode::Mode1 | SpiMode::Mode2))
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});
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cfg_if::cfg_if! {
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if #[cfg(esp32s2)] {
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let ctrl1_reg = reg_block.ctrl1();
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} else {
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let ctrl1_reg = reg_block.slave();
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}
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}
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ctrl1_reg.modify(|_, w| {
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w.clk_mode_13()
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.bit(matches!(data_mode, SpiMode::Mode1 | SpiMode::Mode3))
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});
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self
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}
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