Reordered RX-TX pairs to be consistent (#2074)

* feat: Update rx-tx order in i2s

* feat: Update rx-tx order in dma macros

* feat: Update rx-tx order in spi

* feat: Update rx-tx order in aes

* feat: Update rx-tx order in mem2mem

* feat: Update rx-tx order in twai and split methods

* feat: Update rx-tx order in twai

* feat: Update rx-tx order in twai and uart docs

* docs: Add sentence about order

* docs: Update changelog

* feat: Update rx-tx order in embassy_interrupt_spi_dma tests

* style: Rustfmt

* docs: Migrating guide

* fix: Typo

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Diff

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Tests rx-tx order

* fix: Update new_with_default_pins order

* feat: Update rx/tx order in hil_test::common_test_pins!

* feat: Update dma_extmem2mem example

* fix: Revert deleted input arg

* style: rustfmt

* feat: Disable test_asymmetric_dma_transfer for S2

---------

Co-authored-by: Dániel Buga <bugadani@gmail.com>

documentation/API-GUIDELINES.md

@@ -44,6 +44,7 @@ The following paragraphs contain additional recommendations.
     - Common cases of useless type info is storing pin information - this is usually not required after configuring the pins and will bloat the complexity of the type massively. When following the `PeripheralRef` pattern it's not needed in order to keep users from re-using the pin while in use
 - Avoiding `&mut self` when `&self` is safe to use. `&self` is generally easier to use as an API. Typical applications of this are where the methods just do writes to registers which don't have side effects.
     - For example starting a timer is fine for `&self`, worst case a timer will be started twice if two parts of the program call it. You can see a real example of this [here](https://github.com/esp-rs/esp-hal/pull/1500#pullrequestreview-2015911974)
+- Maintain order consistency in the API, such as in the case of pairs like RX/TX.
 
 ## Maintainability
 

esp-hal/CHANGELOG.md

@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Changed
 - Make saving and restoring SHA digest state an explicit operation (#2049)
+- Reordered RX-TX pairs in all APIs to be consistent (#2074)
 
 - `Delay::new()` is now a `const` function (#1999)
 - You can now create an `AnyPin` out of an `ErasedPin`. (#2072)

esp-hal/MIGRATING-0.20.md

@@ -50,6 +50,7 @@ However, if you want to, you can keep using their typed form!
 ```rust
 let pin = Input::new(io.gpio0); // pin will have the type `Input<'some>` (or `Input<'some, ErasedPin>` if you want to be explicit about it)
 let pin = Input::new_typed(io.gpio0); // pin will have the type `Input<'some, GpioPin<0>>`
+```
 
 ## `esp_hal::time::current_time` rename
 
@@ -59,3 +60,23 @@ To avoid confusion with the `Rtc::current_time` wall clock time APIs, we've rena
 - use esp_hal::time::current_time;
 + use esp_hal::time::now;
 ```
+
+## RX/TX Order
+
+Previously, our API was pretty inconsitent with the RX/TX ordering, and different peripherals had different order. Now, all
+the peripherals use rx-tx. Make sure your methods are expecting the rigth RX/TX order, for example an SPI DMA app should be updated to:
+
+```diff
+- let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(4);
++ let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
+let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
+let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+
+...
+
+ let transfer = spi
+-    .dma_transfer(dma_tx_buf, dma_rx_buf)
++    .dma_transfer(dma_rx_buf, dma_tx_buf)
+    .map_err(|e| e.0)
+    .unwrap();
+```

esp-hal/src/aes/mod.rs

@@ -243,7 +243,7 @@ pub mod dma {
             DmaChannel,
             DmaDescriptor,
             DmaPeripheral,
-            DmaTransferTxRx,
+            DmaTransferRxTx,
             ReadBuffer,
             RxPrivate,
             TxPrivate,
@@ -279,8 +279,8 @@ pub mod dma {
         pub aes: super::Aes<'d>,
 
         pub(crate) channel: Channel<'d, C, crate::Blocking>,
-        tx_chain: DescriptorChain,
         rx_chain: DescriptorChain,
+        tx_chain: DescriptorChain,
     }
 
     /// Functionality for using AES with DMA.
@@ -293,8 +293,8 @@ pub mod dma {
         fn with_dma(
             self,
             channel: Channel<'d, C, crate::Blocking>,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> AesDma<'d, C>;
     }
 
@@ -306,16 +306,16 @@ pub mod dma {
         fn with_dma(
             self,
             mut channel: Channel<'d, C, crate::Blocking>,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> AesDma<'d, C> {
             channel.tx.init_channel(); // no need to call this for both, TX and RX
 
             AesDma {
                 aes: self,
                 channel,
-                tx_chain: DescriptorChain::new(tx_descriptors),
                 rx_chain: DescriptorChain::new(rx_descriptors),
+                tx_chain: DescriptorChain::new(tx_descriptors),
             }
         }
     }
@@ -335,7 +335,7 @@ pub mod dma {
         C: DmaChannel,
         C::P: AesPeripheral,
     {
-        fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+        fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
             while self.aes.aes.state().read().state().bits() != 2 // DMA status DONE == 2
             && !self.channel.tx.is_done()
             {
@@ -408,7 +408,7 @@ pub mod dma {
 
         /// Perform a DMA transfer.
         ///
-        /// This will return a [DmaTransferTxRx]. The maximum amount of data to
+        /// This will return a [DmaTransferRxTx]. The maximum amount of data to
         /// be sent/received is 32736 bytes.
         pub fn process<'t, K, TXBUF, RXBUF>(
             &'t mut self,
@@ -417,7 +417,7 @@ pub mod dma {
             mode: Mode,
             cipher_mode: CipherMode,
             key: K,
-        ) -> Result<DmaTransferTxRx<'t, Self>, crate::dma::DmaError>
+        ) -> Result<DmaTransferRxTx<'t, Self>, crate::dma::DmaError>
         where
             K: Into<Key>,
             TXBUF: ReadBuffer,
@@ -427,25 +427,25 @@ pub mod dma {
             let (read_ptr, read_len) = unsafe { read_buffer.write_buffer() };
 
             self.start_transfer_dma(
-                write_ptr,
-                write_len,
                 read_ptr,
                 read_len,
+                write_ptr,
+                write_len,
                 mode,
                 cipher_mode,
                 key.into(),
             )?;
 
-            Ok(DmaTransferTxRx::new(self))
+            Ok(DmaTransferRxTx::new(self))
         }
 
         #[allow(clippy::too_many_arguments)]
         fn start_transfer_dma<K>(
             &mut self,
-            write_buffer_ptr: *const u8,
-            write_buffer_len: usize,
             read_buffer_ptr: *mut u8,
             read_buffer_len: usize,
+            write_buffer_ptr: *const u8,
+            write_buffer_len: usize,
             mode: Mode,
             cipher_mode: CipherMode,
             key: K,

esp-hal/src/dma/gdma.rs

@@ -674,8 +674,8 @@ mod m2m {
         MODE: crate::Mode,
     {
         channel: Channel<'d, C, MODE>,
-        tx_chain: DescriptorChain,
         rx_chain: DescriptorChain,
+        tx_chain: DescriptorChain,
         peripheral: DmaPeripheral,
     }
 
@@ -688,15 +688,15 @@ mod m2m {
         pub fn new(
             channel: Channel<'d, C, MODE>,
             peripheral: impl DmaEligible,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> Result<Self, DmaError> {
             unsafe {
                 Self::new_unsafe(
                     channel,
                     peripheral.dma_peripheral(),
-                    tx_descriptors,
                     rx_descriptors,
+                    tx_descriptors,
                     crate::dma::CHUNK_SIZE,
                 )
             }
@@ -706,16 +706,16 @@ mod m2m {
         pub fn new_with_chunk_size(
             channel: Channel<'d, C, MODE>,
             peripheral: impl DmaEligible,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
             chunk_size: usize,
         ) -> Result<Self, DmaError> {
             unsafe {
                 Self::new_unsafe(
                     channel,
                     peripheral.dma_peripheral(),
-                    tx_descriptors,
                     rx_descriptors,
+                    tx_descriptors,
                     chunk_size,
                 )
             }
@@ -730,8 +730,8 @@ mod m2m {
         pub unsafe fn new_unsafe(
             mut channel: Channel<'d, C, MODE>,
             peripheral: DmaPeripheral,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
             chunk_size: usize,
         ) -> Result<Self, DmaError> {
             if !(1..=4092).contains(&chunk_size) {
@@ -745,16 +745,16 @@ mod m2m {
             Ok(Mem2Mem {
                 channel,
                 peripheral,
-                tx_chain: DescriptorChain::new_with_chunk_size(tx_descriptors, chunk_size),
                 rx_chain: DescriptorChain::new_with_chunk_size(rx_descriptors, chunk_size),
+                tx_chain: DescriptorChain::new_with_chunk_size(tx_descriptors, chunk_size),
             })
         }
 
         /// Start a memory to memory transfer.
         pub fn start_transfer<'t, TXBUF, RXBUF>(
             &mut self,
-            tx_buffer: &'t TXBUF,
             rx_buffer: &'t mut RXBUF,
+            tx_buffer: &'t TXBUF,
         ) -> Result<DmaTransferRx<'_, Self>, DmaError>
         where
             TXBUF: ReadBuffer,
@@ -799,7 +799,7 @@ mod m2m {
         C: DmaChannel,
         MODE: crate::Mode,
     {
-        fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+        fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
             while !self.channel.rx.is_done() {}
         }
 

esp-hal/src/dma/mod.rs

@@ -294,10 +294,10 @@ mod pdma;
 /// Kinds of interrupt to listen to.
 #[derive(EnumSetType)]
 pub enum DmaInterrupt {
-    /// TX is done
-    TxDone,
     /// RX is done
     RxDone,
+    /// TX is done
+    TxDone,
 }
 
 /// The default chunk size used for DMA transfers.
@@ -310,16 +310,16 @@ pub const CHUNK_SIZE: usize = 4092;
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_buffers;
 ///
-/// // TX and RX buffers are 32000 bytes - passing only one parameter makes TX
+/// // RX and TX buffers are 32000 bytes - passing only one parameter makes RX
-/// // and RX the same size.
+/// // and TX the same size.
-/// let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+/// let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
 ///     dma_buffers!(32000, 32000);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_buffers {
-    ($tx_size:expr, $rx_size:expr) => {
+    ($rx_size:expr, $tx_size:expr) => {
-        $crate::dma_buffers_chunk_size!($tx_size, $rx_size, $crate::dma::CHUNK_SIZE)
+        $crate::dma_buffers_chunk_size!($rx_size, $tx_size, $crate::dma::CHUNK_SIZE)
     };
     ($size:expr) => {
         $crate::dma_buffers_chunk_size!($size, $crate::dma::CHUNK_SIZE)
@@ -333,16 +333,16 @@ macro_rules! dma_buffers {
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_circular_buffers;
 ///
-/// // TX and RX buffers are 32000 bytes - passing only one parameter makes TX
+/// // RX and TX buffers are 32000 bytes - passing only one parameter makes RX
-/// // and RX the same size.
+/// // and TX the same size.
-/// let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+/// let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
 ///     dma_circular_buffers!(32000, 32000);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_circular_buffers {
-    ($tx_size:expr, $rx_size:expr) => {
+    ($rx_size:expr, $tx_size:expr) => {
-        $crate::dma_circular_buffers_chunk_size!($tx_size, $rx_size, $crate::dma::CHUNK_SIZE)
+        $crate::dma_circular_buffers_chunk_size!($rx_size, $tx_size, $crate::dma::CHUNK_SIZE)
     };
 
     ($size:expr) => {
@@ -357,15 +357,15 @@ macro_rules! dma_circular_buffers {
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_descriptors;
 ///
-/// // Create TX and RX descriptors for transactions up to 32000 bytes - passing
+/// // Create RX and TX descriptors for transactions up to 32000 bytes - passing
-/// // only one parameter assumes TX and RX are the same size.
+/// // only one parameter assumes RX and TX are the same size.
-/// let (tx_descriptors, rx_descriptors) = dma_descriptors!(32000, 32000);
+/// let (rx_descriptors, tx_descriptors) = dma_descriptors!(32000, 32000);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_descriptors {
-    ($tx_size:expr, $rx_size:expr) => {
+    ($rx_size:expr, $tx_size:expr) => {
-        $crate::dma_descriptors_chunk_size!($tx_size, $rx_size, $crate::dma::CHUNK_SIZE)
+        $crate::dma_descriptors_chunk_size!($rx_size, $tx_size, $crate::dma::CHUNK_SIZE)
     };
 
     ($size:expr) => {
@@ -380,16 +380,16 @@ macro_rules! dma_descriptors {
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_circular_descriptors;
 ///
-/// // Create TX and RX descriptors for transactions up to 32000
+/// // Create RX and TX descriptors for transactions up to 32000
-/// // bytes - passing only one parameter assumes TX and RX are the same size.
+/// // bytes - passing only one parameter assumes RX and TX are the same size.
-/// let (tx_descriptors, rx_descriptors) =
+/// let (rx_descriptors, tx_descriptors) =
 ///     dma_circular_descriptors!(32000, 32000);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_circular_descriptors {
-    ($tx_size:expr, $rx_size:expr) => {
+    ($rx_size:expr, $tx_size:expr) => {
-        $crate::dma_circular_descriptors_chunk_size!($tx_size, $rx_size, $crate::dma::CHUNK_SIZE)
+        $crate::dma_circular_descriptors_chunk_size!($rx_size, $tx_size, $crate::dma::CHUNK_SIZE)
     };
 
     ($size:expr) => {
@@ -407,23 +407,23 @@ macro_rules! dma_circular_descriptors {
 ///
 /// // TX and RX buffers are 32000 bytes - passing only one parameter makes TX
 /// // and RX the same size.
-/// let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+/// let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
 ///     dma_buffers_chunk_size!(32000, 32000, 4032);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_buffers_chunk_size {
-    ($tx_size:expr, $rx_size:expr, $chunk_size:expr) => {{
+    ($rx_size:expr, $tx_size:expr, $chunk_size:expr) => {{
-        static mut TX_BUFFER: [u8; $tx_size] = [0u8; $tx_size];
         static mut RX_BUFFER: [u8; $rx_size] = [0u8; $rx_size];
-        let (mut tx_descriptors, mut rx_descriptors) =
+        static mut TX_BUFFER: [u8; $tx_size] = [0u8; $tx_size];
-            $crate::dma_descriptors_chunk_size!($tx_size, $rx_size, $chunk_size);
+        let (mut rx_descriptors, mut tx_descriptors) =
+            $crate::dma_descriptors_chunk_size!($rx_size, $tx_size, $chunk_size);
         unsafe {
             (
-                &mut TX_BUFFER,
-                tx_descriptors,
                 &mut RX_BUFFER,
                 rx_descriptors,
+                &mut TX_BUFFER,
+                tx_descriptors,
             )
         }
     }};
@@ -441,25 +441,25 @@ macro_rules! dma_buffers_chunk_size {
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_circular_buffers_chunk_size;
 ///
-/// // TX and RX buffers are 32000 bytes - passing only one parameter makes TX
+/// // RX and TX buffers are 32000 bytes - passing only one parameter makes RX
-/// // and RX the same size.
+/// // and TX the same size.
-/// let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+/// let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
 ///     dma_circular_buffers_chunk_size!(32000, 32000, 4032);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_circular_buffers_chunk_size {
-    ($tx_size:expr, $rx_size:expr, $chunk_size:expr) => {{
+    ($rx_size:expr, $tx_size:expr, $chunk_size:expr) => {{
-        static mut TX_BUFFER: [u8; $tx_size] = [0u8; $tx_size];
         static mut RX_BUFFER: [u8; $rx_size] = [0u8; $rx_size];
-        let (mut tx_descriptors, mut rx_descriptors) =
+        static mut TX_BUFFER: [u8; $tx_size] = [0u8; $tx_size];
-            $crate::dma_circular_descriptors_chunk_size!($tx_size, $rx_size, $chunk_size);
+        let (mut rx_descriptors, mut tx_descriptors) =
+            $crate::dma_circular_descriptors_chunk_size!($rx_size, $tx_size, $chunk_size);
         unsafe {
             (
-                &mut TX_BUFFER,
-                tx_descriptors,
                 &mut RX_BUFFER,
                 rx_descriptors,
+                &mut TX_BUFFER,
+                tx_descriptors,
             )
         }
     }};
@@ -476,26 +476,26 @@ macro_rules! dma_circular_buffers_chunk_size {
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_descriptors_chunk_size;
 ///
-/// // Create TX and RX descriptors for transactions up to 32000 bytes - passing
+/// // Create RX and TX descriptors for transactions up to 32000 bytes - passing
-/// // only one parameter assumes TX and RX are the same size.
+/// // only one parameter assumes RX and TX are the same size.
-/// let (tx_descriptors, rx_descriptors) =
+/// let (rx_descriptors, tx_descriptors) =
 ///     dma_descriptors_chunk_size!(32000, 32000, 4032);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_descriptors_chunk_size {
-    ($tx_size:expr, $rx_size:expr, $chunk_size:expr) => {{
+    ($rx_size:expr, $tx_size:expr, $chunk_size:expr) => {{
         // these will check for size at compile time
         const _: () = ::core::assert!($chunk_size <= 4092, "chunk size must be <= 4092");
         const _: () = ::core::assert!($chunk_size > 0, "chunk size must be > 0");
 
-        static mut TX_DESCRIPTORS: [$crate::dma::DmaDescriptor;
-            ($tx_size + $chunk_size - 1) / $chunk_size] =
-            [$crate::dma::DmaDescriptor::EMPTY; ($tx_size + $chunk_size - 1) / $chunk_size];
         static mut RX_DESCRIPTORS: [$crate::dma::DmaDescriptor;
             ($rx_size + $chunk_size - 1) / $chunk_size] =
             [$crate::dma::DmaDescriptor::EMPTY; ($rx_size + $chunk_size - 1) / $chunk_size];
-        unsafe { (&mut TX_DESCRIPTORS, &mut RX_DESCRIPTORS) }
+        static mut TX_DESCRIPTORS: [$crate::dma::DmaDescriptor;
+            ($tx_size + $chunk_size - 1) / $chunk_size] =
+            [$crate::dma::DmaDescriptor::EMPTY; ($tx_size + $chunk_size - 1) / $chunk_size];
+        unsafe { (&mut RX_DESCRIPTORS, &mut TX_DESCRIPTORS) }
     }};
 
     ($size:expr, $chunk_size:expr) => {
@@ -511,36 +511,36 @@ macro_rules! dma_descriptors_chunk_size {
 #[doc = crate::before_snippet!()]
 /// use esp_hal::dma_circular_descriptors_chunk_size;
 ///
-/// // Create TX and RX descriptors for transactions up to 32000 bytes - passing
+/// // Create RX and TX descriptors for transactions up to 32000 bytes - passing
-/// // only one parameter assumes TX and RX are the same size.
+/// // only one parameter assumes RX and TX are the same size.
-/// let (tx_descriptors, rx_descriptors) =
+/// let (rx_descriptors, tx_descriptors) =
 ///     dma_circular_descriptors_chunk_size!(32000, 32000, 4032);
 /// # }
 /// ```
 #[macro_export]
 macro_rules! dma_circular_descriptors_chunk_size {
-    ($tx_size:expr, $rx_size:expr, $chunk_size:expr) => {{
+    ($rx_size:expr, $tx_size:expr, $chunk_size:expr) => {{
         // these will check for size at compile time
         const _: () = ::core::assert!($chunk_size <= 4092, "chunk size must be <= 4092");
         const _: () = ::core::assert!($chunk_size > 0, "chunk size must be > 0");
 
-        const tx_descriptor_len: usize = if $tx_size > $chunk_size * 2 {
-            ($tx_size + $chunk_size - 1) / $chunk_size
-        } else {
-            3
-        };
-
         const rx_descriptor_len: usize = if $rx_size > $chunk_size * 2 {
             ($rx_size + $chunk_size - 1) / $chunk_size
         } else {
             3
         };
 
-        static mut TX_DESCRIPTORS: [$crate::dma::DmaDescriptor; tx_descriptor_len] =
+        const tx_descriptor_len: usize = if $tx_size > $chunk_size * 2 {
-            [$crate::dma::DmaDescriptor::EMPTY; tx_descriptor_len];
+            ($tx_size + $chunk_size - 1) / $chunk_size
+        } else {
+            3
+        };
+
         static mut RX_DESCRIPTORS: [$crate::dma::DmaDescriptor; rx_descriptor_len] =
             [$crate::dma::DmaDescriptor::EMPTY; rx_descriptor_len];
-        unsafe { (&mut TX_DESCRIPTORS, &mut RX_DESCRIPTORS) }
+        static mut TX_DESCRIPTORS: [$crate::dma::DmaDescriptor; tx_descriptor_len] =
+            [$crate::dma::DmaDescriptor::EMPTY; tx_descriptor_len];
+        unsafe { (&mut RX_DESCRIPTORS, &mut TX_DESCRIPTORS) }
     }};
 
     ($size:expr, $chunk_size:expr) => {
@@ -1872,10 +1872,10 @@ where
     CH: DmaChannel,
     MODE: Mode,
 {
-    /// TX half of the channel
-    pub tx: ChannelTx<'d, CH>,
     /// RX half of the channel
     pub rx: ChannelRx<'d, CH>,
+    /// TX half of the channel
+    pub tx: ChannelTx<'d, CH>,
     phantom: PhantomData<MODE>,
 }
 
@@ -1883,7 +1883,7 @@ impl<'d, C> Channel<'d, C, crate::Blocking>
 where
     C: DmaChannel,
 {
-    /// Sets the interrupt handler for TX and RX interrupts, enables them
+    /// Sets the interrupt handler for RX and TX interrupts, enables them
     /// with [crate::interrupt::Priority::max()]
     ///
     /// Interrupts are not enabled at the peripheral level here.
@@ -1895,8 +1895,8 @@ where
     pub fn listen(&mut self, interrupts: EnumSet<DmaInterrupt>) {
         for interrupt in interrupts {
             match interrupt {
-                DmaInterrupt::TxDone => self.tx.listen_ch_out_done(),
                 DmaInterrupt::RxDone => self.rx.listen_ch_in_done(),
+                DmaInterrupt::TxDone => self.tx.listen_ch_out_done(),
             }
         }
     }
@@ -1905,8 +1905,8 @@ where
     pub fn unlisten(&mut self, interrupts: EnumSet<DmaInterrupt>) {
         for interrupt in interrupts {
             match interrupt {
-                DmaInterrupt::TxDone => self.tx.unlisten_ch_out_done(),
                 DmaInterrupt::RxDone => self.rx.unlisten_ch_in_done(),
+                DmaInterrupt::TxDone => self.tx.unlisten_ch_out_done(),
             }
         }
     }
@@ -1914,12 +1914,12 @@ where
     /// Gets asserted interrupts
     pub fn interrupts(&mut self) -> EnumSet<DmaInterrupt> {
         let mut res = EnumSet::new();
-        if self.tx.is_done() {
-            res.insert(DmaInterrupt::TxDone);
-        }
         if self.rx.is_done() {
             res.insert(DmaInterrupt::RxDone);
         }
+        if self.tx.is_done() {
+            res.insert(DmaInterrupt::TxDone);
+        }
         res
     }
 
@@ -1927,14 +1927,14 @@ where
     pub fn clear_interrupts(&mut self, interrupts: EnumSet<DmaInterrupt>) {
         for interrupt in interrupts {
             match interrupt {
-                DmaInterrupt::TxDone => self.tx.clear_ch_out_done(),
                 DmaInterrupt::RxDone => self.rx.clear_ch_in_done(),
+                DmaInterrupt::TxDone => self.tx.clear_ch_out_done(),
             }
         }
     }
 }
 
-/// Error returned from Dma[Tx|Rx|TxRx]Buf operations.
+/// Error returned from Dma[Rx|Tx|RxTx]Buf operations.
 #[derive(Debug)]
 pub enum DmaBufError {
     /// More descriptors are needed for the buffer size
@@ -2295,14 +2295,14 @@ impl DmaRxBuf {
 /// descriptors of length 4092 each.
 /// It can be used for simultaneously transmitting to and receiving from a
 /// peripheral's FIFO. These are typically full-duplex transfers.
-pub struct DmaTxRxBuf {
+pub struct DmaRxTxBuf {
-    tx_descriptors: &'static mut [DmaDescriptor],
     rx_descriptors: &'static mut [DmaDescriptor],
+    tx_descriptors: &'static mut [DmaDescriptor],
     buffer: &'static mut [u8],
 }
 
-impl DmaTxRxBuf {
+impl DmaRxTxBuf {
-    /// Creates a new [DmaTxRxBuf] from some descriptors and a buffer.
+    /// Creates a new [DmaRxTxBuf] from some descriptors and a buffer.
     ///
     /// There must be enough descriptors for the provided buffer.
     /// Each descriptor can handle 4092 bytes worth of buffer.
@@ -2310,42 +2310,42 @@ impl DmaTxRxBuf {
     /// Both the descriptors and buffer must be in DMA-capable memory.
     /// Only DRAM is supported.
     pub fn new(
-        tx_descriptors: &'static mut [DmaDescriptor],
         rx_descriptors: &'static mut [DmaDescriptor],
+        tx_descriptors: &'static mut [DmaDescriptor],
         buffer: &'static mut [u8],
     ) -> Result<Self, DmaBufError> {
         let min_descriptors = buffer.len().div_ceil(CHUNK_SIZE);
-        if tx_descriptors.len() < min_descriptors {
-            return Err(DmaBufError::InsufficientDescriptors);
-        }
         if rx_descriptors.len() < min_descriptors {
             return Err(DmaBufError::InsufficientDescriptors);
         }
+        if tx_descriptors.len() < min_descriptors {
+            return Err(DmaBufError::InsufficientDescriptors);
+        }
 
-        if !is_slice_in_dram(tx_descriptors)
+        if !is_slice_in_dram(rx_descriptors)
-            || !is_slice_in_dram(rx_descriptors)
+            || !is_slice_in_dram(tx_descriptors)
             || !is_slice_in_dram(buffer)
         {
             return Err(DmaBufError::UnsupportedMemoryRegion);
         }
 
         // Reset the provided descriptors
-        tx_descriptors.fill(DmaDescriptor::EMPTY);
         rx_descriptors.fill(DmaDescriptor::EMPTY);
+        tx_descriptors.fill(DmaDescriptor::EMPTY);
 
         let descriptors = tx_descriptors.iter_mut().zip(rx_descriptors.iter_mut());
         let chunks = buffer.chunks_mut(CHUNK_SIZE);
 
-        for ((tx_desc, rx_desc), chunk) in descriptors.zip(chunks) {
+        for ((rx_desc, tx_desc), chunk) in descriptors.zip(chunks) {
-            tx_desc.set_size(chunk.len());
-            tx_desc.buffer = chunk.as_mut_ptr();
             rx_desc.set_size(chunk.len());
             rx_desc.buffer = chunk.as_mut_ptr();
+            tx_desc.set_size(chunk.len());
+            tx_desc.buffer = chunk.as_mut_ptr();
         }
 
         let mut buf = Self {
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
             buffer,
         };
         buf.set_length(buf.capacity());
@@ -2353,7 +2353,7 @@ impl DmaTxRxBuf {
         Ok(buf)
     }
 
-    /// Consume the buf, returning the tx descriptors, rx descriptors and
+    /// Consume the buf, returning the rx descriptors, tx descriptors and
     /// buffer.
     pub fn split(
         self,
@@ -2362,7 +2362,7 @@ impl DmaTxRxBuf {
         &'static mut [DmaDescriptor],
         &'static mut [u8],
     ) {
-        (self.tx_descriptors, self.rx_descriptors, self.buffer)
+        (self.rx_descriptors, self.tx_descriptors, self.buffer)
     }
 
     /// Return the size of the underlying buffer.
@@ -2390,13 +2390,13 @@ impl DmaTxRxBuf {
         // Get the minimum number of descriptors needed for this length of data.
         let descriptor_count = len.div_ceil(CHUNK_SIZE).max(1);
 
-        let relevant_tx_descriptors = &mut self.tx_descriptors[..descriptor_count];
         let relevant_rx_descriptors = &mut self.rx_descriptors[..descriptor_count];
+        let relevant_tx_descriptors = &mut self.tx_descriptors[..descriptor_count];
 
         // Link up the relevant descriptors.
         for descriptors in [
-            &mut relevant_tx_descriptors[..],
             &mut relevant_rx_descriptors[..],
+            &mut relevant_tx_descriptors[..],
         ] {
             let mut next = core::ptr::null_mut();
             for desc in descriptors.iter_mut().rev() {
@@ -2461,7 +2461,7 @@ pub(crate) mod dma_private {
         ///
         /// Please note: This is called in the transfer's `wait` function _and_
         /// by it's [Drop] implementation.
-        fn peripheral_wait_dma(&mut self, is_tx: bool, is_rx: bool);
+        fn peripheral_wait_dma(&mut self, is_rx: bool, is_tx: bool);
 
         /// Only used by circular DMA transfers in both, the `stop` function
         /// _and_ it's [Drop] implementation
@@ -2509,7 +2509,7 @@ where
 
     /// Wait for the transfer to finish.
     pub fn wait(self) -> Result<(), DmaError> {
-        self.instance.peripheral_wait_dma(true, false);
+        self.instance.peripheral_wait_dma(false, true);
 
         if self.instance.tx().has_error() {
             Err(DmaError::DescriptorError)
@@ -2557,7 +2557,7 @@ where
 
     /// Wait for the transfer to finish.
     pub fn wait(self) -> Result<(), DmaError> {
-        self.instance.peripheral_wait_dma(false, true);
+        self.instance.peripheral_wait_dma(true, false);
 
         if self.instance.rx().has_error() {
             Err(DmaError::DescriptorError)
@@ -2577,7 +2577,7 @@ where
     I: dma_private::DmaSupportRx,
 {
     fn drop(&mut self) {
-        self.instance.peripheral_wait_dma(false, true);
+        self.instance.peripheral_wait_dma(true, false);
     }
 }
 
@@ -2588,14 +2588,14 @@ where
 /// Never use [core::mem::forget] on an in-progress transfer
 #[non_exhaustive]
 #[must_use]
-pub struct DmaTransferTxRx<'a, I>
+pub struct DmaTransferRxTx<'a, I>
 where
     I: dma_private::DmaSupportTx + dma_private::DmaSupportRx,
 {
     instance: &'a mut I,
 }
 
-impl<'a, I> DmaTransferTxRx<'a, I>
+impl<'a, I> DmaTransferRxTx<'a, I>
 where
     I: dma_private::DmaSupportTx + dma_private::DmaSupportRx,
 {
@@ -2621,7 +2621,7 @@ where
     }
 }
 
-impl<'a, I> Drop for DmaTransferTxRx<'a, I>
+impl<'a, I> Drop for DmaTransferRxTx<'a, I>
 where
     I: dma_private::DmaSupportTx + dma_private::DmaSupportRx,
 {

esp-hal/src/i2s.rs

@@ -40,7 +40,7 @@
 //! let dma = Dma::new(peripherals.DMA);
 #![cfg_attr(any(esp32, esp32s2), doc = "let dma_channel = dma.i2s0channel;")]
 #![cfg_attr(not(any(esp32, esp32s2)), doc = "let dma_channel = dma.channel0;")]
-//! let (_, tx_descriptors, mut rx_buffer, rx_descriptors) =
+//! let (mut rx_buffer, rx_descriptors, _, tx_descriptors) =
 //! dma_buffers!(0, 4 * 4092);
 //!
 //! let i2s = I2s::new(
@@ -52,8 +52,8 @@
 //!         false,
 //!         DmaPriority::Priority0,
 //!     ),
-//!     tx_descriptors,
 //!     rx_descriptors,
+//!     tx_descriptors,
 //! );
 #![cfg_attr(not(esp32), doc = "let i2s = i2s.with_mclk(io.pins.gpio0);")]
 //! let mut i2s_rx = i2s.i2s_rx
@@ -119,16 +119,16 @@ use crate::{
 #[derive(EnumSetType)]
 /// Represents the various interrupt types for the I2S peripheral.
 pub enum I2sInterrupt {
-    /// Transmit buffer hung, indicating a stall in data transmission.
-    TxHung,
     /// Receive buffer hung, indicating a stall in data reception.
     RxHung,
-    #[cfg(not(any(esp32, esp32s2)))]
+    /// Transmit buffer hung, indicating a stall in data transmission.
-    /// Transmission of data is complete.
+    TxHung,
-    TxDone,
     #[cfg(not(any(esp32, esp32s2)))]
     /// Reception of data is complete.
     RxDone,
+    #[cfg(not(any(esp32, esp32s2)))]
+    /// Transmission of data is complete.
+    TxDone,
 }
 
 #[cfg(any(esp32, esp32s2, esp32s3))]
@@ -326,10 +326,10 @@ where
     CH: DmaChannel,
     DmaMode: Mode,
 {
-    /// Handles the transmission (TX) side of the I2S peripheral.
-    pub i2s_tx: TxCreator<'d, I, CH, DmaMode>,
     /// Handles the reception (RX) side of the I2S peripheral.
     pub i2s_rx: RxCreator<'d, I, CH, DmaMode>,
+    /// Handles the transmission (TX) side of the I2S peripheral.
+    pub i2s_tx: TxCreator<'d, I, CH, DmaMode>,
     phantom: PhantomData<DmaMode>,
 }
 
@@ -346,8 +346,8 @@ where
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
         mut channel: Channel<'d, CH, DmaMode>,
-        tx_descriptors: &'static mut [DmaDescriptor],
         rx_descriptors: &'static mut [DmaDescriptor],
+        tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self {
         // on ESP32-C3 / ESP32-S3 and later RX and TX are independent and
         // could be configured totally independently but for now handle all
@@ -362,18 +362,18 @@ where
         I::update();
 
         Self {
-            i2s_tx: TxCreator {
-                register_access: PhantomData,
-                tx_channel: channel.tx,
-                descriptors: tx_descriptors,
-                phantom: PhantomData,
-            },
             i2s_rx: RxCreator {
                 register_access: PhantomData,
                 rx_channel: channel.rx,
                 descriptors: rx_descriptors,
                 phantom: PhantomData,
             },
+            i2s_tx: TxCreator {
+                register_access: PhantomData,
+                tx_channel: channel.tx,
+                descriptors: tx_descriptors,
+                phantom: PhantomData,
+            },
             phantom: PhantomData,
         }
     }
@@ -447,8 +447,8 @@ where
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
         channel: Channel<'d, CH, DmaMode>,
-        tx_descriptors: &'static mut [DmaDescriptor],
         rx_descriptors: &'static mut [DmaDescriptor],
+        tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
     where
         I: I2s0Instance,
@@ -461,8 +461,8 @@ where
             data_format,
             sample_rate,
             channel,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         )
     }
 
@@ -476,8 +476,8 @@ where
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
         channel: Channel<'d, CH, DmaMode>,
-        tx_descriptors: &'static mut [DmaDescriptor],
         rx_descriptors: &'static mut [DmaDescriptor],
+        tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
     where
         I: I2s1Instance,
@@ -489,8 +489,8 @@ where
             data_format,
             sample_rate,
             channel,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         )
     }
 
@@ -532,7 +532,7 @@ where
     CH: DmaChannel,
     DmaMode: Mode,
 {
-    fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+    fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         self.wait_tx_dma_done().ok();
     }
 
@@ -713,7 +713,7 @@ where
     CH: DmaChannel,
     DmaMode: Mode,
 {
-    fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+    fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         T::wait_for_rx_done();
     }
 
@@ -1038,12 +1038,12 @@ mod private {
 
             for interrupt in interrupts {
                 match interrupt {
-                    I2sInterrupt::TxHung => {
-                        reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
-                    }
                     I2sInterrupt::RxHung => {
                         reg_block.int_ena().modify(|_, w| w.rx_hung().set_bit())
                     }
+                    I2sInterrupt::TxHung => {
+                        reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
+                    }
                 }
             }
         }
@@ -1053,12 +1053,12 @@ mod private {
 
             for interrupt in interrupts {
                 match interrupt {
-                    I2sInterrupt::TxHung => {
-                        reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
-                    }
                     I2sInterrupt::RxHung => {
                         reg_block.int_ena().modify(|_, w| w.rx_hung().clear_bit())
                     }
+                    I2sInterrupt::TxHung => {
+                        reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
+                    }
                 }
             }
         }
@@ -1068,12 +1068,12 @@ mod private {
             let reg_block = Self::register_block();
             let ints = reg_block.int_st().read();
 
-            if ints.tx_hung().bit() {
-                res.insert(I2sInterrupt::TxHung);
-            }
             if ints.rx_hung().bit() {
                 res.insert(I2sInterrupt::RxHung);
             }
+            if ints.tx_hung().bit() {
+                res.insert(I2sInterrupt::TxHung);
+            }
 
             res
         }
@@ -1083,12 +1083,12 @@ mod private {
 
             for interrupt in interrupts {
                 match interrupt {
-                    I2sInterrupt::TxHung => reg_block
-                        .int_clr()
-                        .write(|w| w.tx_hung().clear_bit_by_one()),
                     I2sInterrupt::RxHung => reg_block
                         .int_clr()
                         .write(|w| w.rx_hung().clear_bit_by_one()),
+                    I2sInterrupt::TxHung => reg_block
+                        .int_clr()
+                        .write(|w| w.tx_hung().clear_bit_by_one()),
                 }
             }
         }
@@ -1302,18 +1302,18 @@ mod private {
 
             for interrupt in interrupts {
                 match interrupt {
-                    I2sInterrupt::TxHung => {
-                        reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
-                    }
                     I2sInterrupt::RxHung => {
                         reg_block.int_ena().modify(|_, w| w.rx_hung().set_bit())
                     }
-                    I2sInterrupt::TxDone => {
+                    I2sInterrupt::TxHung => {
-                        reg_block.int_ena().modify(|_, w| w.tx_done().set_bit())
+                        reg_block.int_ena().modify(|_, w| w.tx_hung().set_bit())
                     }
                     I2sInterrupt::RxDone => {
                         reg_block.int_ena().modify(|_, w| w.rx_done().set_bit())
                     }
+                    I2sInterrupt::TxDone => {
+                        reg_block.int_ena().modify(|_, w| w.tx_done().set_bit())
+                    }
                 }
             }
         }
@@ -1323,18 +1323,18 @@ mod private {
 
             for interrupt in interrupts {
                 match interrupt {
-                    I2sInterrupt::TxHung => {
-                        reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
-                    }
                     I2sInterrupt::RxHung => {
                         reg_block.int_ena().modify(|_, w| w.rx_hung().clear_bit())
                     }
-                    I2sInterrupt::TxDone => {
+                    I2sInterrupt::TxHung => {
-                        reg_block.int_ena().modify(|_, w| w.tx_done().clear_bit())
+                        reg_block.int_ena().modify(|_, w| w.tx_hung().clear_bit())
                     }
                     I2sInterrupt::RxDone => {
                         reg_block.int_ena().modify(|_, w| w.rx_done().clear_bit())
                     }
+                    I2sInterrupt::TxDone => {
+                        reg_block.int_ena().modify(|_, w| w.tx_done().clear_bit())
+                    }
                 }
             }
         }
@@ -1344,18 +1344,18 @@ mod private {
             let reg_block = Self::register_block();
             let ints = reg_block.int_st().read();
 
-            if ints.tx_hung().bit() {
-                res.insert(I2sInterrupt::TxHung);
-            }
             if ints.rx_hung().bit() {
                 res.insert(I2sInterrupt::RxHung);
             }
-            if ints.tx_done().bit() {
+            if ints.tx_hung().bit() {
-                res.insert(I2sInterrupt::TxDone);
+                res.insert(I2sInterrupt::TxHung);
             }
             if ints.rx_done().bit() {
                 res.insert(I2sInterrupt::RxDone);
             }
+            if ints.tx_done().bit() {
+                res.insert(I2sInterrupt::TxDone);
+            }
 
             res
         }
@@ -1365,18 +1365,18 @@ mod private {
 
             for interrupt in interrupts {
                 match interrupt {
-                    I2sInterrupt::TxHung => reg_block
-                        .int_clr()
-                        .write(|w| w.tx_hung().clear_bit_by_one()),
                     I2sInterrupt::RxHung => reg_block
                         .int_clr()
                         .write(|w| w.rx_hung().clear_bit_by_one()),
-                    I2sInterrupt::TxDone => reg_block
+                    I2sInterrupt::TxHung => reg_block
                         .int_clr()
-                        .write(|w| w.tx_done().clear_bit_by_one()),
+                        .write(|w| w.tx_hung().clear_bit_by_one()),
                     I2sInterrupt::RxDone => reg_block
                         .int_clr()
                         .write(|w| w.rx_done().clear_bit_by_one()),
+                    I2sInterrupt::TxDone => reg_block
+                        .int_clr()
+                        .write(|w| w.tx_done().clear_bit_by_one()),
                 }
             }
         }

esp-hal/src/lcd_cam/cam.rs

@@ -26,7 +26,7 @@
 //! # let dma = Dma::new(peripherals.DMA);
 //! # let channel = dma.channel0;
 //!
-//! # let (tx_buffer, tx_descriptors, _, rx_descriptors) = dma_buffers!(32678, 0);
+//! # let (_, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32678, 0);
 //!
 //! # let channel = channel.configure(
 //! #     false,
@@ -218,7 +218,7 @@ where
 }
 
 impl<'d, CH: DmaChannel> DmaSupport for Camera<'d, CH> {
-    fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+    fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         loop {
             // Wait for IN_SUC_EOF (i.e. VSYNC)
             if self.rx_channel.is_done() {

esp-hal/src/lcd_cam/lcd/i8080.rs

@@ -24,7 +24,7 @@
 //! # let dma = Dma::new(peripherals.DMA);
 //! # let channel = dma.channel0;
 //!
-//! # let (tx_buffer, tx_descriptors, _, rx_descriptors) = dma_buffers!(32678, 0);
+//! # let ( _, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32678, 0);
 //!
 //! # let channel = channel.configure(
 //! #     false,
@@ -259,7 +259,7 @@ where
 }
 
 impl<'d, CH: DmaChannel, P: TxPins, DM: Mode> DmaSupport for I8080<'d, CH, P, DM> {
-    fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+    fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         let lcd_user = self.lcd_cam.lcd_user();
         // Wait until LCD_START is cleared by hardware.
         while lcd_user.read().lcd_start().bit_is_set() {}

esp-hal/src/parl_io.rs

@@ -1481,7 +1481,7 @@ where
     CH::P: ParlIoPeripheral,
     DM: Mode,
 {
-    fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+    fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         while !Instance::is_tx_eof() {}
 
         Instance::set_tx_start(false);
@@ -1576,7 +1576,7 @@ where
     CH::P: ParlIoPeripheral,
     DM: Mode,
 {
-    fn peripheral_wait_dma(&mut self, _is_tx: bool, _is_rx: bool) {
+    fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
         loop {
             if self.rx_channel.is_done()
                 || self.rx_channel.has_eof_error()

esp-hal/src/spi/master.rs

@@ -975,7 +975,7 @@ mod dma {
             C::P: SpiPeripheral + Spi2Peripheral,
             DmaMode: Mode,
         {
-            channel.tx.init_channel(); // no need to call this for both, TX and RX
+            channel.tx.init_channel(); // no need to call this for both, RX and TX
 
             SpiDma {
                 spi: self.spi,
@@ -1004,7 +1004,7 @@ mod dma {
             C::P: SpiPeripheral + Spi3Peripheral,
             DmaMode: Mode,
         {
-            channel.tx.init_channel(); // no need to call this for both, TX and RX
+            channel.tx.init_channel(); // no need to call this for both, RX and TX
 
             SpiDma {
                 spi: self.spi,
@@ -1137,15 +1137,15 @@ mod dma {
     {
         /// Configures the DMA buffers for the SPI instance.
         ///
-        /// This method sets up both TX and RX buffers for DMA transfers.
+        /// This method sets up both RX and TX buffers for DMA transfers.
         /// It returns an instance of `SpiDmaBus` that can be used for SPI
         /// communication.
         pub fn with_buffers(
             self,
-            dma_tx_buf: DmaTxBuf,
             dma_rx_buf: DmaRxBuf,
+            dma_tx_buf: DmaTxBuf,
         ) -> SpiDmaBus<'d, T, C, D, M> {
-            SpiDmaBus::new(self, dma_tx_buf, dma_rx_buf)
+            SpiDmaBus::new(self, dma_rx_buf, dma_tx_buf)
         }
     }
 
@@ -1190,7 +1190,7 @@ mod dma {
 
         /// Checks if the DMA transfer is complete.
         ///
-        /// This method returns `true` if both TX and RX operations are done,
+        /// This method returns `true` if both RX and TX operations are done,
         /// and the SPI instance is no longer busy.
         pub fn is_done(&self) -> bool {
             if self.is_tx && !self.tx_future_awaited && !self.spi_dma.channel.tx.is_done() {
@@ -1236,7 +1236,7 @@ mod dma {
     {
         /// Waits for the DMA transfer to complete asynchronously.
         ///
-        /// This method awaits the completion of both TX and RX operations.
+        /// This method awaits the completion of both RX and TX operations.
         pub async fn wait_for_done(&mut self) {
             if self.is_tx && !self.tx_future_awaited {
                 let _ = DmaTxFuture::new(&mut self.spi_dma.channel.tx).await;
@@ -1331,41 +1331,41 @@ mod dma {
         #[allow(clippy::type_complexity)]
         pub fn dma_transfer(
             mut self,
-            tx_buffer: DmaTxBuf,
             rx_buffer: DmaRxBuf,
+            tx_buffer: DmaTxBuf,
         ) -> Result<
-            SpiDmaTransfer<'d, T, C, FullDuplexMode, M, (DmaTxBuf, DmaRxBuf)>,
+            SpiDmaTransfer<'d, T, C, FullDuplexMode, M, (DmaRxBuf, DmaTxBuf)>,
-            (Error, Self, DmaTxBuf, DmaRxBuf),
+            (Error, Self, DmaRxBuf, DmaTxBuf),
         > {
-            let bytes_to_write = tx_buffer.len();
             let bytes_to_read = rx_buffer.len();
+            let bytes_to_write = tx_buffer.len();
 
             if bytes_to_write > MAX_DMA_SIZE || bytes_to_read > MAX_DMA_SIZE {
                 return Err((
                     Error::MaxDmaTransferSizeExceeded,
                     self,
-                    tx_buffer,
                     rx_buffer,
+                    tx_buffer,
                 ));
             }
 
             let result = unsafe {
                 self.spi.start_transfer_dma(
-                    tx_buffer.first(),
                     rx_buffer.first(),
-                    bytes_to_write,
+                    tx_buffer.first(),
                     bytes_to_read,
-                    &mut self.channel.tx,
+                    bytes_to_write,
                     &mut self.channel.rx,
+                    &mut self.channel.tx,
                 )
             };
             if let Err(e) = result {
-                return Err((e, self, tx_buffer, rx_buffer));
+                return Err((e, self, rx_buffer, tx_buffer));
             }
 
             Ok(SpiDmaTransfer::new(
                 self,
-                (tx_buffer, rx_buffer),
+                (rx_buffer, tx_buffer),
                 true,
                 true,
             ))
@@ -1553,10 +1553,10 @@ mod dma {
         D: DuplexMode,
         M: Mode,
     {
-        Idle(SpiDma<'d, T, C, D, M>, DmaTxBuf, DmaRxBuf),
+        Idle(SpiDma<'d, T, C, D, M>, DmaRxBuf, DmaTxBuf),
         Reading(SpiDmaTransfer<'d, T, C, D, M, DmaRxBuf>, DmaTxBuf),
         Writing(SpiDmaTransfer<'d, T, C, D, M, DmaTxBuf>, DmaRxBuf),
-        Transferring(SpiDmaTransfer<'d, T, C, D, M, (DmaTxBuf, DmaRxBuf)>),
+        Transferring(SpiDmaTransfer<'d, T, C, D, M, (DmaRxBuf, DmaTxBuf)>),
         #[default]
         TemporarilyRemoved,
     }
@@ -1588,11 +1588,11 @@ mod dma {
         /// buffers.
         pub fn new(
             spi: SpiDma<'d, T, C, D, M>,
-            dma_tx_buf: DmaTxBuf,
             dma_rx_buf: DmaRxBuf,
+            dma_tx_buf: DmaTxBuf,
         ) -> Self {
             Self {
-                state: State::Idle(spi, dma_tx_buf, dma_rx_buf),
+                state: State::Idle(spi, dma_rx_buf, dma_tx_buf),
             }
         }
 
@@ -1600,33 +1600,33 @@ mod dma {
         ///
         /// Interrupts are not enabled at the peripheral level here.
         pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             spi_dma.set_interrupt_handler(handler);
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
         }
 
         /// Listen for the given interrupts
         #[cfg(not(any(esp32, esp32s2)))]
         pub fn listen(&mut self, interrupts: EnumSet<SpiInterrupt>) {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             spi_dma.listen(interrupts);
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
         }
 
         /// Unlisten the given interrupts
         #[cfg(not(any(esp32, esp32s2)))]
         pub fn unlisten(&mut self, interrupts: EnumSet<SpiInterrupt>) {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             spi_dma.unlisten(interrupts);
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
         }
 
         /// Gets asserted interrupts
         #[cfg(not(any(esp32, esp32s2)))]
         pub fn interrupts(&mut self) -> EnumSet<SpiInterrupt> {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             let interrupts = spi_dma.interrupts();
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
             interrupts
         }
@@ -1634,32 +1634,32 @@ mod dma {
         /// Resets asserted interrupts
         #[cfg(not(any(esp32, esp32s2)))]
         pub fn clear_interrupts(&mut self, interrupts: EnumSet<SpiInterrupt>) {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             spi_dma.clear_interrupts(interrupts);
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
         }
 
         /// Changes the SPI bus frequency for the DMA-enabled SPI instance.
         pub fn change_bus_frequency(&mut self, frequency: HertzU32) {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             spi_dma.change_bus_frequency(frequency);
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
         }
 
-        fn wait_for_idle(&mut self) -> (SpiDma<'d, T, C, D, M>, DmaTxBuf, DmaRxBuf) {
+        fn wait_for_idle(&mut self) -> (SpiDma<'d, T, C, D, M>, DmaRxBuf, DmaTxBuf) {
             match core::mem::take(&mut self.state) {
-                State::Idle(spi, tx_buf, rx_buf) => (spi, tx_buf, rx_buf),
+                State::Idle(spi, rx_buf, tx_buf) => (spi, rx_buf, tx_buf),
                 State::Reading(transfer, tx_buf) => {
                     let (spi, rx_buf) = transfer.wait();
-                    (spi, tx_buf, rx_buf)
+                    (spi, rx_buf, tx_buf)
                 }
                 State::Writing(transfer, rx_buf) => {
                     let (spi, tx_buf) = transfer.wait();
-                    (spi, tx_buf, rx_buf)
+                    (spi, rx_buf, tx_buf)
                 }
                 State::Transferring(transfer) => {
-                    let (spi, (tx_buf, rx_buf)) = transfer.wait();
+                    let (spi, (rx_buf, tx_buf)) = transfer.wait();
-                    (spi, tx_buf, rx_buf)
+                    (spi, rx_buf, tx_buf)
                 }
                 State::TemporarilyRemoved => unreachable!(),
             }
@@ -1676,9 +1676,9 @@ mod dma {
     {
         /// Configures the interrupt handler for the DMA-enabled SPI instance.
         fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) {
-            let (mut spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             SpiDma::set_interrupt_handler(&mut spi_dma, handler);
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
         }
     }
 
@@ -1701,7 +1701,7 @@ mod dma {
     {
         /// Reads data from the SPI bus using DMA.
         pub fn read(&mut self, words: &mut [u8]) -> Result<(), Error> {
-            let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle();
 
             for chunk in words.chunks_mut(rx_buf.capacity()) {
                 rx_buf.set_length(chunk.len());
@@ -1709,24 +1709,24 @@ mod dma {
                 match spi_dma.dma_read(rx_buf) {
                     Ok(transfer) => self.state = State::Reading(transfer, tx_buf),
                     Err((e, spi, rx)) => {
-                        self.state = State::Idle(spi, tx_buf, rx);
+                        self.state = State::Idle(spi, rx, tx_buf);
                         return Err(e);
                     }
                 }
-                (spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+                (spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
 
                 let bytes_read = rx_buf.read_received_data(chunk);
                 debug_assert_eq!(bytes_read, chunk.len());
             }
 
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
             Ok(())
         }
 
         /// Writes data to the SPI bus using DMA.
         pub fn write(&mut self, words: &[u8]) -> Result<(), Error> {
-            let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle();
 
             for chunk in words.chunks(tx_buf.capacity()) {
                 tx_buf.fill(chunk);
@@ -1734,21 +1734,21 @@ mod dma {
                 match spi_dma.dma_write(tx_buf) {
                     Ok(transfer) => self.state = State::Writing(transfer, rx_buf),
                     Err((e, spi, tx)) => {
-                        self.state = State::Idle(spi, tx, rx_buf);
+                        self.state = State::Idle(spi, rx_buf, tx);
                         return Err(e);
                     }
                 }
-                (spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+                (spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
             }
 
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
             Ok(())
         }
 
         /// Transfers data to and from the SPI bus simultaneously using DMA.
         pub fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
-            let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle();
 
             let chunk_size = min(tx_buf.capacity(), rx_buf.capacity());
 
@@ -1763,20 +1763,20 @@ mod dma {
                 tx_buf.fill(write_chunk);
                 rx_buf.set_length(read_chunk.len());
 
-                match spi_dma.dma_transfer(tx_buf, rx_buf) {
+                match spi_dma.dma_transfer(rx_buf, tx_buf) {
                     Ok(transfer) => self.state = State::Transferring(transfer),
-                    Err((e, spi, tx, rx)) => {
+                    Err((e, spi, rx, tx)) => {
-                        self.state = State::Idle(spi, tx, rx);
+                        self.state = State::Idle(spi, rx, tx);
                         return Err(e);
                     }
                 }
-                (spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+                (spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
 
                 let bytes_read = rx_buf.read_received_data(read_chunk);
                 debug_assert_eq!(bytes_read, read_chunk.len());
             }
 
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
             if !read_remainder.is_empty() {
                 self.read(read_remainder)
@@ -1789,7 +1789,7 @@ mod dma {
 
         /// Transfers data in place on the SPI bus using DMA.
         pub fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Error> {
-            let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle();
 
             let chunk_size = min(tx_buf.capacity(), rx_buf.capacity());
 
@@ -1797,20 +1797,20 @@ mod dma {
                 tx_buf.fill(chunk);
                 rx_buf.set_length(chunk.len());
 
-                match spi_dma.dma_transfer(tx_buf, rx_buf) {
+                match spi_dma.dma_transfer(rx_buf, tx_buf) {
                     Ok(transfer) => self.state = State::Transferring(transfer),
-                    Err((e, spi, tx, rx)) => {
+                    Err((e, spi, rx, tx)) => {
-                        self.state = State::Idle(spi, tx, rx);
+                        self.state = State::Idle(spi, rx, tx);
                         return Err(e);
                     }
                 }
-                (spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+                (spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
 
                 let bytes_read = rx_buf.read_received_data(chunk);
                 debug_assert_eq!(bytes_read, chunk.len());
             }
 
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
             Ok(())
         }
     }
@@ -1833,7 +1833,7 @@ mod dma {
             dummy: u8,
             buffer: &mut [u8],
         ) -> Result<(), Self::Error> {
-            let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle();
             if buffer.len() > rx_buf.capacity() {
                 return Err(super::Error::DmaError(DmaError::Overflow));
             }
@@ -1843,16 +1843,16 @@ mod dma {
             match spi_dma.read(data_mode, cmd, address, dummy, rx_buf) {
                 Ok(transfer) => self.state = State::Reading(transfer, tx_buf),
                 Err((e, spi, rx)) => {
-                    self.state = State::Idle(spi, tx_buf, rx);
+                    self.state = State::Idle(spi, rx, tx_buf);
                     return Err(e);
                 }
             }
-            (spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            (spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
 
             let bytes_read = rx_buf.read_received_data(buffer);
             debug_assert_eq!(bytes_read, buffer.len());
 
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
             Ok(())
         }
@@ -1866,7 +1866,7 @@ mod dma {
             dummy: u8,
             buffer: &[u8],
         ) -> Result<(), Self::Error> {
-            let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle();
+            let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle();
             if buffer.len() > tx_buf.capacity() {
                 return Err(super::Error::DmaError(DmaError::Overflow));
             }
@@ -1876,13 +1876,13 @@ mod dma {
             match spi_dma.write(data_mode, cmd, address, dummy, tx_buf) {
                 Ok(transfer) => self.state = State::Writing(transfer, rx_buf),
                 Err((e, spi, tx)) => {
-                    self.state = State::Idle(spi, tx, rx_buf);
+                    self.state = State::Idle(spi, rx_buf, tx);
                     return Err(e);
                 }
             }
-            (spi_dma, tx_buf, rx_buf) = self.wait_for_idle();
+            (spi_dma, rx_buf, tx_buf) = self.wait_for_idle();
 
-            self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+            self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
             Ok(())
         }
@@ -1934,8 +1934,8 @@ mod dma {
                 &mut self,
             ) -> (
                 SpiDma<'d, T, C, FullDuplexMode, crate::Async>,
-                DmaTxBuf,
                 DmaRxBuf,
+                DmaTxBuf,
             ) {
                 match &mut self.state {
                     State::Idle(_, _, _) => (),
@@ -1945,18 +1945,18 @@ mod dma {
                     State::TemporarilyRemoved => unreachable!(),
                 }
                 match take(&mut self.state) {
-                    State::Idle(spi, tx_buf, rx_buf) => (spi, tx_buf, rx_buf),
+                    State::Idle(spi, rx_buf, tx_buf) => (spi, rx_buf, tx_buf),
                     State::Reading(transfer, tx_buf) => {
                         let (spi, rx_buf) = transfer.wait();
-                        (spi, tx_buf, rx_buf)
+                        (spi, rx_buf, tx_buf)
                     }
                     State::Writing(transfer, rx_buf) => {
                         let (spi, tx_buf) = transfer.wait();
-                        (spi, tx_buf, rx_buf)
+                        (spi, rx_buf, tx_buf)
                     }
                     State::Transferring(transfer) => {
-                        let (spi, (tx_buf, rx_buf)) = transfer.wait();
+                        let (spi, (rx_buf, tx_buf)) = transfer.wait();
-                        (spi, tx_buf, rx_buf)
+                        (spi, rx_buf, tx_buf)
                     }
                     State::TemporarilyRemoved => unreachable!(),
                 }
@@ -1965,7 +1965,7 @@ mod dma {
             /// Fill the given buffer with data from the bus.
             pub async fn read_async(&mut self, words: &mut [u8]) -> Result<(), super::Error> {
                 // Get previous transfer.
-                let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle_async().await;
+                let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle_async().await;
 
                 for chunk in words.chunks_mut(rx_buf.capacity()) {
                     rx_buf.set_length(chunk.len());
@@ -1975,18 +1975,18 @@ mod dma {
                             self.state = State::Reading(transfer, tx_buf);
                         }
                         Err((e, spi, rx)) => {
-                            self.state = State::Idle(spi, tx_buf, rx);
+                            self.state = State::Idle(spi, rx, tx_buf);
                             return Err(e);
                         }
                     };
 
-                    (spi_dma, tx_buf, rx_buf) = self.wait_for_idle_async().await;
+                    (spi_dma, rx_buf, tx_buf) = self.wait_for_idle_async().await;
 
                     let bytes_read = rx_buf.read_received_data(chunk);
                     debug_assert_eq!(bytes_read, chunk.len());
                 }
 
-                self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+                self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
                 Ok(())
             }
@@ -1994,7 +1994,7 @@ mod dma {
             /// Transmit the given buffer to the bus.
             pub async fn write_async(&mut self, words: &[u8]) -> Result<(), super::Error> {
                 // Get previous transfer.
-                let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle_async().await;
+                let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle_async().await;
 
                 for chunk in words.chunks(tx_buf.capacity()) {
                     tx_buf.fill(chunk);
@@ -2004,15 +2004,15 @@ mod dma {
                             self.state = State::Writing(transfer, rx_buf);
                         }
                         Err((e, spi, tx)) => {
-                            self.state = State::Idle(spi, tx, rx_buf);
+                            self.state = State::Idle(spi, rx_buf, tx);
                             return Err(e);
                         }
                     };
 
-                    (spi_dma, tx_buf, rx_buf) = self.wait_for_idle_async().await;
+                    (spi_dma, rx_buf, tx_buf) = self.wait_for_idle_async().await;
                 }
 
-                self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+                self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
                 Ok(())
             }
@@ -2025,7 +2025,7 @@ mod dma {
                 write: &[u8],
             ) -> Result<(), super::Error> {
                 // Get previous transfer.
-                let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle_async().await;
+                let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle_async().await;
 
                 let chunk_size = min(tx_buf.capacity(), rx_buf.capacity());
 
@@ -2040,23 +2040,23 @@ mod dma {
                     tx_buf.fill(write_chunk);
                     rx_buf.set_length(read_chunk.len());
 
-                    match spi_dma.dma_transfer(tx_buf, rx_buf) {
+                    match spi_dma.dma_transfer(rx_buf, tx_buf) {
                         Ok(transfer) => {
                             self.state = State::Transferring(transfer);
                         }
-                        Err((e, spi, tx, rx)) => {
+                        Err((e, spi, rx, tx)) => {
-                            self.state = State::Idle(spi, tx, rx);
+                            self.state = State::Idle(spi, rx, tx);
                             return Err(e);
                         }
                     };
 
-                    (spi_dma, tx_buf, rx_buf) = self.wait_for_idle_async().await;
+                    (spi_dma, rx_buf, tx_buf) = self.wait_for_idle_async().await;
 
                     let bytes_read = rx_buf.read_received_data(read_chunk);
                     assert_eq!(bytes_read, read_chunk.len());
                 }
 
-                self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+                self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
                 if !read_remainder.is_empty() {
                     self.read_async(read_remainder).await
@@ -2074,18 +2074,18 @@ mod dma {
                 words: &mut [u8],
             ) -> Result<(), super::Error> {
                 // Get previous transfer.
-                let (mut spi_dma, mut tx_buf, mut rx_buf) = self.wait_for_idle_async().await;
+                let (mut spi_dma, mut rx_buf, mut tx_buf) = self.wait_for_idle_async().await;
 
                 for chunk in words.chunks_mut(tx_buf.capacity()) {
                     tx_buf.fill(chunk);
                     rx_buf.set_length(chunk.len());
 
-                    match spi_dma.dma_transfer(tx_buf, rx_buf) {
+                    match spi_dma.dma_transfer(rx_buf, tx_buf) {
                         Ok(transfer) => {
                             self.state = State::Transferring(transfer);
                         }
-                        Err((e, spi, tx, rx)) => {
+                        Err((e, spi, rx, tx)) => {
-                            self.state = State::Idle(spi, tx, rx);
+                            self.state = State::Idle(spi, rx, tx);
                             return Err(e);
                         }
                     };
@@ -2095,10 +2095,10 @@ mod dma {
                         _ => unreachable!(),
                     };
 
-                    (spi_dma, tx_buf, rx_buf) = match take(&mut self.state) {
+                    (spi_dma, rx_buf, tx_buf) = match take(&mut self.state) {
                         State::Transferring(transfer) => {
-                            let (spi, (tx_buf, rx_buf)) = transfer.wait();
+                            let (spi, (rx_buf, tx_buf)) = transfer.wait();
-                            (spi, tx_buf, rx_buf)
+                            (spi, rx_buf, tx_buf)
                         }
                         _ => unreachable!(),
                     };
@@ -2107,7 +2107,7 @@ mod dma {
                     debug_assert_eq!(bytes_read, chunk.len());
                 }
 
-                self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+                self.state = State::Idle(spi_dma, rx_buf, tx_buf);
 
                 Ok(())
             }
@@ -2115,8 +2115,8 @@ mod dma {
             /// Flush any pending data in the SPI peripheral.
             pub async fn flush_async(&mut self) -> Result<(), super::Error> {
                 // Get previous transfer.
-                let (spi_dma, tx_buf, rx_buf) = self.wait_for_idle_async().await;
+                let (spi_dma, rx_buf, tx_buf) = self.wait_for_idle_async().await;
-                self.state = State::Idle(spi_dma, tx_buf, rx_buf);
+                self.state = State::Idle(spi_dma, rx_buf, tx_buf);
                 Ok(())
             }
         }
@@ -2294,20 +2294,20 @@ mod ehal1 {
 #[doc(hidden)]
 pub trait InstanceDma: Instance {
     #[allow(clippy::too_many_arguments)]
-    unsafe fn start_transfer_dma<TX: Tx, RX: Rx>(
+    unsafe fn start_transfer_dma<RX: Rx, TX: Tx>(
         &mut self,
-        tx_desc: *mut DmaDescriptor,
         rx_desc: *mut DmaDescriptor,
-        write_buffer_len: usize,
+        tx_desc: *mut DmaDescriptor,
         read_buffer_len: usize,
-        tx: &mut TX,
+        write_buffer_len: usize,
         rx: &mut RX,
+        tx: &mut TX,
     ) -> Result<(), Error> {
         let reg_block = self.register_block();
         self.configure_datalen(usize::max(read_buffer_len, write_buffer_len) as u32 * 8);
 
-        tx.is_done();
         rx.is_done();
+        tx.is_done();
 
         // re-enable the MISO and MOSI
         reg_block
@@ -2319,10 +2319,10 @@ pub trait InstanceDma: Instance {
 
         self.clear_dma_interrupts();
         reset_dma_before_load_dma_dscr(reg_block);
-        tx.prepare_transfer(self.dma_peripheral(), tx_desc)
-            .and_then(|_| tx.start_transfer())?;
         rx.prepare_transfer(self.dma_peripheral(), rx_desc)
             .and_then(|_| rx.start_transfer())?;
+        tx.prepare_transfer(self.dma_peripheral(), tx_desc)
+            .and_then(|_| tx.start_transfer())?;
 
         reset_dma_before_usr_cmd(reg_block);
 

esp-hal/src/spi/slave.rs

@@ -30,7 +30,7 @@
 //! let mosi = io.pins.gpio2;
 //! let cs = io.pins.gpio3;
 //!
-//! let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+//! let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
 //! dma_buffers!(32000); let mut spi = Spi::new(
 //!     peripherals.SPI2,
 //!     sclk,
@@ -42,13 +42,13 @@
 //! .with_dma(dma_channel.configure(
 //!     false,
 //!     DmaPriority::Priority0,
-//! ), tx_descriptors, rx_descriptors);
+//! ), rx_descriptors, tx_descriptors);
 //!
-//! let mut send = tx_buffer;
 //! let mut receive = rx_buffer;
+//! let mut send = tx_buffer;
 //!
 //! let transfer = spi
-//!     .dma_transfer(&mut send, &mut receive)
+//!     .dma_transfer(&mut receive, &mut send)
 //!     .unwrap();
 //!
 //! transfer.wait().unwrap();
@@ -163,8 +163,8 @@ pub mod dma {
             DmaChannel,
             DmaDescriptor,
             DmaTransferRx,
+            DmaTransferRxTx,
             DmaTransferTx,
-            DmaTransferTxRx,
             ReadBuffer,
             RxPrivate,
             Spi2Peripheral,
@@ -187,8 +187,8 @@ pub mod dma {
         fn with_dma(
             self,
             channel: Channel<'d, C, DmaMode>,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> SpiDma<'d, crate::peripherals::SPI2, C, DmaMode>;
     }
 
@@ -205,8 +205,8 @@ pub mod dma {
         fn with_dma(
             self,
             channel: Channel<'d, C, DmaMode>,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> SpiDma<'d, crate::peripherals::SPI3, C, DmaMode>;
     }
 
@@ -220,16 +220,16 @@ pub mod dma {
         fn with_dma(
             self,
             mut channel: Channel<'d, C, DmaMode>,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> SpiDma<'d, crate::peripherals::SPI2, C, DmaMode> {
             channel.tx.init_channel(); // no need to call this for both, TX and RX
 
             SpiDma {
                 spi: self.spi,
                 channel,
-                tx_chain: DescriptorChain::new(tx_descriptors),
                 rx_chain: DescriptorChain::new(rx_descriptors),
+                tx_chain: DescriptorChain::new(tx_descriptors),
             }
         }
     }
@@ -245,16 +245,16 @@ pub mod dma {
         fn with_dma(
             self,
             mut channel: Channel<'d, C, DmaMode>,
-            tx_descriptors: &'static mut [DmaDescriptor],
             rx_descriptors: &'static mut [DmaDescriptor],
+            tx_descriptors: &'static mut [DmaDescriptor],
         ) -> SpiDma<'d, crate::peripherals::SPI3, C, DmaMode> {
             channel.tx.init_channel(); // no need to call this for both, TX and RX
 
             SpiDma {
                 spi: self.spi,
                 channel,
-                tx_chain: DescriptorChain::new(tx_descriptors),
                 rx_chain: DescriptorChain::new(rx_descriptors),
+                tx_chain: DescriptorChain::new(tx_descriptors),
             }
         }
     }
@@ -268,8 +268,8 @@ pub mod dma {
     {
         pub(crate) spi: PeripheralRef<'d, T>,
         pub(crate) channel: Channel<'d, C, DmaMode>,
-        tx_chain: DescriptorChain,
         rx_chain: DescriptorChain,
+        tx_chain: DescriptorChain,
     }
 
     impl<'d, T, C, DmaMode> core::fmt::Debug for SpiDma<'d, T, C, DmaMode>
@@ -285,12 +285,12 @@ pub mod dma {
 
     impl<'d, T, C, DmaMode> DmaSupport for SpiDma<'d, T, C, DmaMode>
     where
-        T: InstanceDma<ChannelTx<'d, C>, ChannelRx<'d, C>>,
+        T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
         C: DmaChannel,
         C::P: SpiPeripheral,
         DmaMode: Mode,
     {
-        fn peripheral_wait_dma(&mut self, is_tx: bool, is_rx: bool) {
+        fn peripheral_wait_dma(&mut self, is_rx: bool, is_tx: bool) {
             while !((!is_tx || self.channel.tx.is_done())
                 && (!is_rx || self.channel.rx.is_done())
                 && !self.spi.is_bus_busy())
@@ -306,7 +306,7 @@ pub mod dma {
 
     impl<'d, T, C, DmaMode> DmaSupportTx for SpiDma<'d, T, C, DmaMode>
     where
-        T: InstanceDma<ChannelTx<'d, C>, ChannelRx<'d, C>>,
+        T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
         C: DmaChannel,
         C::P: SpiPeripheral,
         DmaMode: Mode,
@@ -324,7 +324,7 @@ pub mod dma {
 
     impl<'d, T, C, DmaMode> DmaSupportRx for SpiDma<'d, T, C, DmaMode>
     where
-        T: InstanceDma<ChannelTx<'d, C>, ChannelRx<'d, C>>,
+        T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
         C: DmaChannel,
         C::P: SpiPeripheral,
         DmaMode: Mode,
@@ -342,7 +342,7 @@ pub mod dma {
 
     impl<'d, T, C, DmaMode> SpiDma<'d, T, C, DmaMode>
     where
-        T: InstanceDma<ChannelTx<'d, C>, ChannelRx<'d, C>>,
+        T: InstanceDma<ChannelRx<'d, C>, ChannelTx<'d, C>>,
         C: DmaChannel,
         C::P: SpiPeripheral,
         DmaMode: Mode,
@@ -401,19 +401,19 @@ pub mod dma {
 
         /// Register buffers for a DMA transfer.
         ///
-        /// This will return a [DmaTransferTxRx]. The maximum amount of data to
+        /// This will return a [DmaTransferRxTx]. The maximum amount of data to
         /// be sent/received is 32736 bytes.
         ///
         /// The data transfer is driven by the SPI master's sclk signal and cs
         /// line.
-        pub fn dma_transfer<'t, TXBUF, RXBUF>(
+        pub fn dma_transfer<'t, RXBUF, TXBUF>(
             &'t mut self,
             words: &'t TXBUF,
             read_buffer: &'t mut RXBUF,
-        ) -> Result<DmaTransferTxRx<'t, Self>, Error>
+        ) -> Result<DmaTransferRxTx<'t, Self>, Error>
         where
-            TXBUF: ReadBuffer,
             RXBUF: WriteBuffer,
+            TXBUF: ReadBuffer,
         {
             let (write_ptr, write_len) = unsafe { words.read_buffer() };
             let (read_ptr, read_len) = unsafe { read_buffer.write_buffer() };
@@ -425,54 +425,54 @@ pub mod dma {
             unsafe {
                 self.spi
                     .start_transfer_dma(
-                        &mut self.tx_chain,
                         &mut self.rx_chain,
-                        write_ptr,
+                        &mut self.tx_chain,
-                        write_len,
                         read_ptr,
                         read_len,
-                        &mut self.channel.tx,
+                        write_ptr,
+                        write_len,
                         &mut self.channel.rx,
+                        &mut self.channel.tx,
                     )
-                    .map(move |_| DmaTransferTxRx::new(self))
+                    .map(move |_| DmaTransferRxTx::new(self))
             }
         }
     }
 }
 
 #[doc(hidden)]
-pub trait InstanceDma<TX, RX>: Instance
+pub trait InstanceDma<RX, TX>: Instance
 where
-    TX: Tx,
     RX: Rx,
+    TX: Tx,
 {
     #[allow(clippy::too_many_arguments)]
     unsafe fn start_transfer_dma(
         &mut self,
-        tx_chain: &mut DescriptorChain,
         rx_chain: &mut DescriptorChain,
-        write_buffer_ptr: *const u8,
+        tx_chain: &mut DescriptorChain,
-        write_buffer_len: usize,
         read_buffer_ptr: *mut u8,
         read_buffer_len: usize,
-        tx: &mut TX,
+        write_buffer_ptr: *const u8,
+        write_buffer_len: usize,
         rx: &mut RX,
+        tx: &mut TX,
     ) -> Result<(), Error> {
         let reg_block = self.register_block();
 
-        tx.is_done();
         rx.is_done();
+        tx.is_done();
 
         self.enable_dma();
 
         reset_dma_before_load_dma_dscr(reg_block);
 
-        tx_chain.fill_for_tx(false, write_buffer_ptr, write_buffer_len)?;
-        tx.prepare_transfer_without_start(self.dma_peripheral(), tx_chain)?;
-
         rx_chain.fill_for_rx(false, read_buffer_ptr, read_buffer_len)?;
         rx.prepare_transfer_without_start(self.dma_peripheral(), rx_chain)?;
 
+        tx_chain.fill_for_tx(false, write_buffer_ptr, write_buffer_len)?;
+        tx.prepare_transfer_without_start(self.dma_peripheral(), tx_chain)?;
+
         reset_dma_before_usr_cmd(reg_block);
 
         reg_block
@@ -680,18 +680,18 @@ fn reset_dma_before_load_dma_dscr(reg_block: &RegisterBlock) {
         .modify(|_, w| w.dma_infifo_full_clr().clear_bit());
 }
 
-impl<TX, RX> InstanceDma<TX, RX> for crate::peripherals::SPI2
+impl<TX, RX> InstanceDma<RX, TX> for crate::peripherals::SPI2
 where
-    TX: Tx,
     RX: Rx,
+    TX: Tx,
 {
 }
 
 #[cfg(spi3)]
-impl<TX, RX> InstanceDma<TX, RX> for crate::peripherals::SPI3
+impl<TX, RX> InstanceDma<RX, TX> for crate::peripherals::SPI3
 where
-    TX: Tx,
     RX: Rx,
+    TX: Tx,
 {
 }
 

esp-hal/src/twai/mod.rs

@@ -38,8 +38,8 @@
 //! # let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 //! // Use GPIO pins 2 and 3 to connect to the respective pins on the TWAI
 //! // transceiver.
-//! let can_tx_pin = io.pins.gpio2;
 //! let can_rx_pin = io.pins.gpio3;
+//! let can_tx_pin = io.pins.gpio2;
 //!
 //! // The speed of the TWAI bus.
 //! const TWAI_BAUDRATE: twai::BaudRate = BaudRate::B1000K;
@@ -48,8 +48,8 @@
 //! // state that prevents transmission but allows configuration.
 //! let mut can_config = twai::TwaiConfiguration::new(
 //!     peripherals.TWAI0,
-//!     can_tx_pin,
 //!     can_rx_pin,
+//!     can_tx_pin,
 //!     TWAI_BAUDRATE,
 //!     TwaiMode::Normal
 //! );
@@ -93,8 +93,8 @@
 //! # let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 //! // Use GPIO pins 2 and 3 to connect to the respective pins on the TWAI
 //! // transceiver.
-//! let can_tx_pin = io.pins.gpio2;
 //! let can_rx_pin = io.pins.gpio3;
+//! let can_tx_pin = io.pins.gpio2;
 //!
 //! // The speed of the TWAI bus.
 //! const TWAI_BAUDRATE: twai::BaudRate = BaudRate::B1000K;
@@ -102,8 +102,8 @@
 //! // Begin configuring the TWAI peripheral.
 //! let mut can_config = twai::TwaiConfiguration::new(
 //!     peripherals.TWAI0,
-//!     can_tx_pin,
 //!     can_rx_pin,
+//!     can_tx_pin,
 //!     TWAI_BAUDRATE,
 //!     TwaiMode::SelfTest
 //! );
@@ -718,8 +718,8 @@ where
 {
     fn new_internal<TX: OutputPin, RX: InputPin>(
         _peripheral: impl Peripheral<P = T> + 'd,
-        tx_pin: impl Peripheral<P = TX> + 'd,
         rx_pin: impl Peripheral<P = RX> + 'd,
+        tx_pin: impl Peripheral<P = TX> + 'd,
         baud_rate: BaudRate,
         no_transceiver: bool,
         mode: TwaiMode,
@@ -883,11 +883,11 @@ where
             .modify(|_, w| w.reset_mode().clear_bit());
 
         Twai {
-            tx: TwaiTx {
+            rx: TwaiRx {
                 _peripheral: PhantomData,
                 phantom: PhantomData,
             },
-            rx: TwaiRx {
+            tx: TwaiTx {
                 _peripheral: PhantomData,
                 phantom: PhantomData,
             },
@@ -903,14 +903,14 @@ where
     /// Create a new instance of [TwaiConfiguration]
     ///
     /// You will need to use a transceiver to connect to the TWAI bus
-    pub fn new<TX: OutputPin, RX: InputPin>(
+    pub fn new<RX: InputPin, TX: OutputPin>(
         peripheral: impl Peripheral<P = T> + 'd,
-        tx_pin: impl Peripheral<P = TX> + 'd,
         rx_pin: impl Peripheral<P = RX> + 'd,
+        tx_pin: impl Peripheral<P = TX> + 'd,
         baud_rate: BaudRate,
         mode: TwaiMode,
     ) -> Self {
-        Self::new_internal(peripheral, tx_pin, rx_pin, baud_rate, false, mode)
+        Self::new_internal(peripheral, rx_pin, tx_pin, baud_rate, false, mode)
     }
 
     /// Create a new instance of [TwaiConfiguration] meant to connect two ESP32s
@@ -918,14 +918,14 @@ where
     ///
     /// You don't need a transceiver by following the description in the
     /// `twai.rs` example
-    pub fn new_no_transceiver<TX: OutputPin, RX: InputPin>(
+    pub fn new_no_transceiver<RX: InputPin, TX: OutputPin>(
         peripheral: impl Peripheral<P = T> + 'd,
-        tx_pin: impl Peripheral<P = TX> + 'd,
         rx_pin: impl Peripheral<P = RX> + 'd,
+        tx_pin: impl Peripheral<P = TX> + 'd,
         baud_rate: BaudRate,
         mode: TwaiMode,
     ) -> Self {
-        Self::new_internal(peripheral, tx_pin, rx_pin, baud_rate, true, mode)
+        Self::new_internal(peripheral, rx_pin, tx_pin, baud_rate, true, mode)
     }
 }
 
@@ -947,14 +947,14 @@ where
     /// Create a new instance of [TwaiConfiguration] in async mode
     ///
     /// You will need to use a transceiver to connect to the TWAI bus
-    pub fn new_async<TX: OutputPin, RX: InputPin>(
+    pub fn new_async<RX: InputPin, TX: OutputPin>(
         peripheral: impl Peripheral<P = T> + 'd,
-        tx_pin: impl Peripheral<P = TX> + 'd,
         rx_pin: impl Peripheral<P = RX> + 'd,
+        tx_pin: impl Peripheral<P = TX> + 'd,
         baud_rate: BaudRate,
         mode: TwaiMode,
     ) -> Self {
-        let mut this = Self::new_internal(peripheral, tx_pin, rx_pin, baud_rate, false, mode);
+        let mut this = Self::new_internal(peripheral, rx_pin, tx_pin, baud_rate, false, mode);
         this.internal_set_interrupt_handler(T::async_handler());
         this
     }
@@ -964,14 +964,14 @@ where
     ///
     /// You don't need a transceiver by following the description in the
     /// `twai.rs` example
-    pub fn new_async_no_transceiver<TX: OutputPin, RX: InputPin>(
+    pub fn new_async_no_transceiver<RX: InputPin, TX: OutputPin>(
         peripheral: impl Peripheral<P = T> + 'd,
-        tx_pin: impl Peripheral<P = TX> + 'd,
         rx_pin: impl Peripheral<P = RX> + 'd,
+        tx_pin: impl Peripheral<P = TX> + 'd,
         baud_rate: BaudRate,
         mode: TwaiMode,
     ) -> Self {
-        let mut this = Self::new_internal(peripheral, tx_pin, rx_pin, baud_rate, true, mode);
+        let mut this = Self::new_internal(peripheral, rx_pin, tx_pin, baud_rate, true, mode);
         this.internal_set_interrupt_handler(T::async_handler());
         this
     }
@@ -1064,8 +1064,8 @@ where
 
     /// Consumes this `Twai` instance and splits it into transmitting and
     /// receiving halves.
-    pub fn split(self) -> (TwaiTx<'d, T, DM>, TwaiRx<'d, T, DM>) {
+    pub fn split(self) -> (TwaiRx<'d, T, DM>, TwaiTx<'d, T, DM>) {
-        (self.tx, self.rx)
+        (self.rx, self.tx)
     }
 }
 

esp-hal/src/uart.rs

@@ -17,7 +17,7 @@
 //!
 //! Each UART controller is individually configurable, and the usual setting
 //! such as baud rate, data bits, parity, and stop bits can easily be
-//! configured. Additionally, the transmit (TX) and receive (RX) pins need to
+//! configured. Additionally, the receive (RX) and transmit (TX) pins need to
 //! be specified.
 //!
 //! ```rust, no_run
@@ -69,7 +69,7 @@
 //! # }
 //! ```
 //! 
-//! ### Splitting the UART into TX and RX Components
+//! ### Splitting the UART into RX and TX Components
 //! ```rust, no_run
 #![doc = crate::before_snippet!()]
 //! # use esp_hal::uart::{config::Config, Uart};
@@ -82,7 +82,7 @@
 //! #     io.pins.gpio2,
 //! # ).unwrap();
 //! // The UART can be split into separate Transmit and Receive components:
-//! let (mut tx, mut rx) = uart1.split();
+//! let (mut rx, mut tx) = uart1.split();
 //!
 //! // Each component can be used individually to interact with the UART:
 //! tx.write_bytes(&[42u8]).expect("write error!");
@@ -90,7 +90,7 @@
 //! # }
 //! ```
 //! 
-//! ### Inverting TX and RX Pins
+//! ### Inverting RX and TX Pins
 //! ```rust, no_run
 #![doc = crate::before_snippet!()]
 //! # use esp_hal::uart::Uart;
@@ -98,17 +98,17 @@
 //!
 //! let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 //!
-//! let tx = AnyPin::new_inverted(io.pins.gpio1);
 //! let rx = AnyPin::new_inverted(io.pins.gpio2);
+//! let tx = AnyPin::new_inverted(io.pins.gpio1);
 //! let mut uart1 = Uart::new(
 //!     peripherals.UART1,
-//!     tx,
 //!     rx,
+//!     tx,
 //! ).unwrap();
 //! # }
 //! ```
 //! 
-//! ### Constructing TX and RX Components
+//! ### Constructing RX and TX Components
 //! ```rust, no_run
 #![doc = crate::before_snippet!()]
 //! # use esp_hal::uart::{UartTx, UartRx};
@@ -496,8 +496,8 @@ pub mod config {
 
 /// UART (Full-duplex)
 pub struct Uart<'d, T, M> {
-    tx: UartTx<'d, T, M>,
     rx: UartRx<'d, T, M>,
+    tx: UartTx<'d, T, M>,
 }
 
 /// UART (Transmit)
@@ -589,7 +589,7 @@ where
         tx.set_to_push_pull_output(Internal);
         tx.connect_peripheral_to_output(T::tx_signal(), Internal);
 
-        let (uart_tx, _) = Uart::<'d, T, Blocking>::new_with_config_inner(uart, config)?.split();
+        let (_, uart_tx) = Uart::<'d, T, Blocking>::new_with_config_inner(uart, config)?.split();
 
         Ok(uart_tx)
     }
@@ -794,7 +794,7 @@ where
         rx.set_to_input(Internal);
         rx.connect_input_to_peripheral(T::rx_signal(), Internal);
 
-        let (_, uart_rx) = Uart::<'d, T, Blocking>::new_with_config_inner(uart, config)?.split();
+        let (uart_rx, _) = Uart::<'d, T, Blocking>::new_with_config_inner(uart, config)?.split();
 
         Ok(uart_rx)
     }
@@ -809,8 +809,8 @@ where
     pub fn new_with_config<TX: OutputPin, RX: InputPin>(
         uart: impl Peripheral<P = T> + 'd,
         config: Config,
-        tx: impl Peripheral<P = TX> + 'd,
         rx: impl Peripheral<P = RX> + 'd,
+        tx: impl Peripheral<P = TX> + 'd,
     ) -> Result<Self, Error> {
         crate::into_ref!(tx);
         crate::into_ref!(rx);
@@ -825,8 +825,8 @@ where
     /// Create a new UART instance with defaults in [`Blocking`] mode.
     pub fn new<TX: OutputPin, RX: InputPin>(
         uart: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = TX> + 'd,
         rx: impl Peripheral<P = RX> + 'd,
+        tx: impl Peripheral<P = TX> + 'd,
     ) -> Result<Self, Error> {
         crate::into_ref!(tx);
         crate::into_ref!(rx);
@@ -842,8 +842,8 @@ where
     /// Verify that the default pins (DefaultTxPin and DefaultRxPin) are used.
     pub fn new_with_default_pins(
         uart: impl Peripheral<P = T> + 'd,
-        tx: &mut DefaultTxPin,
         rx: &mut DefaultRxPin,
+        tx: &mut DefaultTxPin,
     ) -> Result<Self, Error> {
         tx.set_to_push_pull_output(Internal);
         tx.connect_peripheral_to_output(T::tx_signal(), Internal);
@@ -866,11 +866,11 @@ where
         Self::init();
 
         let mut serial = Uart {
-            tx: UartTx::new_inner(),
             rx: UartRx::new_inner(
                 #[cfg(not(esp32))]
                 config.symbol_length(),
             ),
+            tx: UartTx::new_inner(),
         };
 
         serial
@@ -935,8 +935,8 @@ where
     ///
     /// This is particularly useful when having two tasks correlating to
     /// transmitting and receiving.
-    pub fn split(self) -> (UartTx<'d, T, M>, UartRx<'d, T, M>) {
+    pub fn split(self) -> (UartRx<'d, T, M>, UartTx<'d, T, M>) {
-        (self.tx, self.rx)
+        (self.rx, self.tx)
     }
 
     /// Write bytes out over the UART
@@ -2130,14 +2130,14 @@ mod asynch {
     {
         /// Create a new UART instance with configuration options in [`Async`]
         /// mode.
-        pub fn new_async_with_config<TX: OutputPin, RX: InputPin>(
+        pub fn new_async_with_config<RX: InputPin, TX: OutputPin>(
             uart: impl Peripheral<P = T> + 'd,
             config: Config,
-            tx: impl Peripheral<P = TX> + 'd,
             rx: impl Peripheral<P = RX> + 'd,
+            tx: impl Peripheral<P = TX> + 'd,
         ) -> Result<Self, Error> {
-            crate::into_ref!(tx);
             crate::into_ref!(rx);
+            crate::into_ref!(tx);
             tx.set_to_push_pull_output(Internal);
             tx.connect_peripheral_to_output(T::tx_signal(), Internal);
 
@@ -2159,21 +2159,21 @@ mod asynch {
         }
 
         /// Create a new UART instance with defaults in [`Async`] mode.
-        pub fn new_async<TX: OutputPin, RX: InputPin>(
+        pub fn new_async<RX: InputPin, TX: OutputPin>(
             uart: impl Peripheral<P = T> + 'd,
-            tx: impl Peripheral<P = TX> + 'd,
             rx: impl Peripheral<P = RX> + 'd,
+            tx: impl Peripheral<P = TX> + 'd,
         ) -> Result<Self, Error> {
-            Self::new_async_with_config(uart, Default::default(), tx, rx)
+            Self::new_async_with_config(uart, Default::default(), rx, tx)
         }
 
         /// Create a new UART instance with defaults in [`Async`] mode.
         pub fn new_async_with_default_pins(
             uart: impl Peripheral<P = T> + 'd,
-            tx: DefaultTxPin,
             rx: DefaultRxPin,
+            tx: DefaultTxPin,
         ) -> Result<Self, Error> {
-            Self::new_async_with_config(uart, Default::default(), tx, rx)
+            Self::new_async_with_config(uart, Default::default(), rx, tx)
         }
     }
 
@@ -2233,7 +2233,7 @@ mod asynch {
                 _ => unreachable!(),
             });
 
-            let (uart_tx, _) = uart.split();
+            let (_, uart_tx) = uart.split();
             Ok(uart_tx)
         }
 
@@ -2318,7 +2318,7 @@ mod asynch {
                 _ => unreachable!(),
             });
 
-            let (_, uart_rx) = uart.split();
+            let (uart_rx, _) = uart.split();
             Ok(uart_rx)
         }
 

esp-hal/src/usb_serial_jtag.rs

@@ -61,7 +61,7 @@
 //! let mut usb_serial = UsbSerialJtag::new(peripherals.USB_DEVICE);
 //! // The USB Serial/JTAG can be split into separate Transmit and Receive
 //! // components:
-//! let (mut tx, mut rx) = usb_serial.split();
+//! let (mut rx, mut tx) = usb_serial.split();
 //!
 //! // Each component can be used individually to interact with the USB
 //! // Serial/JTAG:
@@ -92,8 +92,8 @@ type Error = Infallible;
 
 /// USB Serial/JTAG (Full-duplex)
 pub struct UsbSerialJtag<'d, M> {
-    tx: UsbSerialJtagTx<'d, M>,
     rx: UsbSerialJtagRx<'d, M>,
+    tx: UsbSerialJtagTx<'d, M>,
 }
 
 /// USB Serial/JTAG (Transmit)
@@ -304,8 +304,8 @@ where
         }
 
         Self {
-            tx: UsbSerialJtagTx::new_inner(),
             rx: UsbSerialJtagRx::new_inner(),
+            tx: UsbSerialJtagTx::new_inner(),
         }
     }
 
@@ -319,8 +319,8 @@ where
     /// Split the USB Serial JTAG peripheral into a transmitter and receiver,
     /// which is particularly useful when having two tasks correlating to
     /// transmitting and receiving.
-    pub fn split(self) -> (UsbSerialJtagTx<'d, M>, UsbSerialJtagRx<'d, M>) {
+    pub fn split(self) -> (UsbSerialJtagRx<'d, M>, UsbSerialJtagTx<'d, M>) {
-        (self.tx, self.rx)
+        (self.rx, self.tx)
     }
 
     /// Write data to the serial output in chunks of up to 64 bytes

examples/src/bin/dma_extmem2mem.rs

@@ -69,7 +69,7 @@ fn main() -> ! {
 
     let mut extram_buffer: &mut [u8] = dma_alloc_buffer!(DATA_SIZE, 64);
     let mut intram_buffer = dma_buffer_aligned!(DATA_SIZE, A64);
-    let (tx_descriptors, rx_descriptors) = dma_descriptors_chunk_size!(DATA_SIZE, CHUNK_SIZE);
+    let (rx_descriptors, tx_descriptors) = dma_descriptors_chunk_size!(DATA_SIZE, CHUNK_SIZE);
 
     let dma = Dma::new(peripherals.DMA);
     let channel = dma.channel0.configure(false, DmaPriority::Priority0);
@@ -78,8 +78,8 @@ fn main() -> ! {
     let mut mem2mem = Mem2Mem::new_with_chunk_size(
         channel,
         dma_peripheral,
-        tx_descriptors,
         rx_descriptors,
+        tx_descriptors,
         CHUNK_SIZE,
     )
     .unwrap();
@@ -90,7 +90,7 @@ fn main() -> ! {
     }
 
     info!(" ext2int: Starting transfer of {} bytes", DATA_SIZE);
-    match mem2mem.start_transfer(&extram_buffer, &mut intram_buffer) {
+    match mem2mem.start_transfer(&mut intram_buffer, &extram_buffer) {
         Ok(dma_wait) => {
             info!("Transfer started");
             dma_wait.wait().unwrap();
@@ -122,7 +122,7 @@ fn main() -> ! {
     }
 
     info!(" int2ext: Starting transfer of {} bytes", DATA_SIZE);
-    match mem2mem.start_transfer(&intram_buffer, &mut extram_buffer) {
+    match mem2mem.start_transfer(&mut extram_buffer, &intram_buffer) {
         Ok(dma_wait) => {
             info!("Transfer started");
             dma_wait.wait().unwrap();

examples/src/bin/dma_mem2mem.rs

@@ -25,7 +25,7 @@ fn main() -> ! {
 
     let delay = Delay::new();
 
-    let (tx_buffer, tx_descriptors, mut rx_buffer, rx_descriptors) = dma_buffers!(DATA_SIZE);
+    let (mut rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE);
 
     let dma = Dma::new(peripherals.DMA);
     let channel = dma.channel0.configure(false, DmaPriority::Priority0);
@@ -35,14 +35,14 @@ fn main() -> ! {
     let dma_peripheral = peripherals.MEM2MEM1;
 
     let mut mem2mem =
-        Mem2Mem::new(channel, dma_peripheral, tx_descriptors, rx_descriptors).unwrap();
+        Mem2Mem::new(channel, dma_peripheral, rx_descriptors, tx_descriptors).unwrap();
 
     for i in 0..core::mem::size_of_val(tx_buffer) {
         tx_buffer[i] = (i % 256) as u8;
     }
 
     info!("Starting transfer of {} bytes", DATA_SIZE);
-    let result = mem2mem.start_transfer(&tx_buffer, &mut rx_buffer);
+    let result = mem2mem.start_transfer(&mut rx_buffer, tx_buffer);
     match result {
         Ok(dma_wait) => {
             info!("Transfer started");

examples/src/bin/embassy_i2s_read.rs

@@ -45,7 +45,7 @@ async fn main(_spawner: Spawner) {
     #[cfg(not(any(feature = "esp32", feature = "esp32s2")))]
     let dma_channel = dma.channel0;
 
-    let (_, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(0, 4092 * 4);
+    let (rx_buffer, rx_descriptors, _, tx_descriptors) = dma_buffers!(0, 4092 * 4);
 
     let i2s = I2s::new(
         peripherals.I2S0,
@@ -53,8 +53,8 @@ async fn main(_spawner: Spawner) {
         DataFormat::Data16Channel16,
         44100u32.Hz(),
         dma_channel.configure_for_async(false, DmaPriority::Priority0),
-        tx_descriptors,
         rx_descriptors,
+        tx_descriptors,
     );
 
     #[cfg(not(feature = "esp32"))]

examples/src/bin/embassy_i2s_sound.rs

@@ -67,7 +67,7 @@ async fn main(_spawner: Spawner) {
     #[cfg(not(any(feature = "esp32", feature = "esp32s2")))]
     let dma_channel = dma.channel0;
 
-    let (tx_buffer, tx_descriptors, _, rx_descriptors) = dma_buffers!(32000, 0);
+    let (_, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000, 0);
 
     let i2s = I2s::new(
         peripherals.I2S0,
@@ -75,8 +75,8 @@ async fn main(_spawner: Spawner) {
         DataFormat::Data16Channel16,
         44100u32.Hz(),
         dma_channel.configure_for_async(false, DmaPriority::Priority0),
-        tx_descriptors,
         rx_descriptors,
+        tx_descriptors,
     );
 
     let i2s_tx = i2s

examples/src/bin/embassy_parl_io_rx.rs

@@ -33,7 +33,7 @@ async fn main(_spawner: Spawner) {
 
     let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-    let (_, _, rx_buffer, rx_descriptors) = dma_buffers!(0, 32000);
+    let (rx_buffer, rx_descriptors, _, _) = dma_buffers!(0, 32000);
 
     let dma = Dma::new(peripherals.DMA);
     let dma_channel = dma.channel0;

examples/src/bin/embassy_parl_io_tx.rs

@@ -44,7 +44,7 @@ async fn main(_spawner: Spawner) {
 
     let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-    let (tx_buffer, tx_descriptors, _, _) = dma_buffers!(32000, 0);
+    let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(32000, 0);
 
     let dma = Dma::new(peripherals.DMA);
     let dma_channel = dma.channel0;

examples/src/bin/embassy_serial.rs

@@ -104,10 +104,10 @@ async fn main(spawner: Spawner) {
 
     let config = Config::default().rx_fifo_full_threshold(READ_BUF_SIZE as u16);
 
-    let mut uart0 = Uart::new_async_with_config(peripherals.UART0, config, tx_pin, rx_pin).unwrap();
+    let mut uart0 = Uart::new_async_with_config(peripherals.UART0, config, rx_pin, tx_pin).unwrap();
     uart0.set_at_cmd(AtCmdConfig::new(None, None, None, AT_CMD, None));
 
-    let (tx, rx) = uart0.split();
+    let (rx, tx) = uart0.split();
 
     static SIGNAL: StaticCell<Signal<NoopRawMutex, usize>> = StaticCell::new();
     let signal = &*SIGNAL.init(Signal::new());

examples/src/bin/embassy_spi.rs

@@ -54,14 +54,14 @@ async fn main(_spawner: Spawner) {
         }
     }
 
-    let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(32000);
+    let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
-    let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
     let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+    let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
     let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
         .with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs))
         .with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0))
-        .with_buffers(dma_tx_buf, dma_rx_buf);
+        .with_buffers(dma_rx_buf, dma_tx_buf);
 
     let send_buffer = [0, 1, 2, 3, 4, 5, 6, 7];
     loop {

examples/src/bin/embassy_twai.rs

@@ -101,8 +101,8 @@ async fn main(spawner: Spawner) {
     // state that prevents transmission but allows configuration.
     let mut can_config = twai::TwaiConfiguration::new_async_no_transceiver(
         peripherals.TWAI0,
-        can_tx_pin,
         can_rx_pin,
+        can_tx_pin,
         CAN_BAUDRATE,
         TwaiMode::Normal,
     );
@@ -123,7 +123,7 @@ async fn main(spawner: Spawner) {
     let can = can_config.start();
 
     // Get separate transmit and receive halves of the peripheral.
-    let (tx, rx) = can.split();
+    let (rx, tx) = can.split();
 
     interrupt::enable(
         peripherals::Interrupt::TWAI0,

examples/src/bin/embassy_usb_serial_jtag.rs

@@ -68,7 +68,7 @@ async fn main(spawner: Spawner) {
     let timg0 = TimerGroup::new(peripherals.TIMG0);
     esp_hal_embassy::init(timg0.timer0);
 
-    let (tx, rx) = UsbSerialJtag::new_async(peripherals.USB_DEVICE).split();
+    let (rx, tx) = UsbSerialJtag::new_async(peripherals.USB_DEVICE).split();
 
     static SIGNAL: StaticCell<Signal<NoopRawMutex, heapless::String<MAX_BUFFER_SIZE>>> =
         StaticCell::new();

examples/src/bin/hello_world.rs

@@ -43,7 +43,7 @@ fn main() -> ! {
     }
 
     let mut uart0 =
-        Uart::new_with_default_pins(peripherals.UART0, &mut tx_pin, &mut rx_pin).unwrap();
+        Uart::new_with_default_pins(peripherals.UART0, &mut rx_pin, &mut tx_pin).unwrap();
 
     loop {
         writeln!(uart0, "Hello world!").unwrap();

examples/src/bin/i2s_read.rs

@@ -38,7 +38,7 @@ fn main() -> ! {
     #[cfg(not(any(feature = "esp32", feature = "esp32s2")))]
     let dma_channel = dma.channel0;
 
-    let (_, tx_descriptors, mut rx_buffer, rx_descriptors) = dma_buffers!(0, 4 * 4092);
+    let (mut rx_buffer, rx_descriptors, _, tx_descriptors) = dma_buffers!(0, 4 * 4092);
 
     // Here we test that the type is
     // 1) reasonably simple (or at least this will flag changes that may make it
@@ -50,8 +50,8 @@ fn main() -> ! {
         DataFormat::Data16Channel16,
         44100.Hz(),
         dma_channel.configure(false, DmaPriority::Priority0),
-        tx_descriptors,
         rx_descriptors,
+        tx_descriptors,
     );
 
     #[cfg(not(feature = "esp32"))]

examples/src/bin/i2s_sound.rs

@@ -59,7 +59,7 @@ fn main() -> ! {
     #[cfg(not(any(feature = "esp32", feature = "esp32s2")))]
     let dma_channel = dma.channel0;
 
-    let (tx_buffer, tx_descriptors, _, rx_descriptors) = dma_buffers!(32000, 0);
+    let (_, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000, 0);
 
     let i2s = I2s::new(
         peripherals.I2S0,
@@ -67,8 +67,8 @@ fn main() -> ! {
         DataFormat::Data16Channel16,
         44100.Hz(),
         dma_channel.configure(false, DmaPriority::Priority0),
-        tx_descriptors,
         rx_descriptors,
+        tx_descriptors,
     );
 
     let mut i2s_tx = i2s

examples/src/bin/ieee802154_sniffer.rs

@@ -28,7 +28,7 @@ fn main() -> ! {
     }
 
     let mut uart0 =
-        Uart::new_with_default_pins(peripherals.UART0, &mut tx_pin, &mut rx_pin).unwrap();
+        Uart::new_with_default_pins(peripherals.UART0, &mut rx_pin, &mut tx_pin).unwrap();
 
     // read two characters which get parsed as the channel
     let mut cnt = 0;

examples/src/bin/lcd_cam_ov2640.rs

@@ -49,7 +49,7 @@ fn main() -> ! {
     let dma = Dma::new(peripherals.DMA);
     let channel = dma.channel0;
 
-    let (_, _, rx_buffer, rx_descriptors) = dma_buffers!(0, 32678);
+    let (rx_buffer, rx_descriptors, _, _) = dma_buffers!(0, 32678);
 
     let channel = channel.configure(false, DmaPriority::Priority0);
 

examples/src/bin/lcd_i8080.rs

@@ -50,7 +50,7 @@ fn main() -> ! {
     let dma = Dma::new(peripherals.DMA);
     let channel = dma.channel0;
 
-    let (tx_buffer, tx_descriptors, _, _) = dma_buffers!(32678, 0);
+    let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(32678, 0);
 
     let channel = channel.configure(false, DmaPriority::Priority0);
 

examples/src/bin/parl_io_rx.rs

@@ -26,7 +26,7 @@ fn main() -> ! {
 
     let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-    let (_, _, rx_buffer, rx_descriptors) = dma_buffers!(0, 32000);
+    let (rx_buffer, rx_descriptors, _, _) = dma_buffers!(0, 32000);
 
     let dma = Dma::new(peripherals.DMA);
     let dma_channel = dma.channel0;

examples/src/bin/parl_io_tx.rs

@@ -37,7 +37,7 @@ fn main() -> ! {
 
     let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-    let (tx_buffer, tx_descriptors, _, _) = dma_buffers!(32000, 0);
+    let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(32000, 0);
 
     let dma = Dma::new(peripherals.DMA);
     let dma_channel = dma.channel0;

examples/src/bin/qspi_flash.rs

@@ -75,9 +75,9 @@ fn main() -> ! {
         }
     }
 
-    let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(256, 320);
+    let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(256, 320);
-    let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
     let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+    let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
     let mut spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
         .with_pins(

examples/src/bin/spi_loopback_dma.rs

@@ -49,9 +49,9 @@ fn main() -> ! {
         }
     }
 
-    let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(32000);
+    let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
-    let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
     let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+    let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
     let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
         .with_pins(Some(sclk), Some(mosi), Some(miso), Some(cs))
@@ -71,7 +71,7 @@ fn main() -> ! {
         i = i.wrapping_add(1);
 
         let transfer = spi
-            .dma_transfer(dma_tx_buf, dma_rx_buf)
+            .dma_transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
         // here we could do something else while DMA transfer is in progress
@@ -83,7 +83,7 @@ fn main() -> ! {
             n += 1;
         }
 
-        (spi, (dma_tx_buf, dma_rx_buf)) = transfer.wait();
+        (spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
         println!(
             "{:x?} .. {:x?}",
             &dma_rx_buf.as_slice()[..10],

examples/src/bin/spi_slave_dma.rs

@@ -68,7 +68,7 @@ fn main() -> ! {
         }
     }
 
-    let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(32000);
+    let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
 
     let mut spi = Spi::new(
         peripherals.SPI2,
@@ -113,7 +113,7 @@ fn main() -> ! {
         println!("Do `dma_transfer`");
 
         let transfer = spi
-            .dma_transfer(&mut slave_send, &mut slave_receive)
+            .dma_transfer(&mut slave_receive, &mut slave_send)
             .unwrap();
 
         bitbang_master(

examples/src/bin/twai.rs

@@ -53,8 +53,8 @@ fn main() -> ! {
     // For self-testing use `SelfTest` mode of the TWAI peripheral.
     let mut can_config = twai::TwaiConfiguration::new_no_transceiver(
         peripherals.TWAI0,
-        can_tx_pin,
         can_rx_pin,
+        can_tx_pin,
         CAN_BAUDRATE,
         TwaiMode::Normal,
     );

hil-test/tests/aes_dma.rs

@@ -36,12 +36,12 @@ mod tests {
         let dma = Dma::new(peripherals.DMA);
         let dma_channel = dma.channel0;
 
-        let (input, tx_descriptors, mut output, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
         let mut aes = Aes::new(peripherals.AES).with_dma(
             dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         );
 
         let keytext = b"SUp4SeCp@sSw0rd";
@@ -78,12 +78,12 @@ mod tests {
         let dma = Dma::new(peripherals.DMA);
         let dma_channel = dma.channel0;
 
-        let (input, tx_descriptors, mut output, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
         let mut aes = Aes::new(peripherals.AES).with_dma(
             dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         );
 
         let keytext = b"SUp4SeCp@sSw0rd";
@@ -119,12 +119,12 @@ mod tests {
         let dma = Dma::new(peripherals.DMA);
         let dma_channel = dma.channel0;
 
-        let (input, tx_descriptors, mut output, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
         let mut aes = Aes::new(peripherals.AES).with_dma(
             dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         );
 
         let keytext = b"SUp4SeCp@sSw0rd";
@@ -161,12 +161,12 @@ mod tests {
         let dma = Dma::new(peripherals.DMA);
         let dma_channel = dma.channel0;
 
-        let (input, tx_descriptors, mut output, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (mut output, rx_descriptors, input, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
 
         let mut aes = Aes::new(peripherals.AES).with_dma(
             dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         );
 
         let keytext = b"SUp4SeCp@sSw0rd";

hil-test/tests/dma_macros.rs

@@ -34,33 +34,33 @@ mod tests {
     #[test]
     fn test_dma_descriptors_same_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        let (tx_descriptors, rx_descriptors) = esp_hal::dma_descriptors!(DATA_SIZE);
+        let (rx_descriptors, tx_descriptors) = esp_hal::dma_descriptors!(DATA_SIZE);
-        assert_eq!(tx_descriptors.len(), rx_descriptors.len());
+        assert_eq!(rx_descriptors.len(), tx_descriptors.len());
-        assert_eq!(tx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
         assert_eq!(rx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
     }
 
     #[test]
     fn test_dma_descriptors_different_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        const TX_SIZE: usize = DATA_SIZE;
         const RX_SIZE: usize = DATA_SIZE / 2;
-        let (tx_descriptors, rx_descriptors) = esp_hal::dma_descriptors!(TX_SIZE, RX_SIZE);
+        const TX_SIZE: usize = DATA_SIZE;
-        assert_eq!(tx_descriptors.len(), compute_size(TX_SIZE, CHUNK_SIZE));
+        let (rx_descriptors, tx_descriptors) = esp_hal::dma_descriptors!(RX_SIZE, TX_SIZE);
         assert_eq!(rx_descriptors.len(), compute_size(RX_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_descriptors.len(), compute_size(TX_SIZE, CHUNK_SIZE));
     }
 
     #[test]
     fn test_dma_circular_descriptors_same_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        let (tx_descriptors, rx_descriptors) = esp_hal::dma_circular_descriptors!(DATA_SIZE);
+        let (rx_descriptors, tx_descriptors) = esp_hal::dma_circular_descriptors!(DATA_SIZE);
-        assert_eq!(tx_descriptors.len(), rx_descriptors.len());
+        assert_eq!(rx_descriptors.len(), tx_descriptors.len());
         assert_eq!(
-            tx_descriptors.len(),
+            rx_descriptors.len(),
             compute_circular_size(DATA_SIZE, CHUNK_SIZE)
         );
         assert_eq!(
-            rx_descriptors.len(),
+            tx_descriptors.len(),
             compute_circular_size(DATA_SIZE, CHUNK_SIZE)
         );
     }
@@ -68,59 +68,59 @@ mod tests {
     #[test]
     fn test_dma_circular_descriptors_different_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        const TX_SIZE: usize = CHUNK_SIZE * 2;
         const RX_SIZE: usize = DATA_SIZE / 2;
-        let (tx_descriptors, rx_descriptors) = esp_hal::dma_circular_descriptors!(TX_SIZE, RX_SIZE);
+        const TX_SIZE: usize = CHUNK_SIZE * 2;
-        assert_eq!(
+        let (rx_descriptors, tx_descriptors) = esp_hal::dma_circular_descriptors!(RX_SIZE, TX_SIZE);
-            tx_descriptors.len(),
-            compute_circular_size(TX_SIZE, CHUNK_SIZE)
-        );
         assert_eq!(
             rx_descriptors.len(),
             compute_circular_size(RX_SIZE, CHUNK_SIZE)
         );
+        assert_eq!(
+            tx_descriptors.len(),
+            compute_circular_size(TX_SIZE, CHUNK_SIZE)
+        );
     }
 
     #[test]
     fn test_dma_buffers_same_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
             esp_hal::dma_buffers!(DATA_SIZE);
-        assert_eq!(tx_buffer.len(), DATA_SIZE);
         assert_eq!(rx_buffer.len(), DATA_SIZE);
+        assert_eq!(tx_buffer.len(), DATA_SIZE);
         assert_eq!(tx_descriptors.len(), rx_descriptors.len());
-        assert_eq!(tx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
         assert_eq!(rx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
     }
 
     #[test]
     fn test_dma_buffers_different_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        const TX_SIZE: usize = DATA_SIZE;
         const RX_SIZE: usize = DATA_SIZE / 2;
+        const TX_SIZE: usize = DATA_SIZE;
 
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
-            esp_hal::dma_buffers!(TX_SIZE, RX_SIZE);
+            esp_hal::dma_buffers!(RX_SIZE, TX_SIZE);
-        assert_eq!(tx_buffer.len(), TX_SIZE);
         assert_eq!(rx_buffer.len(), RX_SIZE);
-        assert_eq!(tx_descriptors.len(), compute_size(TX_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_buffer.len(), TX_SIZE);
         assert_eq!(rx_descriptors.len(), compute_size(RX_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_descriptors.len(), compute_size(TX_SIZE, CHUNK_SIZE));
     }
 
     #[test]
     fn test_dma_circular_buffers_same_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
             esp_hal::dma_circular_buffers!(DATA_SIZE);
-        assert_eq!(tx_buffer.len(), DATA_SIZE);
         assert_eq!(rx_buffer.len(), DATA_SIZE);
-        assert_eq!(tx_descriptors.len(), rx_descriptors.len());
+        assert_eq!(tx_buffer.len(), DATA_SIZE);
+        assert_eq!(rx_descriptors.len(), tx_descriptors.len());
         assert_eq!(
-            tx_descriptors.len(),
+            rx_descriptors.len(),
             compute_circular_size(DATA_SIZE, CHUNK_SIZE)
         );
         assert_eq!(
-            rx_descriptors.len(),
+            tx_descriptors.len(),
             compute_circular_size(DATA_SIZE, CHUNK_SIZE)
         );
     }
@@ -128,57 +128,57 @@ mod tests {
     #[test]
     fn test_dma_circular_buffers_different_size() {
         use esp_hal::dma::CHUNK_SIZE;
-        const TX_SIZE: usize = CHUNK_SIZE * 4;
         const RX_SIZE: usize = CHUNK_SIZE * 2;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        const TX_SIZE: usize = CHUNK_SIZE * 4;
-            esp_hal::dma_circular_buffers!(TX_SIZE, RX_SIZE);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
-        assert_eq!(tx_buffer.len(), TX_SIZE);
+            esp_hal::dma_circular_buffers!(RX_SIZE, TX_SIZE);
         assert_eq!(rx_buffer.len(), RX_SIZE);
-        assert_eq!(
+        assert_eq!(tx_buffer.len(), TX_SIZE);
-            tx_descriptors.len(),
-            compute_circular_size(TX_SIZE, CHUNK_SIZE)
-        );
         assert_eq!(
             rx_descriptors.len(),
             compute_circular_size(RX_SIZE, CHUNK_SIZE)
         );
+        assert_eq!(
+            tx_descriptors.len(),
+            compute_circular_size(TX_SIZE, CHUNK_SIZE)
+        );
     }
 
     #[test]
     fn test_dma_descriptors_chunk_size_same_size() {
         const CHUNK_SIZE: usize = 2048;
-        let (tx_descriptors, rx_descriptors) =
+        let (rx_descriptors, tx_descriptors) =
             esp_hal::dma_descriptors_chunk_size!(DATA_SIZE, CHUNK_SIZE);
-        assert_eq!(tx_descriptors.len(), rx_descriptors.len());
+        assert_eq!(rx_descriptors.len(), tx_descriptors.len());
-        assert_eq!(tx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
         assert_eq!(rx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_descriptors.len(), compute_size(DATA_SIZE, CHUNK_SIZE));
     }
 
     #[test]
     fn test_dma_descriptors_chunk_size_different_size() {
         const CHUNK_SIZE: usize = 2048;
-        const TX_SIZE: usize = DATA_SIZE;
         const RX_SIZE: usize = DATA_SIZE / 2;
-        let (tx_descriptors, rx_descriptors) =
+        const TX_SIZE: usize = DATA_SIZE;
-            esp_hal::dma_descriptors_chunk_size!(TX_SIZE, RX_SIZE, CHUNK_SIZE);
+        let (rx_descriptors, tx_descriptors) =
-        assert_eq!(tx_descriptors.len(), compute_size(TX_SIZE, CHUNK_SIZE));
+            esp_hal::dma_descriptors_chunk_size!(RX_SIZE, TX_SIZE, CHUNK_SIZE);
         assert_eq!(rx_descriptors.len(), compute_size(RX_SIZE, CHUNK_SIZE));
+        assert_eq!(tx_descriptors.len(), compute_size(TX_SIZE, CHUNK_SIZE));
     }
 
     #[test]
     fn test_dma_circular_buffers_chunk_size_same_size() {
         const CHUNK_SIZE: usize = 2048;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
             esp_hal::dma_circular_buffers_chunk_size!(DATA_SIZE, CHUNK_SIZE);
-        assert_eq!(tx_buffer.len(), DATA_SIZE);
         assert_eq!(rx_buffer.len(), DATA_SIZE);
-        assert_eq!(tx_descriptors.len(), rx_descriptors.len());
+        assert_eq!(tx_buffer.len(), DATA_SIZE);
+        assert_eq!(rx_descriptors.len(), tx_descriptors.len());
         assert_eq!(
-            tx_descriptors.len(),
+            rx_descriptors.len(),
             compute_circular_size(DATA_SIZE, CHUNK_SIZE)
         );
         assert_eq!(
-            rx_descriptors.len(),
+            tx_descriptors.len(),
             compute_circular_size(DATA_SIZE, CHUNK_SIZE)
         );
     }
@@ -186,19 +186,19 @@ mod tests {
     #[test]
     fn test_dma_circular_buffers_chunk_size_different_size() {
         const CHUNK_SIZE: usize = 2048;
-        const TX_SIZE: usize = DATA_SIZE;
         const RX_SIZE: usize = DATA_SIZE / 2;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        const TX_SIZE: usize = DATA_SIZE;
-            esp_hal::dma_circular_buffers_chunk_size!(TX_SIZE, RX_SIZE, CHUNK_SIZE);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
-        assert_eq!(tx_buffer.len(), TX_SIZE);
+            esp_hal::dma_circular_buffers_chunk_size!(RX_SIZE, TX_SIZE, CHUNK_SIZE);
         assert_eq!(rx_buffer.len(), RX_SIZE);
-        assert_eq!(
+        assert_eq!(tx_buffer.len(), TX_SIZE);
-            tx_descriptors.len(),
-            compute_circular_size(TX_SIZE, CHUNK_SIZE)
-        );
         assert_eq!(
             rx_descriptors.len(),
             compute_circular_size(RX_SIZE, CHUNK_SIZE)
         );
+        assert_eq!(
+            tx_descriptors.len(),
+            compute_circular_size(TX_SIZE, CHUNK_SIZE)
+        );
     }
 }

hil-test/tests/dma_mem2mem.rs

@@ -59,20 +59,20 @@ mod tests {
 
     #[test]
     fn test_internal_mem2mem(ctx: Context) {
-        let (tx_buffer, tx_descriptors, mut rx_buffer, rx_descriptors) = dma_buffers!(DATA_SIZE);
+        let (mut rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE);
 
         let mut mem2mem = Mem2Mem::new(
             ctx.channel,
             ctx.dma_peripheral,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         )
         .unwrap();
 
         for i in 0..core::mem::size_of_val(tx_buffer) {
             tx_buffer[i] = (i % 256) as u8;
         }
-        let dma_wait = mem2mem.start_transfer(&tx_buffer, &mut rx_buffer).unwrap();
+        let dma_wait = mem2mem.start_transfer(&mut rx_buffer, &tx_buffer).unwrap();
         dma_wait.wait().unwrap();
         for i in 0..core::mem::size_of_val(tx_buffer) {
             assert_eq!(rx_buffer[i], tx_buffer[i]);
@@ -89,8 +89,8 @@ mod tests {
         let mut mem2mem = Mem2Mem::new_with_chunk_size(
             ctx.channel,
             ctx.dma_peripheral,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
             CHUNK_SIZE,
         )
         .unwrap();
@@ -98,7 +98,7 @@ mod tests {
         for i in 0..core::mem::size_of_val(tx_buffer) {
             tx_buffer[i] = (i % 256) as u8;
         }
-        let dma_wait = mem2mem.start_transfer(&tx_buffer, &mut rx_buffer).unwrap();
+        let dma_wait = mem2mem.start_transfer(&mut rx_buffer, &tx_buffer).unwrap();
         dma_wait.wait().unwrap();
         for i in 0..core::mem::size_of_val(tx_buffer) {
             assert_eq!(rx_buffer[i], tx_buffer[i]);
@@ -109,12 +109,12 @@ mod tests {
     fn test_mem2mem_errors_zero_tx(ctx: Context) {
         use esp_hal::dma::CHUNK_SIZE;
 
-        let (tx_descriptors, rx_descriptors) = dma_descriptors!(0, 1024);
+        let (rx_descriptors, tx_descriptors) = dma_descriptors!(1024, 0);
         match Mem2Mem::new_with_chunk_size(
             ctx.channel,
             ctx.dma_peripheral,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
             CHUNK_SIZE,
         ) {
             Err(DmaError::OutOfDescriptors) => (),
@@ -126,12 +126,12 @@ mod tests {
     fn test_mem2mem_errors_zero_rx(ctx: Context) {
         use esp_hal::dma::CHUNK_SIZE;
 
-        let (tx_descriptors, rx_descriptors) = dma_descriptors!(1024, 0);
+        let (rx_descriptors, tx_descriptors) = dma_descriptors!(0, 1024);
         match Mem2Mem::new_with_chunk_size(
             ctx.channel,
             ctx.dma_peripheral,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
             CHUNK_SIZE,
         ) {
             Err(DmaError::OutOfDescriptors) => (),
@@ -141,12 +141,12 @@ mod tests {
 
     #[test]
     fn test_mem2mem_errors_chunk_size_too_small(ctx: Context) {
-        let (tx_descriptors, rx_descriptors) = dma_descriptors!(1024, 1024);
+        let (rx_descriptors, tx_descriptors) = dma_descriptors!(1024, 1024);
         match Mem2Mem::new_with_chunk_size(
             ctx.channel,
             ctx.dma_peripheral,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
             0,
         ) {
             Err(DmaError::InvalidChunkSize) => (),
@@ -156,12 +156,12 @@ mod tests {
 
     #[test]
     fn test_mem2mem_errors_chunk_size_too_big(ctx: Context) {
-        let (tx_descriptors, rx_descriptors) = dma_descriptors!(1024, 1024);
+        let (rx_descriptors, tx_descriptors) = dma_descriptors!(1024, 1024);
         match Mem2Mem::new_with_chunk_size(
             ctx.channel,
             ctx.dma_peripheral,
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
             4093,
         ) {
             Err(DmaError::InvalidChunkSize) => (),

hil-test/tests/embassy_interrupt_spi_dma.rs

@@ -49,11 +49,11 @@ macro_rules! mk_static {
 async fn interrupt_driven_task(spi: SpiDma<'static, SPI3, DmaChannel1, FullDuplexMode, Async>) {
     let mut ticker = Ticker::every(Duration::from_millis(1));
 
-    let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(128);
+    let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(128);
-    let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
     let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+    let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
-    let mut spi = spi.with_buffers(dma_tx_buf, dma_rx_buf);
+    let mut spi = spi.with_buffers(dma_rx_buf, dma_tx_buf);
 
     loop {
         let mut buffer: [u8; 8] = [0; 8];
@@ -92,13 +92,13 @@ mod test {
             }
         }
 
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(1024);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(1024);
-        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
             .with_dma(dma_channel1.configure_for_async(false, DmaPriority::Priority0))
-            .with_buffers(dma_tx_buf, dma_rx_buf);
+            .with_buffers(dma_rx_buf, dma_tx_buf);
 
         let spi2 = Spi::new(peripherals.SPI3, 100.kHz(), SpiMode::Mode0)
             .with_dma(dma_channel2.configure_for_async(false, DmaPriority::Priority0));

hil-test/tests/i2s.rs

@@ -63,7 +63,7 @@ mod tests {
         let dma = Dma::new(peripherals.DMA);
         let dma_channel = dma.channel0;
 
-        let (tx_buffer, tx_descriptors, mut rx_buffer, rx_descriptors) = dma_buffers!(16000, 16000);
+        let (mut rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(16000, 16000);
 
         let i2s = I2s::new(
             peripherals.I2S0,
@@ -71,8 +71,8 @@ mod tests {
             DataFormat::Data16Channel16,
             16000.Hz(),
             dma_channel.configure(false, DmaPriority::Priority0),
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         );
 
         let (dout, din) = hil_test::common_test_pins!(io);

hil-test/tests/i2s_async.rs

@@ -111,7 +111,7 @@ mod tests {
             }
         }
 
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) =
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) =
             esp_hal::dma_circular_buffers!(BUFFER_SIZE, BUFFER_SIZE);
 
         let i2s = I2s::new(
@@ -120,8 +120,8 @@ mod tests {
             DataFormat::Data16Channel16,
             16000.Hz(),
             dma_channel.configure_for_async(false, DmaPriority::Priority0),
-            tx_descriptors,
             rx_descriptors,
+            tx_descriptors,
         );
 
         let (dout, din) = hil_test::common_test_pins!(io);

hil-test/tests/lcd_cam_i8080.rs

@@ -36,7 +36,7 @@ mod tests {
         let peripherals = esp_hal::init(esp_hal::Config::default());
         let dma = Dma::new(peripherals.DMA);
         let lcd_cam = LcdCam::new(peripherals.LCD_CAM);
-        let (tx_buffer, tx_descriptors, _, _) = dma_buffers!(DATA_SIZE, 0);
+        let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE, 0);
 
         Context {
             lcd_cam,

hil-test/tests/lcd_cam_i8080_async.rs

@@ -38,7 +38,7 @@ mod tests {
 
         let dma = Dma::new(peripherals.DMA);
         let lcd_cam = LcdCam::new_async(peripherals.LCD_CAM);
-        let (tx_buffer, tx_descriptors, _, _) = dma_buffers!(DATA_SIZE, 0);
+        let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE, 0);
 
         Context {
             lcd_cam,

hil-test/tests/qspi_read.rs

@@ -52,7 +52,7 @@ fn execute(
 ) {
     const DMA_BUFFER_SIZE: usize = 4;
 
-    let (buffer, descriptors, _, _) = dma_buffers!(DMA_BUFFER_SIZE, 0);
+    let (_, _, buffer, descriptors) = dma_buffers!(0, DMA_BUFFER_SIZE);
     let mut dma_rx_buf = DmaRxBuf::new(descriptors, buffer).unwrap();
 
     miso_mirror.set_low();

hil-test/tests/qspi_write.rs

@@ -60,7 +60,7 @@ fn execute(
 ) {
     const DMA_BUFFER_SIZE: usize = 4;
 
-    let (buffer, descriptors, _, _) = dma_buffers!(DMA_BUFFER_SIZE, 0);
+    let (_, _, buffer, descriptors) = dma_buffers!(0, DMA_BUFFER_SIZE);
     let mut dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
 
     dma_tx_buf.fill(&[write; DMA_BUFFER_SIZE]);

hil-test/tests/qspi_write_read.rs

@@ -54,10 +54,10 @@ fn execute(
 ) {
     const DMA_BUFFER_SIZE: usize = 4;
 
-    let (buffer, descriptors, rx_buffer, rx_descriptors) =
+    let (rx_buffer, rx_descriptors, buffer, descriptors) =
         dma_buffers!(DMA_BUFFER_SIZE, DMA_BUFFER_SIZE);
-    let mut dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
     let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+    let mut dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
 
     dma_tx_buf.fill(&[0xff; DMA_BUFFER_SIZE]);
 

hil-test/tests/rmt.rs

@@ -41,7 +41,7 @@ mod tests {
 
         let rmt = Rmt::new(peripherals.RMT, freq).unwrap();
 
-        let (tx, rx) = hil_test::common_test_pins!(io);
+        let (rx, tx) = hil_test::common_test_pins!(io);
 
         let tx_config = TxChannelConfig {
             clk_divider: 255,

hil-test/tests/spi_full_duplex_dma.rs

@@ -79,45 +79,46 @@ mod tests {
     #[test]
     #[timeout(3)]
     fn test_symmetric_dma_transfer(ctx: Context) {
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(4);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
-        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
 
         let transfer = ctx
             .spi
-            .dma_transfer(dma_tx_buf, dma_rx_buf)
+            .dma_transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
-        let (_, (dma_tx_buf, dma_rx_buf)) = transfer.wait();
+        let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
         assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice());
     }
 
     #[test]
     #[timeout(3)]
+    #[cfg(not(feature = "esp32s2"))]
     fn test_asymmetric_dma_transfer(ctx: Context) {
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(4, 2);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(2, 4);
-        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
 
         let transfer = ctx
             .spi
-            .dma_transfer(dma_tx_buf, dma_rx_buf)
+            .dma_transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
-        let (_, (dma_tx_buf, dma_rx_buf)) = transfer.wait();
+        let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
         assert_eq!(dma_tx_buf.as_slice()[0..1], dma_rx_buf.as_slice()[0..1]);
     }
 
     #[test]
     #[timeout(3)]
     fn test_symmetric_dma_transfer_huge_buffer(ctx: Context) {
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(4096);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4096);
-        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         for (i, d) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
             *d = i as _;
@@ -125,21 +126,21 @@ mod tests {
 
         let transfer = ctx
             .spi
-            .dma_transfer(dma_tx_buf, dma_rx_buf)
+            .dma_transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
-        let (_, (dma_tx_buf, dma_rx_buf)) = transfer.wait();
+        let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
         assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice());
     }
 
     #[test]
     #[timeout(3)]
     fn test_dma_bus_symmetric_transfer(ctx: Context) {
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(4);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
-        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
-        let mut spi = ctx.spi.with_buffers(dma_tx_buf, dma_rx_buf);
+        let mut spi = ctx.spi.with_buffers(dma_rx_buf, dma_tx_buf);
 
         let tx_buf = [0xde, 0xad, 0xbe, 0xef];
         let mut rx_buf = [0; 4];
@@ -152,11 +153,11 @@ mod tests {
     #[test]
     #[timeout(3)]
     fn test_dma_bus_asymmetric_transfer(ctx: Context) {
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(4);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
-        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
-        let mut spi = ctx.spi.with_buffers(dma_tx_buf, dma_rx_buf);
+        let mut spi = ctx.spi.with_buffers(dma_rx_buf, dma_tx_buf);
 
         let tx_buf = [0xde, 0xad, 0xbe, 0xef];
         let mut rx_buf = [0; 4];
@@ -171,11 +172,11 @@ mod tests {
     fn test_dma_bus_symmetric_transfer_huge_buffer(ctx: Context) {
         const DMA_BUFFER_SIZE: usize = 4096;
 
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(40);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(40);
-        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
-        let mut spi = ctx.spi.with_buffers(dma_tx_buf, dma_rx_buf);
+        let mut spi = ctx.spi.with_buffers(dma_rx_buf, dma_tx_buf);
 
         let tx_buf = core::array::from_fn(|i| i as _);
         let mut rx_buf = [0; DMA_BUFFER_SIZE];

hil-test/tests/spi_full_duplex_dma_async.rs

@@ -93,16 +93,16 @@ mod tests {
             }
         }
 
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
-        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
             .with_sck(sclk)
             .with_mosi(mosi)
             .with_miso(miso)
             .with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0))
-            .with_buffers(dma_tx_buf, dma_rx_buf);
+            .with_buffers(dma_rx_buf, dma_tx_buf);
 
         Context {
             spi,

hil-test/tests/spi_full_duplex_dma_pcnt.rs

@@ -105,9 +105,9 @@ mod tests {
     #[timeout(3)]
     fn test_dma_read_dma_write_pcnt(ctx: Context) {
         const DMA_BUFFER_SIZE: usize = 5;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
-        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let unit = ctx.pcnt_unit;
         let mut spi = ctx.spi;
@@ -140,9 +140,9 @@ mod tests {
     #[timeout(3)]
     fn test_dma_read_dma_transfer_pcnt(ctx: Context) {
         const DMA_BUFFER_SIZE: usize = 5;
-        let (tx_buffer, tx_descriptors, rx_buffer, rx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
+        let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
-        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
         let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
+        let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
 
         let unit = ctx.pcnt_unit;
         let mut spi = ctx.spi;
@@ -166,10 +166,10 @@ mod tests {
             assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
 
             let transfer = spi
-                .dma_transfer(dma_tx_buf, dma_rx_buf)
+                .dma_transfer(dma_rx_buf, dma_tx_buf)
                 .map_err(|e| e.0)
                 .unwrap();
-            (spi, (dma_tx_buf, dma_rx_buf)) = transfer.wait();
+            (spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
             assert_eq!(unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
         }
     }

hil-test/tests/spi_half_duplex_read.rs

@@ -131,11 +131,12 @@ mod tests {
     fn test_spidmabus_reads_correctly_from_gpio_pin(mut ctx: Context) {
         const DMA_BUFFER_SIZE: usize = 4;
 
+        // WAS THIS AN ERROR?
         let (buffer, descriptors, tx, txd) = dma_buffers!(DMA_BUFFER_SIZE, 1);
         let dma_rx_buf = DmaRxBuf::new(descriptors, buffer).unwrap();
         let dma_tx_buf = DmaTxBuf::new(txd, tx).unwrap();
 
-        let mut spi = ctx.spi.with_buffers(dma_tx_buf, dma_rx_buf);
+        let mut spi = ctx.spi.with_buffers(dma_rx_buf, dma_tx_buf);
 
         // SPI should read '0's from the MISO pin
         ctx.miso_mirror.set_low();

hil-test/tests/spi_half_duplex_write.rs

@@ -99,7 +99,7 @@ mod tests {
     fn test_spi_writes_are_correctly_by_pcnt(ctx: Context) {
         const DMA_BUFFER_SIZE: usize = 4;
 
-        let (buffer, descriptors, _, _) = dma_buffers!(DMA_BUFFER_SIZE, 0);
+        let (_, _, buffer, descriptors) = dma_buffers!(0, DMA_BUFFER_SIZE);
         let mut dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
 
         let unit = ctx.pcnt_unit;
@@ -149,12 +149,12 @@ mod tests {
     fn test_spidmabus_writes_are_correctly_by_pcnt(ctx: Context) {
         const DMA_BUFFER_SIZE: usize = 4;
 
-        let (buffer, descriptors, rx, rxd) = dma_buffers!(DMA_BUFFER_SIZE, 1);
+        let (rx, rxd, buffer, descriptors) = dma_buffers!(1, DMA_BUFFER_SIZE);
-        let dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
         let dma_rx_buf = DmaRxBuf::new(rxd, rx).unwrap();
+        let dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
 
         let unit = ctx.pcnt_unit;
-        let mut spi = ctx.spi.with_buffers(dma_tx_buf, dma_rx_buf);
+        let mut spi = ctx.spi.with_buffers(dma_rx_buf, dma_tx_buf);
 
         unit.channel0.set_edge_signal(PcntSource::from_pin(
             ctx.mosi_mirror,

hil-test/tests/twai.rs

@@ -43,8 +43,8 @@ mod tests {
 
         let mut config = twai::TwaiConfiguration::new(
             peripherals.TWAI0,
-            can_tx_pin,
             can_rx_pin,
+            can_tx_pin,
             twai::BaudRate::B1000K,
             TwaiMode::SelfTest,
         );

hil-test/tests/uart.rs

@@ -39,7 +39,7 @@ mod tests {
 
         let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-        let (tx, rx) = hil_test::common_test_pins!(io);
+        let (rx, tx) = hil_test::common_test_pins!(io);
 
         let uart = Uart::new(peripherals.UART1, tx, rx).unwrap();
 

hil-test/tests/uart_async.rs

@@ -32,9 +32,9 @@ mod tests {
 
         let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-        let (tx, rx) = hil_test::common_test_pins!(io);
+        let (rx, tx) = hil_test::common_test_pins!(io);
 
-        let uart = Uart::new_async(peripherals.UART0, tx, rx).unwrap();
+        let uart = Uart::new_async(peripherals.UART0, rx, tx).unwrap();
 
         Context { uart }
     }

hil-test/tests/uart_tx_rx.rs

@@ -22,8 +22,8 @@ use hil_test as _;
 use nb::block;
 
 struct Context {
-    tx: UartTx<'static, UART0, Blocking>,
     rx: UartRx<'static, UART1, Blocking>,
+    tx: UartTx<'static, UART0, Blocking>,
 }
 
 #[cfg(test)]
@@ -39,12 +39,12 @@ mod tests {
 
         let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-        let (tx, rx) = hil_test::common_test_pins!(io);
+        let (rx, tx) = hil_test::common_test_pins!(io);
 
         let tx = UartTx::new(peripherals.UART0, tx).unwrap();
         let rx = UartRx::new(peripherals.UART1, rx).unwrap();
 
-        Context { tx, rx }
+        Context { rx, tx }
     }
 
     #[test]

hil-test/tests/uart_tx_rx_async.rs

@@ -21,8 +21,8 @@ use esp_hal::{
 use hil_test as _;
 
 struct Context {
-    tx: UartTx<'static, UART0, Async>,
     rx: UartRx<'static, UART1, Async>,
+    tx: UartTx<'static, UART0, Async>,
 }
 
 #[cfg(test)]
@@ -38,12 +38,12 @@ mod tests {
 
         let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
 
-        let (tx, rx) = hil_test::common_test_pins!(io);
+        let (rx, tx) = hil_test::common_test_pins!(io);
 
         let tx = UartTx::new_async(peripherals.UART0, tx).unwrap();
         let rx = UartRx::new_async(peripherals.UART1, rx).unwrap();
 
-        Context { tx, rx }
+        Context { rx, tx }
     }
 
     #[test]