b5f0246129
* feat: Update rx-tx order in i2s * feat: Update rx-tx order in dma macros * feat: Update rx-tx order in spi * feat: Update rx-tx order in aes * feat: Update rx-tx order in mem2mem * feat: Update rx-tx order in twai and split methods * feat: Update rx-tx order in twai * feat: Update rx-tx order in twai and uart docs * docs: Add sentence about order * docs: Update changelog * feat: Update rx-tx order in embassy_interrupt_spi_dma tests * style: Rustfmt * docs: Migrating guide * fix: Typo Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Diff Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Tests rx-tx order * fix: Update new_with_default_pins order * feat: Update rx/tx order in hil_test::common_test_pins! * feat: Update dma_extmem2mem example * fix: Revert deleted input arg * style: rustfmt * feat: Disable test_asymmetric_dma_transfer for S2 --------- Co-authored-by: Dániel Buga <bugadani@gmail.com>
111 lines
2.5 KiB
Rust
111 lines
2.5 KiB
Rust
//! lcd_cam i8080 tests
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//% CHIPS: esp32s3
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#![no_std]
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#![no_main]
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use esp_hal::{
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dma::{Dma, DmaDescriptor, DmaPriority},
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dma_buffers,
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gpio::DummyPin,
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lcd_cam::{
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lcd::i8080::{Command, Config, TxEightBits, I8080},
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LcdCam,
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},
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prelude::*,
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};
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use hil_test as _;
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const DATA_SIZE: usize = 1024 * 10;
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struct Context<'d> {
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lcd_cam: LcdCam<'d, esp_hal::Blocking>,
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dma: Dma<'d>,
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tx_buffer: &'static [u8],
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tx_descriptors: &'static mut [DmaDescriptor],
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context<'static> {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let dma = Dma::new(peripherals.DMA);
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let lcd_cam = LcdCam::new(peripherals.LCD_CAM);
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let (_, _, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE, 0);
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Context {
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lcd_cam,
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dma,
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tx_buffer,
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tx_descriptors,
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}
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}
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#[test]
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fn test_i8080_8bit(ctx: Context<'static>) {
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let channel = ctx.dma.channel0.configure(false, DmaPriority::Priority0);
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let pins = TxEightBits::new(
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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);
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let mut i8080 = I8080::new(
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ctx.lcd_cam.lcd,
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channel.tx,
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ctx.tx_descriptors,
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pins,
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20.MHz(),
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Config::default(),
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);
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let xfer = i8080
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.send_dma(Command::<u8>::None, 0, &ctx.tx_buffer)
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.unwrap();
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xfer.wait().unwrap();
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}
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#[test]
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fn test_i8080_8bit_async_channel(ctx: Context<'static>) {
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let channel = ctx
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.dma
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.channel0
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.configure_for_async(false, DmaPriority::Priority0);
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let pins = TxEightBits::new(
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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DummyPin::new(),
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);
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let mut i8080 = I8080::new(
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ctx.lcd_cam.lcd,
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channel.tx,
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ctx.tx_descriptors,
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pins,
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20.MHz(),
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Config::default(),
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);
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let xfer = i8080
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.send_dma(Command::<u8>::None, 0, &ctx.tx_buffer)
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.unwrap();
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xfer.wait().unwrap();
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}
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}
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