esp-hal/hil-test/tests/uart.rs
Sergio Gasquez Arcos b5f0246129
Reordered RX-TX pairs to be consistent (#2074)
* feat: Update rx-tx order in i2s

* feat: Update rx-tx order in dma macros

* feat: Update rx-tx order in spi

* feat: Update rx-tx order in aes

* feat: Update rx-tx order in mem2mem

* feat: Update rx-tx order in twai and split methods

* feat: Update rx-tx order in twai

* feat: Update rx-tx order in twai and uart docs

* docs: Add sentence about order

* docs: Update changelog

* feat: Update rx-tx order in embassy_interrupt_spi_dma tests

* style: Rustfmt

* docs: Migrating guide

* fix: Typo

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Diff

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Tests rx-tx order

* fix: Update new_with_default_pins order

* feat: Update rx/tx order in hil_test::common_test_pins!

* feat: Update dma_extmem2mem example

* fix: Revert deleted input arg

* style: rustfmt

* feat: Disable test_asymmetric_dma_transfer for S2

---------

Co-authored-by: Dániel Buga <bugadani@gmail.com>
2024-09-06 09:56:10 +00:00

134 lines
3.7 KiB
Rust

//! UART Test
//!
//! Folowing pins are used:
//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
//!
//! Connect TX and RX pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
#![no_std]
#![no_main]
use embedded_hal_02::serial::{Read, Write};
use esp_hal::{
gpio::Io,
peripherals::UART1,
prelude::*,
uart::{ClockSource, Uart},
Blocking,
};
use hil_test as _;
use nb::block;
struct Context {
uart: Uart<'static, UART1, Blocking>,
}
#[cfg(test)]
#[embedded_test::tests]
mod tests {
use defmt::assert_eq;
use super::*;
#[init]
fn init() -> Context {
let peripherals = esp_hal::init(esp_hal::Config::default());
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let (rx, tx) = hil_test::common_test_pins!(io);
let uart = Uart::new(peripherals.UART1, tx, rx).unwrap();
Context { uart }
}
#[test]
#[timeout(3)]
fn test_send_receive(mut ctx: Context) {
ctx.uart.write(0x42).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(0x42));
}
#[test]
#[timeout(3)]
fn test_send_receive_buffer(mut ctx: Context) {
const BUF_SIZE: usize = 128; // UART_FIFO_SIZE
let data = [13; BUF_SIZE];
let written = ctx.uart.write_bytes(&data).unwrap();
assert_eq!(written, BUF_SIZE);
let mut buffer = [0; BUF_SIZE];
let mut i = 0;
while i < BUF_SIZE {
match ctx.uart.read() {
Ok(byte) => {
buffer[i] = byte;
i += 1;
}
Err(nb::Error::WouldBlock) => continue,
Err(nb::Error::Other(_)) => panic!(),
}
}
assert_eq!(data, buffer);
}
#[test]
#[timeout(3)]
fn test_send_receive_different_baud_rates_and_clock_sources(mut ctx: Context) {
// The default baud rate for the UART is 115,200, so we will try to
// send/receive with some other common baud rates to ensure this is
// working as expected. We will also using different clock sources
// while we're at it.
#[cfg(not(feature = "esp32s2"))]
{
#[cfg(not(any(feature = "esp32", feature = "esp32c3", feature = "esp32c2")))]
{
// 9600 baud, RC FAST clock source:
ctx.uart.change_baud(9600, ClockSource::RcFast);
ctx.uart.write(7).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(7));
}
// 19,200 baud, XTAL clock source:
#[cfg(not(feature = "esp32"))]
{
ctx.uart.change_baud(19_200, ClockSource::Xtal);
ctx.uart.write(55).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(55));
}
// 921,600 baud, APB clock source:
ctx.uart.change_baud(921_600, ClockSource::Apb);
ctx.uart.write(253).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(253));
}
#[cfg(feature = "esp32s2")]
{
// 9600 baud, REF TICK clock source:
ctx.uart.change_baud(9600, ClockSource::RefTick);
ctx.uart.write(7).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(7));
// 921,600 baud, APB clock source:
ctx.uart.change_baud(921_600, ClockSource::Apb);
ctx.uart.write(253).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(253));
}
}
}