* feat: Update rx-tx order in i2s * feat: Update rx-tx order in dma macros * feat: Update rx-tx order in spi * feat: Update rx-tx order in aes * feat: Update rx-tx order in mem2mem * feat: Update rx-tx order in twai and split methods * feat: Update rx-tx order in twai * feat: Update rx-tx order in twai and uart docs * docs: Add sentence about order * docs: Update changelog * feat: Update rx-tx order in embassy_interrupt_spi_dma tests * style: Rustfmt * docs: Migrating guide * fix: Typo Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Diff Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Tests rx-tx order * fix: Update new_with_default_pins order * feat: Update rx/tx order in hil_test::common_test_pins! * feat: Update dma_extmem2mem example * fix: Revert deleted input arg * style: rustfmt * feat: Disable test_asymmetric_dma_transfer for S2 --------- Co-authored-by: Dániel Buga <bugadani@gmail.com>
172 lines
4.7 KiB
Rust
172 lines
4.7 KiB
Rust
//! DMA Mem2Mem Tests
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//% CHIPS: esp32s3 esp32c2 esp32c3 esp32c6 esp32h2
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#![no_std]
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#![no_main]
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use esp_hal::{
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dma::{Channel, Dma, DmaChannel0, DmaError, DmaPriority, Mem2Mem},
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dma_buffers,
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dma_buffers_chunk_size,
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dma_descriptors,
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Blocking,
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};
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use hil_test as _;
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const DATA_SIZE: usize = 1024 * 10;
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3"))] {
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type DmaPeripheralType = esp_hal::peripherals::SPI2;
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} else {
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type DmaPeripheralType = esp_hal::peripherals::MEM2MEM1;
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}
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}
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struct Context {
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channel: Channel<'static, DmaChannel0, Blocking>,
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dma_peripheral: DmaPeripheralType,
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let dma = Dma::new(peripherals.DMA);
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let channel = dma.channel0.configure(false, DmaPriority::Priority0);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32c2", feature = "esp32c3", feature = "esp32s3"))] {
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let dma_peripheral = peripherals.SPI2;
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} else {
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let dma_peripheral = peripherals.MEM2MEM1;
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}
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}
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Context {
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channel,
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dma_peripheral,
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}
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}
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#[test]
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fn test_internal_mem2mem(ctx: Context) {
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let (mut rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DATA_SIZE);
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let mut mem2mem = Mem2Mem::new(
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ctx.channel,
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ctx.dma_peripheral,
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rx_descriptors,
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tx_descriptors,
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)
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.unwrap();
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for i in 0..core::mem::size_of_val(tx_buffer) {
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tx_buffer[i] = (i % 256) as u8;
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}
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let dma_wait = mem2mem.start_transfer(&mut rx_buffer, &tx_buffer).unwrap();
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dma_wait.wait().unwrap();
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for i in 0..core::mem::size_of_val(tx_buffer) {
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assert_eq!(rx_buffer[i], tx_buffer[i]);
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}
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}
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#[test]
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fn test_internal_mem2mem_chunk_size(ctx: Context) {
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const CHUNK_SIZE: usize = 2048;
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let (tx_buffer, tx_descriptors, mut rx_buffer, rx_descriptors) =
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dma_buffers_chunk_size!(DATA_SIZE, CHUNK_SIZE);
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let mut mem2mem = Mem2Mem::new_with_chunk_size(
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ctx.channel,
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ctx.dma_peripheral,
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rx_descriptors,
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tx_descriptors,
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CHUNK_SIZE,
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)
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.unwrap();
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for i in 0..core::mem::size_of_val(tx_buffer) {
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tx_buffer[i] = (i % 256) as u8;
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}
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let dma_wait = mem2mem.start_transfer(&mut rx_buffer, &tx_buffer).unwrap();
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dma_wait.wait().unwrap();
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for i in 0..core::mem::size_of_val(tx_buffer) {
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assert_eq!(rx_buffer[i], tx_buffer[i]);
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}
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}
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#[test]
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fn test_mem2mem_errors_zero_tx(ctx: Context) {
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use esp_hal::dma::CHUNK_SIZE;
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let (rx_descriptors, tx_descriptors) = dma_descriptors!(1024, 0);
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match Mem2Mem::new_with_chunk_size(
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ctx.channel,
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ctx.dma_peripheral,
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rx_descriptors,
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tx_descriptors,
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CHUNK_SIZE,
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) {
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Err(DmaError::OutOfDescriptors) => (),
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_ => panic!("Expected OutOfDescriptors"),
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}
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}
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#[test]
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fn test_mem2mem_errors_zero_rx(ctx: Context) {
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use esp_hal::dma::CHUNK_SIZE;
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let (rx_descriptors, tx_descriptors) = dma_descriptors!(0, 1024);
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match Mem2Mem::new_with_chunk_size(
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ctx.channel,
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ctx.dma_peripheral,
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rx_descriptors,
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tx_descriptors,
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CHUNK_SIZE,
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) {
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Err(DmaError::OutOfDescriptors) => (),
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_ => panic!("Expected OutOfDescriptors"),
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}
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}
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#[test]
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fn test_mem2mem_errors_chunk_size_too_small(ctx: Context) {
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let (rx_descriptors, tx_descriptors) = dma_descriptors!(1024, 1024);
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match Mem2Mem::new_with_chunk_size(
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ctx.channel,
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ctx.dma_peripheral,
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rx_descriptors,
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tx_descriptors,
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0,
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) {
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Err(DmaError::InvalidChunkSize) => (),
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_ => panic!("Expected InvalidChunkSize"),
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}
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}
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#[test]
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fn test_mem2mem_errors_chunk_size_too_big(ctx: Context) {
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let (rx_descriptors, tx_descriptors) = dma_descriptors!(1024, 1024);
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match Mem2Mem::new_with_chunk_size(
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ctx.channel,
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ctx.dma_peripheral,
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rx_descriptors,
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tx_descriptors,
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4093,
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) {
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Err(DmaError::InvalidChunkSize) => (),
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_ => panic!("Expected InvalidChunkSize"),
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}
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}
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}
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