* feat: Update rx-tx order in i2s * feat: Update rx-tx order in dma macros * feat: Update rx-tx order in spi * feat: Update rx-tx order in aes * feat: Update rx-tx order in mem2mem * feat: Update rx-tx order in twai and split methods * feat: Update rx-tx order in twai * feat: Update rx-tx order in twai and uart docs * docs: Add sentence about order * docs: Update changelog * feat: Update rx-tx order in embassy_interrupt_spi_dma tests * style: Rustfmt * docs: Migrating guide * fix: Typo Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Diff Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Tests rx-tx order * fix: Update new_with_default_pins order * feat: Update rx/tx order in hil_test::common_test_pins! * feat: Update dma_extmem2mem example * fix: Revert deleted input arg * style: rustfmt * feat: Disable test_asymmetric_dma_transfer for S2 --------- Co-authored-by: Dániel Buga <bugadani@gmail.com>
249 lines
6.6 KiB
Rust
249 lines
6.6 KiB
Rust
//! QSPI Write Test
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//!
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//! This uses PCNT to count the edges of the MOSI signal
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//!
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//! Following pins are used:
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//! MOSI GPIO2 / GPIO9 (esp32s2 and esp32s3)
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//!
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//! PCNT GPIO3 / GPIO10 (esp32s2 and esp32s3)
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//!
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//! Connect MOSI and PCNT pins.
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//% CHIPS: esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use esp_hal::{
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dma::{Channel, Dma, DmaPriority, DmaTxBuf},
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dma_buffers,
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gpio::{AnyPin, Io, Pull},
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pcnt::{
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channel::{EdgeMode, PcntInputConfig, PcntSource},
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unit::Unit,
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Pcnt,
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},
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prelude::*,
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spi::{
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master::{Address, Command, Spi, SpiDma},
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HalfDuplexMode,
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SpiDataMode,
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SpiMode,
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},
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Blocking,
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};
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(any(
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feature = "esp32",
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feature = "esp32s2",
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))] {
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use esp_hal::dma::Spi2DmaChannel as DmaChannel0;
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} else {
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use esp_hal::dma::DmaChannel0;
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}
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}
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struct Context {
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spi: esp_hal::peripherals::SPI2,
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pcnt: esp_hal::peripherals::PCNT,
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dma_channel: Channel<'static, DmaChannel0, Blocking>,
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mosi: AnyPin<'static>,
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mosi_mirror: AnyPin<'static>,
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}
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fn execute(
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unit: Unit<'static, 0>,
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mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>,
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write: u8,
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) {
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const DMA_BUFFER_SIZE: usize = 4;
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let (_, _, buffer, descriptors) = dma_buffers!(0, DMA_BUFFER_SIZE);
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let mut dma_tx_buf = DmaTxBuf::new(descriptors, buffer).unwrap();
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dma_tx_buf.fill(&[write; DMA_BUFFER_SIZE]);
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let transfer = spi
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.write(
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SpiDataMode::Quad,
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Command::Command8(write as u16, SpiDataMode::Quad),
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Address::Address24(
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write as u32 | (write as u32) << 8 | (write as u32) << 16,
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SpiDataMode::Quad,
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),
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0,
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dma_tx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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(spi, dma_tx_buf) = transfer.wait();
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assert_eq!(unit.get_value(), 8);
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dma_tx_buf.set_length(0);
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let transfer = spi
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.write(
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SpiDataMode::Quad,
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Command::Command8(write as u16, SpiDataMode::Quad),
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Address::Address24(
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write as u32 | (write as u32) << 8 | (write as u32) << 16,
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SpiDataMode::Quad,
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),
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0,
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dma_tx_buf,
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)
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.map_err(|e| e.0)
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.unwrap();
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_ = transfer.wait();
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assert_eq!(unit.get_value(), 8 + 4);
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let (mosi, mosi_mirror) = hil_test::common_test_pins!(io);
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let mosi = AnyPin::new(mosi);
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let mosi_mirror = AnyPin::new(mosi_mirror);
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let dma = Dma::new(peripherals.DMA);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
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let dma_channel = dma.spi2channel;
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} else {
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let dma_channel = dma.channel0;
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}
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}
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let dma_channel = dma_channel.configure(false, DmaPriority::Priority0);
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Context {
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spi: peripherals.SPI2,
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pcnt: peripherals.PCNT,
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dma_channel,
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mosi,
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mosi_mirror,
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}
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}
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#[test]
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#[timeout(3)]
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fn test_spi_writes_correctly_to_pin_0(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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Some(ctx.mosi),
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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let pcnt = Pcnt::new(ctx.pcnt);
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let unit = pcnt.unit0;
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unit.channel0.set_edge_signal(PcntSource::from_pin(
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ctx.mosi_mirror,
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PcntInputConfig { pull: Pull::None },
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));
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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super::execute(unit, spi, 0b0000_0001);
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}
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#[test]
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#[timeout(3)]
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fn test_spi_writes_correctly_to_pin_1(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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Some(ctx.mosi),
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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let pcnt = Pcnt::new(ctx.pcnt);
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let unit = pcnt.unit0;
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unit.channel0.set_edge_signal(PcntSource::from_pin(
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ctx.mosi_mirror,
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PcntInputConfig { pull: Pull::None },
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));
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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super::execute(unit, spi, 0b0000_0010);
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}
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#[test]
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#[timeout(3)]
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fn test_spi_writes_correctly_to_pin_2(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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Some(ctx.mosi),
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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let pcnt = Pcnt::new(ctx.pcnt);
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let unit = pcnt.unit0;
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unit.channel0.set_edge_signal(PcntSource::from_pin(
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ctx.mosi_mirror,
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PcntInputConfig { pull: Pull::None },
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));
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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super::execute(unit, spi, 0b0000_0100);
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}
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#[test]
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#[timeout(3)]
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fn test_spi_writes_correctly_to_pin_3(ctx: Context) {
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let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0)
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.with_pins(
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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esp_hal::gpio::NO_PIN,
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Some(ctx.mosi),
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esp_hal::gpio::NO_PIN,
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)
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.with_dma(ctx.dma_channel);
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let pcnt = Pcnt::new(ctx.pcnt);
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let unit = pcnt.unit0;
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unit.channel0.set_edge_signal(PcntSource::from_pin(
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ctx.mosi_mirror,
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PcntInputConfig { pull: Pull::None },
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));
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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super::execute(unit, spi, 0b0000_1000);
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}
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}
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