* feat: Update rx-tx order in i2s * feat: Update rx-tx order in dma macros * feat: Update rx-tx order in spi * feat: Update rx-tx order in aes * feat: Update rx-tx order in mem2mem * feat: Update rx-tx order in twai and split methods * feat: Update rx-tx order in twai * feat: Update rx-tx order in twai and uart docs * docs: Add sentence about order * docs: Update changelog * feat: Update rx-tx order in embassy_interrupt_spi_dma tests * style: Rustfmt * docs: Migrating guide * fix: Typo Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Diff Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Tests rx-tx order * fix: Update new_with_default_pins order * feat: Update rx/tx order in hil_test::common_test_pins! * feat: Update dma_extmem2mem example * fix: Revert deleted input arg * style: rustfmt * feat: Disable test_asymmetric_dma_transfer for S2 --------- Co-authored-by: Dániel Buga <bugadani@gmail.com>
119 lines
3.2 KiB
Rust
119 lines
3.2 KiB
Rust
//! RMT Loopback Test
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//!
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//! It's assumed GPIO2 is connected to GPIO3
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//! (GPIO9 and GPIO10 for esp32s2 and esp32s3)
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//! (GPIO26 and GPIO27 for esp32)
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//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use esp_hal::{
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gpio::Io,
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prelude::*,
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rmt::{PulseCode, Rmt, RxChannel, RxChannelConfig, TxChannel, TxChannelConfig},
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};
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use hil_test as _;
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use super::*;
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#[init]
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fn init() {}
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#[test]
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#[timeout(1)]
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fn rmt_loopback() {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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cfg_if::cfg_if! {
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if #[cfg(feature = "esp32h2")] {
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let freq = 32.MHz();
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} else {
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let freq = 80.MHz();
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}
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};
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let rmt = Rmt::new(peripherals.RMT, freq).unwrap();
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let (rx, tx) = hil_test::common_test_pins!(io);
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let tx_config = TxChannelConfig {
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clk_divider: 255,
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..TxChannelConfig::default()
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};
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let tx_channel = {
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use esp_hal::rmt::TxChannelCreator;
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rmt.channel0.configure(tx, tx_config).unwrap()
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};
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let rx_config = RxChannelConfig {
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clk_divider: 255,
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idle_threshold: 1000,
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..RxChannelConfig::default()
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};
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cfg_if::cfg_if! {
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if #[cfg(feature = "esp32")] {
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let rx_channel = {
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use esp_hal::rmt::RxChannelCreator;
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rmt.channel1.configure(rx, rx_config).unwrap()
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};
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} else if #[cfg(feature = "esp32s2")] {
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let rx_channel = {
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use esp_hal::rmt::RxChannelCreator;
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rmt.channel1.configure(rx, rx_config).unwrap()
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};
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} else if #[cfg(feature = "esp32s3")] {
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let rx_channel = {
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use esp_hal::rmt::RxChannelCreator;
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rmt.channel7.configure(rx, rx_config).unwrap()
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};
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} else {
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let rx_channel = {
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use esp_hal::rmt::RxChannelCreator;
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rmt.channel2.configure(rx, rx_config).unwrap()
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};
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}
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}
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let mut tx_data = [PulseCode {
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level1: true,
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length1: 200,
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level2: false,
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length2: 50,
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}; 20];
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tx_data[tx_data.len() - 2] = PulseCode {
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level1: true,
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length1: 3000,
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level2: false,
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length2: 500,
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};
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tx_data[tx_data.len() - 1] = PulseCode::default();
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let mut rcv_data = [PulseCode {
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level1: false,
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length1: 0,
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level2: false,
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length2: 0,
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}; 20];
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let rx_transaction = rx_channel.receive(&mut rcv_data).unwrap();
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let tx_transaction = tx_channel.transmit(&tx_data);
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rx_transaction.wait().unwrap();
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tx_transaction.wait().unwrap();
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// the last two pulse-codes are the ones which wait for the timeout so
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// they can't be equal
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assert_eq!(&tx_data[..18], &rcv_data[..18]);
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}
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}
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