esp-hal/hil-test/tests/uart_tx_rx_async.rs
Sergio Gasquez Arcos b5f0246129
Reordered RX-TX pairs to be consistent (#2074)
* feat: Update rx-tx order in i2s

* feat: Update rx-tx order in dma macros

* feat: Update rx-tx order in spi

* feat: Update rx-tx order in aes

* feat: Update rx-tx order in mem2mem

* feat: Update rx-tx order in twai and split methods

* feat: Update rx-tx order in twai

* feat: Update rx-tx order in twai and uart docs

* docs: Add sentence about order

* docs: Update changelog

* feat: Update rx-tx order in embassy_interrupt_spi_dma tests

* style: Rustfmt

* docs: Migrating guide

* fix: Typo

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Diff

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Tests rx-tx order

* fix: Update new_with_default_pins order

* feat: Update rx/tx order in hil_test::common_test_pins!

* feat: Update dma_extmem2mem example

* fix: Revert deleted input arg

* style: rustfmt

* feat: Disable test_asymmetric_dma_transfer for S2

---------

Co-authored-by: Dániel Buga <bugadani@gmail.com>
2024-09-06 09:56:10 +00:00

62 lines
1.4 KiB
Rust

//! UART TX/RX Async Test
//!
//! Folowing pins are used:
//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
//!
//! Connect TX and RX pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
//% FEATURES: generic-queue
#![no_std]
#![no_main]
use esp_hal::{
gpio::Io,
peripherals::{UART0, UART1},
uart::{UartRx, UartTx},
Async,
};
use hil_test as _;
struct Context {
rx: UartRx<'static, UART1, Async>,
tx: UartTx<'static, UART0, Async>,
}
#[cfg(test)]
#[embedded_test::tests(executor = esp_hal_embassy::Executor::new())]
mod tests {
use defmt::assert_eq;
use super::*;
#[init]
async fn init() -> Context {
let peripherals = esp_hal::init(esp_hal::Config::default());
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let (rx, tx) = hil_test::common_test_pins!(io);
let tx = UartTx::new_async(peripherals.UART0, tx).unwrap();
let rx = UartRx::new_async(peripherals.UART1, rx).unwrap();
Context { rx, tx }
}
#[test]
#[timeout(3)]
async fn test_send_receive(mut ctx: Context) {
let byte = [0x42];
let mut read = [0u8; 1];
ctx.tx.flush_async().await.unwrap();
ctx.tx.write_async(&byte).await.unwrap();
let _ = ctx.rx.read_async(&mut read).await;
assert_eq!(read, byte);
}
}