* Update a bunch of dependencies
* Implement `embedded-io` and `embedded-io-async` traits for USB Serial JTAG
* Implement `embedded-io` and `embedded-io-async` traits for UART
* Fix `embassy_serial` examples
* Update CHANGELOG
* Address review comments
* Use all remaining memory for stack(s)
* Remove HEAP related code from RISCV linker scripts
* Fix direct-boot / mcu-boot linker scripts
* Use a statically allocated stack for core-1
* direct vectoring support added
* provide minimal handlers for hooking the vector table directly
* changed direct vectoring interrupt enable interface to map to CPU interrupt
* direct vectoring interrupt nesting
* removed unused dependency
* added tentative c2 and c6 support for direct vector table hooking
* added direct vectoring examples
* added direct vectoring examples
* updated changelog
* added direct vectoring to CI
* Added H2 support and example, moved helpers to esp-hal-common
* Added H2 direct vectoring example to CI
* Removed remnants of removed feature
* C6 and H2 examples fixed
* C6 and H2 examples fixed
* C6 and H2 examples fixed
* Comment fixed
* Added preemption flag to RT
---------
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update to latest (unreleased) versions of PACs
* Update `SDMCC` peripheral to `SDHOST` for ESP32
* Fix `USB_DEVICE` interrupts
* Fix references to various renamed GPIO fields for ESP32-S2
* Update and re-organize the `rmt` driver
* Update CHANGELOG
* Remove the old `pulse_control` driver
* Update `esp-hal-smartled` to use the new `rmt` driver instead
* Update the `hello_rgb` example for each chip
* Update CHANGELOG
* Add Initial MCPWM DeadTime configuration
* Add option to use other channel for action trigger
* Fix build for non-esp32s3 (register name difference)
* Fix changelog build & add a way to update RED/FED after construction
* Fix regs
* Implementing ASYNC features for USB_SERIAL_JTAG (work in progress)
Fix: Interrupt name
* Async works for USB Serial/JTAG
PS. : Yet only for esp32c3, we need to update PACs
Temporary example fix
* Adjustment for different chips
+ Update examples according to upstream
+ Code cleaning
Rust format
* Add record to the CHANGELOG
* Code cleaning, getting rid of useless generic argument
Typo fix
Fix fmt
* deep sleep api for esp32
* move to list of wakeup sources
* improve Ext0WakeupSource - still WIP
* add deep sleep with timer wakeup example
add Ext0 wakeup source (WIP/Non-working)
* removed alloc (using heapless now)
* Sleep: ext0 wakeup working
* add sleep_timer_ext0 example
* API change: move sleep into RTC as sleep, sleep_deep, sleep_light
* fix sleep examples for new API
* sleep only implemented for esp32 at this time
* sleep only implemented for esp32 at this time
* Implement a simple RTCPin trait to support sleep
* implement RTCPin for all xtensa SOC
* cargo fmt & update changelog
* fix change log order (accidentally swaped during rebase)
* implement Drop for Ext0WakeupSource
* added Ext1 wakeup source
* cargo fmt
* healpess was unused, removed
* fix pase macro usage
* adc_cal: c2: Add efuse functions for reading calibration
* adc_cal: c3: Add efuse functions for reading calibration
* adc_cal: c6: Add efuse functions for reading calibration
* adc_cal: Add extra traits to support calibration
- `AdcCalScheme<ADCI>` implemented for each calibration scheme (basic, linear, curved)
- `AdcCalEfuse` implemented for each ADC unit to get calibration data from efuse bits
* adc_cal: Add basic ADC calibration scheme
Basic calibration is related to setting some initial bias value to ADC unit.
Such values usually is stored in efuse bit fields but also can be measured
in runtime by connecting ADC input to ground internally.
* adc_cal: Add line fitting ADC calibration scheme
This scheme also includes basic calibration and implements gain correction based
on reference point.
Reference point is a pair of reference voltage and corresponding mean raw ADC
value. Such raw values usually is stored in efuse bit fields for each supported
attenuation.
Possibly it also can be measured in runtime by connecting ADC to reference
voltage internally.
* adc_cal: Add curve fitting ADC calibration scheme
This scheme also includes basic and linear and implements final polynomial error
correction.
* adc_cal: riscv: Add ADC calibration implementation for riscv chips
* adc_cal: c2: Add calibrated ADC reading example
This example uses line fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: c3: Add calibrated ADC reading example
This example uses curve fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: c6: Add calibrated ADC reading example
This example uses curve fitting calibration scheme by default.
It periodically prints both raw measured value and computed millivolts.
* adc_cal: riscv: Add changelog entry for ADC calibration
* Introduce a trait for DMA channels
This trait is then used to hold types related to the particular DMA channel. This change allows us to simplify user-facing types.
* Remove private type from I2s
* Remove redundant spi3 example, update examples
* Merge markdown sections
* Add changelog entry
* Add ROM MD5 definitions in linker and devices
* Add initial MD5 support
* Implement traits and add comments to MD5 module
* Add MD5 example to ESP32-C3
* Test MD5 context on the quick brown fox
* Implemenr From<Context> for Digest
* Add MD5 to the rest of the examples
* Add docs for MD5
* Remove #[repr(transparent)] from md5::Digest
* Update CHANGELOG.md
* Create issue_handler.yml
* No longer re-export `embedded-hal`, hide exported macros in documentation
* Add simple package-level documentation for each HAL package
* Clean up/simplify re-exports
* Fix the examples that I broke
* Ensure top-level modules/types/functions have doc comments
* Update CHANGELOG
* Re-export the `soc::psram` module where available
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
This is temporary measure, as the problem cannot be solved cleanly right
now.
The issue is that the msrv check uses the stable compiler, which uses a
stable cargo. With a stable cargo, the unstable `build-std` option is
not respected within `.cargo/config.toml`. This means `core` is never
rebuilt with the atomic cfg flags so we get this error when building log
version 0.4.19. The 0.4.19 release uses the atomic cfg flags instead of
a custom build script, so by switching back to 0.4.188888888 we can avoid this
issue... for now at least.
* H2: Add initial i2s support and i2s_read and i2s_sound examples
* Add I2S_SCLK and I2S_DEFAULT_CLK_SRC constants for all chips
* Update I2S driver
* fmt
* Add changelog
* Change DIN GPIO17 to GPIO14 in ESP32 i2s_read example
* First README prototype
* README update
Fixed link, uncommented Matrix link, made some preparations before docs will be posted
* Added a change to CHANGELOG
* typo: return header sign back
* Process Fosc frequencies for ECO1+ ESP32C6 chips
e3148369f3
* Final update for FOSC calibration (ESP32C6)
+ fixed few errors
* Fix format + add update to Changelog
Formatting
Formatting (1)
* First README prototype
* README update
Fixed link, uncommented Matrix link, made some preparations before docs will be posted
* Added a change to CHANGELOG
* typo: return header sign back
* Use built-in LED pin (gpio2) in blinky example
Hi, I was just running the blinky example and noticed the comments about an LED
being connected to pin GPIO25. I was thinking it might makes more sense to use
the built-in LED pin instead, and no external hardware would be required.
* Add note on GPIO2 led
* Add GPIO2 LED pin change to changelog
* H2: Use PLL_48M_CLK in Timg driver and add imer_interrupt example
* Clean timer driver, add helper configure_src_clk and configure_wdt_src_clk methods
* H2: Add imer_interrupt example
* add helper methods for selecting default clk src
* Change PR number in the Changelog
* Add efuse field tables from IDF
* Add efuse fields constants generator
* Fix MAC field in efuse tables
* Add common efuse field impl
* Add efuse fields support for chips
* Add efuse changes to changelog
* Async GPIO multibank fix
- Removes dead code from the default impl of the BankAccess trait
- Adds one new function to the async module to control the interrupt
enable for any pin
* Add changelog entry
* Simplify the `Delay` driver, derive `Clone` and `Copy`
The RISC-V and Xtensa implementations of the delay functionality are both safe to access from multiple contexts, and the `Delay` struct does not take ownership of any peripheral struct, so `Delay` is safe to clone/copy
* Update the CHANGELOG
* Update the `GDMA` driver to support the ESP32-H2
* Update the `SPI` driver to support the ESP32-H2
* Add `SPI` examples for ESP32-H2
* Update CHANGELOG
* Remove copy-pasted references to ESP32-C6
* Update GPIO pins used in SPI examples, add `qspi_flash` example
* Update SPI clock configuration to produce correct clock rate
* Correct comment regarding clock source frequency
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
* H2: Add PLL_48M_CLK src to ClockControl and RawClocks
* H2: Use PLL_48M_CLK as SPI clk src
* H2: cleanup commented block in SPI driver
* H2: update docs comment in embassy_spi example
* fmt
* Add a new line in embassy_spi example
---------
Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
* feat: relocate riscv isr to iram
Previously, the trap vector itself and its immediate callees
(`_start_trap` and `_start_trap_rust_hal`) were located in the mapped
instruction flash range `0x420..`, increasing cache pressure and adding
variable latency to the very beginning of the interrupt/exception
service flow.
This change places those routines in iram directly:
```
Num: Value Size Type Bind Vis Ndx Name
48177: 40380280 2428 FUNC GLOBAL DEFAULT 6 _start_trap_rust_hal
48197: 40380bfc 54 FUNC GLOBAL DEFAULT 6 _start_trap_rust
48265: 40380200 0 FUNC GLOBAL DEFAULT 6 _vector_table
48349: 40380100 0 NOTYPE GLOBAL DEFAULT 6 default_start_trap
48350: 40380100 0 NOTYPE GLOBAL DEFAULT 6 _start_trap
```
As seen via `readelf -W -s -C ./target/riscv32imc-unknown-none-elf/debug/examples/gpio_interrupt | grep -E _start_trap\|_vector\|Ndx`
* feat(riscv): place .trap in RAM
This change follows through on relocating the `_vector_table`,
`_start_trap`, and `_start_trap_rust` functions for all present
build/link modes for the 'c2, 'c3, 'c6, and 'h2.
It has been tested by running the `software_interrupts` example for the
'c3 in direct-boot and esp-bootloader contexts, but I wasn't able to
identify how to run the `mcu-boot` mode for the 'c3, nor do I have
present access to any of the other devices for testing.
* docs: Update CHANGELOG.md
* Support for multicore async GPIO:
Use the correct registers depending on which core the interrupt is being
serviced on. Fixed a bug in the `esp32::gpio_intr` which would enable
the interrupt on both cores. It now enables the interrupt for the core
in which `listen()` is called.
* add changelog item
* Simplify GPIO interrupt status
For now, only the -c3.
---
Open up LEDC fade support to all chips.
The C6 chip needs some special handling because its fade registers also
handle gamma, and the ESP chip needs some special handling because it
has two banks of channels. The code to handle these is already present
in channel.rs, but needs to be copied and adapted. Do that, and drop
all the esp32c3 feature checks.
---
Add a function to poll the duty-fade state
Use the unmasked interrupt bit in the LEDC register block, since that
will get updated by the hardware whether or not we've connected anything
to the interrupt source. Also be sure to clear that bit before starting
a new fade, so it's always clear while fading.
This will allow dumb (non-async-code) polling of the fade state after
one is started by the start_duty_fade API.
---
Fix non-C3 devices to use the right int_raw bits
These are inconsistently named between the esp32 variants.
---
Add examples of hardware duty-cycle fading
Just a relatively simple zero to 100 and back to zero, over a total of 2
seconds, to get a breathing effect.
This does make the main loop{} have a 2-second period instead of the
current nearly-zero period, but nothing else is happening so that's
fine.
---
Fix two bugs in hardware fading
When figuring out how many duty-cycle changes need to happen per counter
overflow, we need to use the absolute value of the difference between
the start and end duty values, not the raw difference. When fading from
(e.g.) 100% to 0, this will overflow, and both the debug-mode panic and
the release-mode wrapping behavior give the wrong delta value.
So calculate an absolute value difference first, and use that.
Then, when running through the while loop that allocates bits between
pwm_cycles and duty_cycle, the check on pwm_cycles was wrong -- since
the value reduces each time through the loop, we need to keep looping as
long as it's *above* some threshold, not below.
---
Simplify and refactor duty-cycle fade code
I'm not sure if this will fix the extremely-short fade times that we're
seeing with the older code, but we'll see.
Move all the calculations out of the ChannelHW implementations, and make
those *just* set registers. The calculations are the same for all chip
variants, so don't need to be duplicated for each chip feature, like the
register macros are.
Change the calculations from a loop doing bit shifts, to an explicit
division and a couple of range checks. This way we can get a lot closer
to the requested percentages and durations.
Use the u32::abs_diff function instead of open-coding it (now that I see
it exists).
Use u16::try_from() to limit the range of values, and use try_into<u16>
and map_err and the ? operator to more clearly handle numbers out of
range.
Drop the Result<> return type from the ChannelHW function, as it can't
fail anymore.
Fix the duty_range value -- before, when duty_exp was (say) 8,
duty_range would be 256, and if one of the *_duty_pct values was 100,
the start or end duty value would be too big. The range of start and
end duty values is 0..255, so we have to subtract one to handle 100%.
Finally, add a comment on the is_duty_fade_running{,_hw} methods.
---
Some fades can't work; return errors for them.
Add a new Error enum value with a sub-error enum with more details.
Return it from the error cases in the fade method.
If the calculated cycles_per_step is more than 10 bits, fail as well;
the field in the register is only 10 bits wide.
Fix all the examples to run a 1-second fade instead of a 2-second, since
the 2-second fade will run into this error. (Assert that, as well.)
---
When fading on a -c6 chip, set two more registers
The gamma functionality of -c6 chips needs two more fields set. One
tells the chip how many gamma stages it should iterate through, but we
only implement linear fading, so always use 1. The other tells the chip
to latch the value of the other gamma registers into the chosen slot, so
even though its value never changes, the write needs to happen.
---
Add changelog entry
* async gpio fixes
- Fix pin number calculation for bank1
- Clear interrupt status after disabling interrupt to avoid hardware
pending another interrupt
- Clear interrupt status per pin when we create the input future
* add changelog item
* Small refactor to extract functions for setting up reads/writes
* Implement async capabilities for `I2C` driver
* Add async I2C examples for each supported chip
* Update CHANGELOG
