Update the top-level README and CHANGELOG, fix blinky example
This commit is contained in:
parent
ad0b4e4bef
commit
ca54d29fcb
@ -12,12 +12,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
|
||||
### Added
|
||||
|
||||
- Add bare-bones PSRAM support for ESP32 (#506)
|
||||
- Add initial support for the ESP32-H2 (#513)
|
||||
|
||||
### Fixed
|
||||
|
||||
- DMA is supported for SPI3 on ESP32-S3 (#507)
|
||||
|
||||
|
||||
## [0.9.0] - 2023-05-02
|
||||
|
||||
### Added
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||

|
||||
[](https://matrix.to/#/#esp-rs:matrix.org)
|
||||
|
||||
**H**ardware **A**bstraction **L**ayer crates for the **ESP32**, **ESP32-C2/C3/C6**, and **ESP32-S2/S3** from Espressif.
|
||||
**H**ardware **A**bstraction **L**ayer crates for the **ESP32**, **ESP32-C2/C3/C6**, **ESP32-H2**, and **ESP32-S2/S3** from Espressif.
|
||||
|
||||
These HALs are `no_std`; if you are looking for `std` support, please use [esp-idf-hal] instead.
|
||||
|
||||
@ -18,6 +18,7 @@ If you have any questions, comments, or concerns, please [open an issue], [start
|
||||
| [esp32c2-hal] | `riscv32imc-unknown-none-elf` | [ESP32-C2] |
|
||||
| [esp32c3-hal] | `riscv32imc-unknown-none-elf` | [ESP32-C3] |
|
||||
| [esp32c6-hal] | `riscv32imac-unknown-none-elf` | [ESP32-C6] |
|
||||
| [esp32h2-hal] | `riscv32imac-unknown-none-elf` | _Currently unavailable_ |
|
||||
| [esp32s2-hal] | `xtensa-esp32s2-none-elf` | [ESP32-S2] |
|
||||
| [esp32s3-hal] | `xtensa-esp32s3-none-elf` | [ESP32-S3] |
|
||||
|
||||
@ -79,7 +80,7 @@ There are a number of other crates within the [esp-rs organization] which can be
|
||||
|
||||
The **M**inimum **S**upported **R**ust **V**ersions are:
|
||||
|
||||
- `1.65.0` for RISC-V devices (**ESP32-C2**, **ESP32-C3**, **ESP32-C6**)
|
||||
- `1.65.0` for RISC-V devices (**ESP32-C2**, **ESP32-C3**, **ESP32-C6**, **ESP32-H2**)
|
||||
- `1.65.0` for Xtensa devices (**ESP32**, **ESP32-S2**, **ESP32-S3**)
|
||||
- `1.67.0` for all `async` examples (`embassy_hello_world`, `embassy_wait`, etc.)
|
||||
|
||||
|
||||
@ -10,9 +10,9 @@ use esp32h2_hal::{
|
||||
gpio::IO,
|
||||
peripherals::Peripherals,
|
||||
prelude::*,
|
||||
// timer::TimerGroup,
|
||||
timer::TimerGroup,
|
||||
Delay,
|
||||
// Rtc,
|
||||
Rtc,
|
||||
};
|
||||
use esp_backtrace as _;
|
||||
|
||||
@ -24,24 +24,24 @@ fn main() -> ! {
|
||||
|
||||
// Disable the watchdog timers. For the ESP32-H2, this includes the Super WDT,
|
||||
// and the TIMG WDTs.
|
||||
// let mut rtc = Rtc::new(peripherals.LP_CLKRST);
|
||||
// let timer_group0 = TimerGroup::new(
|
||||
// peripherals.TIMG0,
|
||||
// &clocks,
|
||||
// &mut system.peripheral_clock_control,
|
||||
// );
|
||||
// let mut wdt0 = timer_group0.wdt;
|
||||
// let timer_group1 = TimerGroup::new(
|
||||
// peripherals.TIMG1,
|
||||
// &clocks,
|
||||
// &mut system.peripheral_clock_control,
|
||||
// );
|
||||
// let mut wdt1 = timer_group1.wdt;
|
||||
let mut rtc = Rtc::new(peripherals.LP_CLKRST);
|
||||
let timer_group0 = TimerGroup::new(
|
||||
peripherals.TIMG0,
|
||||
&clocks,
|
||||
&mut system.peripheral_clock_control,
|
||||
);
|
||||
let mut wdt0 = timer_group0.wdt;
|
||||
let timer_group1 = TimerGroup::new(
|
||||
peripherals.TIMG1,
|
||||
&clocks,
|
||||
&mut system.peripheral_clock_control,
|
||||
);
|
||||
let mut wdt1 = timer_group1.wdt;
|
||||
|
||||
// rtc.swd.disable();
|
||||
// rtc.rwdt.disable();
|
||||
// wdt0.disable();
|
||||
// wdt1.disable();
|
||||
rtc.swd.disable();
|
||||
rtc.rwdt.disable();
|
||||
wdt0.disable();
|
||||
wdt1.disable();
|
||||
|
||||
// Set GPIO5 as an output, and set its state high initially.
|
||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user