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Fix: incorrect variable access (#603)

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* Fix: incorrect variable access 


Added the change to the Changelog


Fix: typo

* Additional details for the CHANGELOG entry
This commit is contained in:
Kirill Mikhailov 2023-06-22 11:24:19 +02:00 committed by Scott Mabin
parent 0c1d59b553
commit 14f46371eb
2 changed files with 4 additions and 1 deletions
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1
CHANGELOG.md
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@ -68,6 +68,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- ESP32-C6: Support FOSC CLK calibration for ECO1+ chip revisions - ESP32-C6: Support FOSC CLK calibration for ECO1+ chip revisions
- Fixed CI by pinning the log crate to 0.4.18 (#600) - Fixed CI by pinning the log crate to 0.4.18 (#600)
- ESP32-S3: Fix calculation of PSRAM start address - ESP32-S3: Fix calculation of PSRAM start address
- Fixed wrong variable access (FOSC CLK calibration for ESP32-C6 #593)
### Changed ### Changed

4
esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs
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@ -646,6 +646,8 @@ impl RtcClock {
let minor: u8 = Efuse::read_field_le(WAFER_VERSION_MINOR); let minor: u8 = Efuse::read_field_le(WAFER_VERSION_MINOR);
let major: u8 = Efuse::read_field_le(WAFER_VERSION_MAJOR); let major: u8 = Efuse::read_field_le(WAFER_VERSION_MAJOR);
let mut slowclk_cycles = slowclk_cycles;
// The Fosc CLK of calibration circuit is divided by 32 for ECO1. // The Fosc CLK of calibration circuit is divided by 32 for ECO1.
// So we need to divide the calibrate cycles of the FOSC for ECO1 and above // So we need to divide the calibrate cycles of the FOSC for ECO1 and above
// chips by 32 to avoid excessive calibration time.*/ // chips by 32 to avoid excessive calibration time.*/
@ -654,7 +656,7 @@ impl RtcClock {
// formula: MAJOR * 100 + MINOR. (if the result is 1, then version is v0.1) // formula: MAJOR * 100 + MINOR. (if the result is 1, then version is v0.1)
if (major * 100 + minor) > 0 { if (major * 100 + minor) > 0 {
if cal_clk == RtcCalSel::RtcCalRcFast { if cal_clk == RtcCalSel::RtcCalRcFast {
let slowclk_cycles = slowclk_cycles >> 5; slowclk_cycles >>= 5;
} }
} }