ESP32-S3 Octal SPIRAM Support (#610)

* ESP32-S3 Octal SPIRAM Support

* Adjust some code comments

CHANGELOG.md

@@ -45,6 +45,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Add a `debug` feature to enable the PACs' `impl-register-debug` feature (#596)
 - Add initial support for `I2S` in ESP32-H2 (#597)
 - Fix rom::crc docs
+- Add octal PSRAM support for ESP32-S3 (#610)
 
 ### Changed
 

esp-hal-common/Cargo.toml

@@ -82,6 +82,10 @@ psram_2m = []
 psram_4m = []
 psram_8m = []
 
+opsram_2m = []
+opsram_4m = []
+opsram_8m = []
+
 # Implement the `embedded-hal==1.0.0-alpha.x` traits
 eh1 = ["embedded-hal-1", "embedded-hal-nb", "embedded-can"]
 

esp32s3-hal/Cargo.toml

@@ -70,6 +70,9 @@ psram     = []
 psram_2m  = ["esp-hal-common/psram_2m", "psram"]
 psram_4m  = ["esp-hal-common/psram_4m", "psram"]
 psram_8m  = ["esp-hal-common/psram_8m", "psram"]
+opsram_2m  = ["esp-hal-common/opsram_2m", "psram"]
+opsram_4m  = ["esp-hal-common/opsram_4m", "psram"]
+opsram_8m  = ["esp-hal-common/opsram_8m", "psram"]
 
 [[example]]
 name              = "spi_eh1_loopback"
@@ -95,6 +98,10 @@ required-features = ["embassy", "async"]
 name              = "psram"
 required-features = ["psram_2m"]
 
+[[example]]
+name              = "octal_psram"
+required-features = ["opsram_2m"]
+
 [[example]]
 name              = "embassy_serial"
 required-features = ["embassy", "async"]

esp32s3-hal/examples/octal_psram.rs

@@ -0,0 +1,80 @@
+//! This shows how to use PSRAM as heap-memory via esp-alloc
+//!
+//! You need an ESP32-S3 with at least 2 MB of PSRAM memory.
+
+#![no_std]
+#![no_main]
+
+use esp32s3_hal::{
+    clock::ClockControl,
+    peripherals::Peripherals,
+    prelude::*,
+    soc,
+    timer::TimerGroup,
+    Rtc,
+};
+use esp_backtrace as _;
+use esp_println::println;
+
+extern crate alloc;
+
+#[global_allocator]
+static ALLOCATOR: esp_alloc::EspHeap = esp_alloc::EspHeap::empty();
+
+fn init_psram_heap() {
+    unsafe {
+        ALLOCATOR.init(
+            soc::psram::PSRAM_VADDR_START as *mut u8,
+            soc::psram::PSRAM_BYTES,
+        );
+    }
+}
+
+#[entry]
+fn main() -> ! {
+    #[cfg(debug_assertions)]
+    compile_error!("PSRAM on ESP32-S3 needs to be built in release mode");
+
+    esp_println::logger::init_logger_from_env();
+
+    let peripherals = Peripherals::take();
+    soc::psram::init_psram(peripherals.PSRAM);
+    init_psram_heap();
+
+    let mut system = peripherals.SYSTEM.split();
+    let clocks = ClockControl::configure(
+        system.clock_control,
+        esp_hal_common::clock::CpuClock::Clock240MHz,
+    )
+    .freeze();
+
+    let timer_group0 = TimerGroup::new(
+        peripherals.TIMG0,
+        &clocks,
+        &mut system.peripheral_clock_control,
+    );
+    let mut wdt = timer_group0.wdt;
+    let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+
+    // Disable MWDT and RWDT (Watchdog) flash boot protection
+    wdt.disable();
+    rtc.rwdt.disable();
+
+    println!("Going to access PSRAM");
+    let mut large_vec: alloc::vec::Vec<u32> = alloc::vec::Vec::with_capacity(500 * 1024 / 4);
+
+    for i in 0..(500 * 1024 / 4) {
+        large_vec.push((i & 0xff) as u32);
+    }
+
+    println!("vec size = {} bytes", large_vec.len() * 4);
+    println!("vec address = {:p}", large_vec.as_ptr());
+    println!("vec[..100] = {:?}", &large_vec[..100]);
+
+    let string = alloc::string::String::from("A string allocated in PSRAM");
+    println!("'{}' allocated at {:p}", &string, string.as_ptr());
+
+    println!("done");
+
+    loop {}
+}

esp32s3-hal/ld/rom-functions.x

@@ -26,3 +26,7 @@ PROVIDE(esp_rom_crc8_be = 0x40001cd4);
 PROVIDE(esp_rom_crc32_le = 0x40001c98);
 PROVIDE(esp_rom_crc16_le = 0x40001cb0);
 PROVIDE(esp_rom_crc8_le = 0x40001cc8);
+
+PROVIDE (esp_rom_opiflash_exec_cmd = 0x400008b8);
+PROVIDE( esp_rom_spi_set_dtr_swap_mode = 0x4000093c );
+PROVIDE( esp_rom_opiflash_pin_config = 0x40000894 );