From 14f46371eb34e1d94add06ac952a1a786d955510 Mon Sep 17 00:00:00 2001
From: Kirill Mikhailov <62840029+playfulFence@users.noreply.github.com>
Date: Thu, 22 Jun 2023 11:24:19 +0200
Subject: [PATCH] Fix: incorrect variable access (#603)

* Fix: incorrect variable access


Added the change to the Changelog


Fix: typo

* Additional details for the CHANGELOG entry
---
 CHANGELOG.md                               | 1 +
 esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 007ecb4d6..6f91f4e50 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -68,6 +68,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - ESP32-C6: Support FOSC CLK calibration for ECO1+ chip revisions
 - Fixed CI by pinning the log crate to 0.4.18 (#600)
 - ESP32-S3: Fix calculation of PSRAM start address
+- Fixed wrong variable access (FOSC CLK calibration for ESP32-C6 #593)
 
 ### Changed
 
diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs
index 5ba8ee539..e6a7232b9 100644
--- a/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs
+++ b/esp-hal-common/src/rtc_cntl/rtc/esp32c6.rs
@@ -646,6 +646,8 @@ impl RtcClock {
         let minor: u8 = Efuse::read_field_le(WAFER_VERSION_MINOR);
         let major: u8 = Efuse::read_field_le(WAFER_VERSION_MAJOR);
 
+        let mut slowclk_cycles = slowclk_cycles;
+
         // The Fosc CLK of calibration circuit is divided by 32 for ECO1.
         // So we need to divide the calibrate cycles of the FOSC for ECO1 and above
         // chips by 32 to avoid excessive calibration time.*/
@@ -654,7 +656,7 @@ impl RtcClock {
         // formula: MAJOR * 100 + MINOR. (if the result is 1, then version is v0.1)
         if (major * 100 + minor) > 0 {
             if cal_clk == RtcCalSel::RtcCalRcFast {
-                let slowclk_cycles = slowclk_cycles >> 5;
+                slowclk_cycles >>= 5;
             }
         }