Jesse Braham cf270700e7 Use the new esp-riscv-rt package for RISC-V HALs (#365) ... * Update PACs and modify `esp-hal-common` to use new `esp-riscv-rt` package * Update `esp32c2-hal` and `esp32c3-hal` to use `esp-riscv-rt` as well * Update all RISC-V examples to use `esp-riscv-rt` * Update RISC-V trap frame handling according to review feedback		2023-01-27 10:49:38 -08:00
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bl-esp32c2-memory.x	Re-enable RTC in remaining examples, fix linker scripts, fix CI	2022-10-12 10:01:13 -07:00
bl-linkall.x	Refactor the clock module, provide ROM functions via linker scripts (#353)	2023-01-23 07:12:33 -08:00
bl-riscv-link.x	Use the new esp-riscv-rt package for RISC-V HALs (#365)	2023-01-27 10:49:38 -08:00
db-esp32c2-link.x	Add startup code and build/linker scripts, add ADC, eFuse, GPIO, and TIMG	2022-10-11 10:11:36 -07:00
db-esp32c2-memory.x	Re-enable RTC in remaining examples, fix linker scripts, fix CI	2022-10-12 10:01:13 -07:00
db-linkall.x	Refactor the clock module, provide ROM functions via linker scripts (#353)	2023-01-23 07:12:33 -08:00
db-riscv-link.x	Use the new esp-riscv-rt package for RISC-V HALs (#365)	2023-01-27 10:49:38 -08:00
hal-defaults.x	Create the esp32c2-hal package and add it to the workspace	2022-10-11 08:03:43 -07:00
rom-functions.x	Refactor the clock module, provide ROM functions via linker scripts (#353)	2023-01-23 07:12:33 -08:00