Re-enable RTC in remaining examples, fix linker scripts, fix CI
This commit is contained in:
Jesse Braham
parent
2880ca4ca0
commit
5ddfacb1c6
16
.github/workflows/ci.yml
vendored
16
.github/workflows/ci.yml
vendored
@ -20,8 +20,12 @@ jobs:
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strategy:
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fail-fast: false
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matrix:
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chip: [esp32c2, esp32c3]
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toolchain: [stable, nightly]
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include:
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- chip: esp32c2
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features: "eh1,ufmt"
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- chip: esp32c3
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features: "eh1,smartled,ufmt"
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steps:
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- uses: actions/checkout@v2
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- uses: actions-rs/toolchain@v1
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@ -34,7 +38,7 @@ jobs:
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- uses: actions-rs/cargo@v1
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with:
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command: check
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args: --examples --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=eh1,smartled,ufmt
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args: --examples --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=${{ matrix.features }}
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check-xtensa:
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name: Check Xtensa Examples
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@ -111,7 +115,11 @@ jobs:
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strategy:
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fail-fast: false
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matrix:
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chip: [esp32c2, esp32c3]
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include:
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- chip: esp32c2
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features: "eh1,ufmt"
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- chip: esp32c3
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features: "eh1,smartled,ufmt"
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steps:
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- uses: actions/checkout@v2
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- uses: actions-rs/toolchain@v1
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@ -124,7 +132,7 @@ jobs:
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- uses: actions-rs/cargo@v1
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with:
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command: check
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args: --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=eh1,smartled,ufmt
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args: --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=${{ matrix.features }}
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msrv-xtensa:
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name: Check Xtensa MSRV
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@ -29,12 +29,12 @@ fn main() -> ! {
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// Disable the watchdog timers. For the ESP32-C2, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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// let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt0 = timer_group0.wdt;
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// rtc.swd.disable();
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// rtc.rwdt.disable();
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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@ -33,12 +33,12 @@ fn main() -> ! {
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// Disable the watchdog timers. For the ESP32-C2, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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// let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt0 = timer_group0.wdt;
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// rtc.swd.disable();
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// rtc.rwdt.disable();
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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// Set GPIO5 as an output
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@ -1,98 +0,0 @@
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//! This shows how to use RTC memory.
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//! RTC memory is retained during resets and during most sleep modes.
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//! Initialized memory is always re-initialized on startup.
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//! Uninitialzed memory isn't initialized on startup and can be used to keep
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//! data during resets. Zeroed memory is initialized to zero on startup.
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//! We can also run code from RTC memory.
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#![no_std]
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#![no_main]
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use esp32c2_hal::{
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clock::ClockControl,
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macros::ram,
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pac::Peripherals,
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prelude::*,
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timer::TimerGroup,
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};
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use esp_backtrace as _;
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use esp_println::println;
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use nb::block;
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use riscv_rt::entry;
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#[ram(rtc_fast)]
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static mut SOME_INITED_DATA: [u8; 2] = [0xaa, 0xbb];
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#[ram(rtc_fast, uninitialized)]
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static mut SOME_UNINITED_DATA: [u8; 2] = [0; 2];
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#[ram(rtc_fast, zeroed)]
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static mut SOME_ZEROED_DATA: [u8; 8] = [0; 8];
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut timer0 = timer_group0.timer0;
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let mut wdt0 = timer_group0.wdt;
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// Disable MWDT flash boot protection
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wdt0.disable();
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// The RWDT flash boot protection remains enabled and it being triggered is part
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// of the example
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timer0.start(1u64.secs());
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println!(
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"IRAM function located at {:p}",
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function_in_ram as *const ()
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);
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unsafe {
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println!("SOME_INITED_DATA {:x?}", SOME_INITED_DATA);
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println!("SOME_UNINITED_DATA {:x?}", SOME_UNINITED_DATA);
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println!("SOME_ZEROED_DATA {:x?}", SOME_ZEROED_DATA);
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SOME_INITED_DATA[0] = 0xff;
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SOME_ZEROED_DATA[0] = 0xff;
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println!("SOME_INITED_DATA {:x?}", SOME_INITED_DATA);
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println!("SOME_UNINITED_DATA {:x?}", SOME_UNINITED_DATA);
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println!("SOME_ZEROED_DATA {:x?}", SOME_ZEROED_DATA);
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if SOME_UNINITED_DATA[0] != 0 {
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SOME_UNINITED_DATA[0] = 0;
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SOME_UNINITED_DATA[1] = 0;
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}
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if SOME_UNINITED_DATA[1] == 0xff {
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SOME_UNINITED_DATA[1] = 0;
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}
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println!("Counter {}", SOME_UNINITED_DATA[1]);
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SOME_UNINITED_DATA[1] += 1;
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}
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println!(
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"RTC_FAST function located at {:p}",
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function_in_rtc_ram as *const ()
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);
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println!("Result {}", function_in_rtc_ram());
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loop {
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function_in_ram();
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block!(timer0.wait()).unwrap();
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}
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}
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#[ram]
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fn function_in_ram() {
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println!("Hello world!");
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}
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#[ram(rtc_fast)]
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fn function_in_rtc_ram() -> u32 {
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42
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}
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@ -34,11 +34,11 @@ fn main() -> ! {
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt = timer_group0.wdt;
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// let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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// Disable MWDT and RWDT (Watchdog) flash boot protection
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wdt.disable();
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// rtc.rwdt.disable();
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rtc.rwdt.disable();
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let syst = SystemTimer::new(peripherals.SYSTIMER);
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@ -1,25 +1,21 @@
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MEMORY
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{
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/*
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NOTE: the ESP32-C2 inherits from the ESP32-C3 in esptool, and uses the same memory map
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https://github.com/espressif/esptool/blob/ed64d20b051d05f3f522bacc6a786098b562d4b8/esptool/targets/esp32c3.py#L78-L90
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https://github.com/espressif/esptool/blob/10828527038d143e049790d330ac4de76ce987d6/esptool/targets/esp32c2.py#L53-L62
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MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"],
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[0x3C000000, 0x3C800000, "DROM"],
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[0x3FC80000, 0x3FCE0000, "DRAM"],
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[0x3C000000, 0x3C400000, "DROM"],
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[0x3FCA0000, 0x3FCE0000, "DRAM"],
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[0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
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[0x3FF00000, 0x3FF20000, "DROM_MASK"],
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[0x40000000, 0x40060000, "IROM_MASK"],
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[0x42000000, 0x42800000, "IROM"],
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[0x4037C000, 0x403E0000, "IRAM"],
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[0x50000000, 0x50002000, "RTC_IRAM"],
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[0x50000000, 0x50002000, "RTC_DRAM"],
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[0x600FE000, 0x60100000, "MEM_INTERNAL2"]]
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[0x3FF00000, 0x3FF50000, "DROM_MASK"],
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[0x40000000, 0x40090000, "IROM_MASK"],
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[0x42000000, 0x42400000, "IROM"],
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[0x4037C000, 0x403C0000, "IRAM"]]
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*/
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/* 272K of on soc RAM, 16K reserved for cache */
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ICACHE : ORIGIN = 0x4037C000, LENGTH = 0x4000
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ICACHE : ORIGIN = 0x4037C000, LENGTH = 16K
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/* Instruction RAM */
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IRAM : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 272K - 0x4000
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IRAM : ORIGIN = 0x4037C000 + 16K, LENGTH = 272K - 16K
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/* Data RAM */
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DRAM : ORIGIN = 0x3FCA0000, LENGTH = 0x30000
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@ -1,25 +1,21 @@
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MEMORY
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{
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/*
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NOTE: the ESP32-C2 inherits from the ESP32-C3 in esptool, and uses the same memory map
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https://github.com/espressif/esptool/blob/ed64d20b051d05f3f522bacc6a786098b562d4b8/esptool/targets/esp32c3.py#L78-L90
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https://github.com/espressif/esptool/blob/10828527038d143e049790d330ac4de76ce987d6/esptool/targets/esp32c2.py#L53-L62
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MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"],
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[0x3C000000, 0x3C800000, "DROM"],
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[0x3FC80000, 0x3FCE0000, "DRAM"],
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[0x3C000000, 0x3C400000, "DROM"],
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[0x3FCA0000, 0x3FCE0000, "DRAM"],
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[0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
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[0x3FF00000, 0x3FF20000, "DROM_MASK"],
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[0x40000000, 0x40060000, "IROM_MASK"],
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[0x42000000, 0x42800000, "IROM"],
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[0x4037C000, 0x403E0000, "IRAM"],
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[0x50000000, 0x50002000, "RTC_IRAM"],
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[0x50000000, 0x50002000, "RTC_DRAM"],
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[0x600FE000, 0x60100000, "MEM_INTERNAL2"]]
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[0x3FF00000, 0x3FF50000, "DROM_MASK"],
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[0x40000000, 0x40090000, "IROM_MASK"],
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[0x42000000, 0x42400000, "IROM"],
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[0x4037C000, 0x403C0000, "IRAM"]]
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*/
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/* 272K of on soc RAM, 16K reserved for cache */
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ICACHE : ORIGIN = 0x4037C000, LENGTH = 0x4000
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ICACHE : ORIGIN = 0x4037C000, LENGTH = 16K
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/* Instruction RAM */
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IRAM : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 272K - 0x4000
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IRAM : ORIGIN = 0x4037C000 + 16K, LENGTH = 272K - 16K
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/* Data RAM */
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DRAM : ORIGIN = 0x3FCA0000, LENGTH = 0x30000
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