From 5ddfacb1c63adace12685e408102a36dde719369 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Wed, 12 Oct 2022 10:01:13 -0700 Subject: [PATCH] Re-enable RTC in remaining examples, fix linker scripts, fix CI --- .github/workflows/ci.yml | 16 +++-- esp32c2-hal/examples/adc.rs | 6 +- esp32c2-hal/examples/gpio_interrupt.rs | 6 +- esp32c2-hal/examples/ram.rs | 98 -------------------------- esp32c2-hal/examples/systimer.rs | 4 +- esp32c2-hal/ld/bl-esp32c2-memory.x | 22 +++--- esp32c2-hal/ld/db-esp32c2-memory.x | 22 +++--- 7 files changed, 38 insertions(+), 136 deletions(-) delete mode 100644 esp32c2-hal/examples/ram.rs diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 23f698c5c..a6a97c0f5 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -20,8 +20,12 @@ jobs: strategy: fail-fast: false matrix: - chip: [esp32c2, esp32c3] toolchain: [stable, nightly] + include: + - chip: esp32c2 + features: "eh1,ufmt" + - chip: esp32c3 + features: "eh1,smartled,ufmt" steps: - uses: actions/checkout@v2 - uses: actions-rs/toolchain@v1 @@ -34,7 +38,7 @@ jobs: - uses: actions-rs/cargo@v1 with: command: check - args: --examples --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=eh1,smartled,ufmt + args: --examples --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=${{ matrix.features }} check-xtensa: name: Check Xtensa Examples @@ -111,7 +115,11 @@ jobs: strategy: fail-fast: false matrix: - chip: [esp32c2, esp32c3] + include: + - chip: esp32c2 + features: "eh1,ufmt" + - chip: esp32c3 + features: "eh1,smartled,ufmt" steps: - uses: actions/checkout@v2 - uses: actions-rs/toolchain@v1 @@ -124,7 +132,7 @@ jobs: - uses: actions-rs/cargo@v1 with: command: check - args: --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=eh1,smartled,ufmt + args: --manifest-path=${{ matrix.chip }}-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=${{ matrix.features }} msrv-xtensa: name: Check Xtensa MSRV diff --git a/esp32c2-hal/examples/adc.rs b/esp32c2-hal/examples/adc.rs index df90f4a12..d3498eb15 100644 --- a/esp32c2-hal/examples/adc.rs +++ b/esp32c2-hal/examples/adc.rs @@ -29,12 +29,12 @@ fn main() -> ! { // Disable the watchdog timers. For the ESP32-C2, this includes the Super WDT, // the RTC WDT, and the TIMG WDTs. - // let mut rtc = Rtc::new(peripherals.RTC_CNTL); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt0 = timer_group0.wdt; - // rtc.swd.disable(); - // rtc.rwdt.disable(); + rtc.swd.disable(); + rtc.rwdt.disable(); wdt0.disable(); let io = IO::new(peripherals.GPIO, peripherals.IO_MUX); diff --git a/esp32c2-hal/examples/gpio_interrupt.rs b/esp32c2-hal/examples/gpio_interrupt.rs index 7edc81c23..86dd749df 100644 --- a/esp32c2-hal/examples/gpio_interrupt.rs +++ b/esp32c2-hal/examples/gpio_interrupt.rs @@ -33,12 +33,12 @@ fn main() -> ! { // Disable the watchdog timers. For the ESP32-C2, this includes the Super WDT, // the RTC WDT, and the TIMG WDTs. - // let mut rtc = Rtc::new(peripherals.RTC_CNTL); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt0 = timer_group0.wdt; - // rtc.swd.disable(); - // rtc.rwdt.disable(); + rtc.swd.disable(); + rtc.rwdt.disable(); wdt0.disable(); // Set GPIO5 as an output diff --git a/esp32c2-hal/examples/ram.rs b/esp32c2-hal/examples/ram.rs deleted file mode 100644 index 4c6f187a0..000000000 --- a/esp32c2-hal/examples/ram.rs +++ /dev/null @@ -1,98 +0,0 @@ -//! This shows how to use RTC memory. -//! RTC memory is retained during resets and during most sleep modes. -//! Initialized memory is always re-initialized on startup. -//! Uninitialzed memory isn't initialized on startup and can be used to keep -//! data during resets. Zeroed memory is initialized to zero on startup. -//! We can also run code from RTC memory. - -#![no_std] -#![no_main] - -use esp32c2_hal::{ - clock::ClockControl, - macros::ram, - pac::Peripherals, - prelude::*, - timer::TimerGroup, -}; -use esp_backtrace as _; -use esp_println::println; -use nb::block; -use riscv_rt::entry; - -#[ram(rtc_fast)] -static mut SOME_INITED_DATA: [u8; 2] = [0xaa, 0xbb]; - -#[ram(rtc_fast, uninitialized)] -static mut SOME_UNINITED_DATA: [u8; 2] = [0; 2]; - -#[ram(rtc_fast, zeroed)] -static mut SOME_ZEROED_DATA: [u8; 8] = [0; 8]; - -#[entry] -fn main() -> ! { - let peripherals = Peripherals::take().unwrap(); - let system = peripherals.SYSTEM.split(); - let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - - let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); - let mut timer0 = timer_group0.timer0; - let mut wdt0 = timer_group0.wdt; - - // Disable MWDT flash boot protection - wdt0.disable(); - // The RWDT flash boot protection remains enabled and it being triggered is part - // of the example - - timer0.start(1u64.secs()); - - println!( - "IRAM function located at {:p}", - function_in_ram as *const () - ); - unsafe { - println!("SOME_INITED_DATA {:x?}", SOME_INITED_DATA); - println!("SOME_UNINITED_DATA {:x?}", SOME_UNINITED_DATA); - println!("SOME_ZEROED_DATA {:x?}", SOME_ZEROED_DATA); - - SOME_INITED_DATA[0] = 0xff; - SOME_ZEROED_DATA[0] = 0xff; - - println!("SOME_INITED_DATA {:x?}", SOME_INITED_DATA); - println!("SOME_UNINITED_DATA {:x?}", SOME_UNINITED_DATA); - println!("SOME_ZEROED_DATA {:x?}", SOME_ZEROED_DATA); - - if SOME_UNINITED_DATA[0] != 0 { - SOME_UNINITED_DATA[0] = 0; - SOME_UNINITED_DATA[1] = 0; - } - - if SOME_UNINITED_DATA[1] == 0xff { - SOME_UNINITED_DATA[1] = 0; - } - - println!("Counter {}", SOME_UNINITED_DATA[1]); - SOME_UNINITED_DATA[1] += 1; - } - - println!( - "RTC_FAST function located at {:p}", - function_in_rtc_ram as *const () - ); - println!("Result {}", function_in_rtc_ram()); - - loop { - function_in_ram(); - block!(timer0.wait()).unwrap(); - } -} - -#[ram] -fn function_in_ram() { - println!("Hello world!"); -} - -#[ram(rtc_fast)] -fn function_in_rtc_ram() -> u32 { - 42 -} diff --git a/esp32c2-hal/examples/systimer.rs b/esp32c2-hal/examples/systimer.rs index a14245102..7cabbff6a 100644 --- a/esp32c2-hal/examples/systimer.rs +++ b/esp32c2-hal/examples/systimer.rs @@ -34,11 +34,11 @@ fn main() -> ! { let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks); let mut wdt = timer_group0.wdt; - // let mut rtc = Rtc::new(peripherals.RTC_CNTL); + let mut rtc = Rtc::new(peripherals.RTC_CNTL); // Disable MWDT and RWDT (Watchdog) flash boot protection wdt.disable(); - // rtc.rwdt.disable(); + rtc.rwdt.disable(); let syst = SystemTimer::new(peripherals.SYSTIMER); diff --git a/esp32c2-hal/ld/bl-esp32c2-memory.x b/esp32c2-hal/ld/bl-esp32c2-memory.x index ecd0444c6..bde044378 100644 --- a/esp32c2-hal/ld/bl-esp32c2-memory.x +++ b/esp32c2-hal/ld/bl-esp32c2-memory.x @@ -1,25 +1,21 @@ MEMORY { /* - NOTE: the ESP32-C2 inherits from the ESP32-C3 in esptool, and uses the same memory map - https://github.com/espressif/esptool/blob/ed64d20b051d05f3f522bacc6a786098b562d4b8/esptool/targets/esp32c3.py#L78-L90 + https://github.com/espressif/esptool/blob/10828527038d143e049790d330ac4de76ce987d6/esptool/targets/esp32c2.py#L53-L62 MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"], - [0x3C000000, 0x3C800000, "DROM"], - [0x3FC80000, 0x3FCE0000, "DRAM"], + [0x3C000000, 0x3C400000, "DROM"], + [0x3FCA0000, 0x3FCE0000, "DRAM"], [0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"], - [0x3FF00000, 0x3FF20000, "DROM_MASK"], - [0x40000000, 0x40060000, "IROM_MASK"], - [0x42000000, 0x42800000, "IROM"], - [0x4037C000, 0x403E0000, "IRAM"], - [0x50000000, 0x50002000, "RTC_IRAM"], - [0x50000000, 0x50002000, "RTC_DRAM"], - [0x600FE000, 0x60100000, "MEM_INTERNAL2"]] + [0x3FF00000, 0x3FF50000, "DROM_MASK"], + [0x40000000, 0x40090000, "IROM_MASK"], + [0x42000000, 0x42400000, "IROM"], + [0x4037C000, 0x403C0000, "IRAM"]] */ /* 272K of on soc RAM, 16K reserved for cache */ - ICACHE : ORIGIN = 0x4037C000, LENGTH = 0x4000 + ICACHE : ORIGIN = 0x4037C000, LENGTH = 16K /* Instruction RAM */ - IRAM : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 272K - 0x4000 + IRAM : ORIGIN = 0x4037C000 + 16K, LENGTH = 272K - 16K /* Data RAM */ DRAM : ORIGIN = 0x3FCA0000, LENGTH = 0x30000 diff --git a/esp32c2-hal/ld/db-esp32c2-memory.x b/esp32c2-hal/ld/db-esp32c2-memory.x index 6179017d8..4fec84658 100644 --- a/esp32c2-hal/ld/db-esp32c2-memory.x +++ b/esp32c2-hal/ld/db-esp32c2-memory.x @@ -1,25 +1,21 @@ MEMORY { /* - NOTE: the ESP32-C2 inherits from the ESP32-C3 in esptool, and uses the same memory map - https://github.com/espressif/esptool/blob/ed64d20b051d05f3f522bacc6a786098b562d4b8/esptool/targets/esp32c3.py#L78-L90 + https://github.com/espressif/esptool/blob/10828527038d143e049790d330ac4de76ce987d6/esptool/targets/esp32c2.py#L53-L62 MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"], - [0x3C000000, 0x3C800000, "DROM"], - [0x3FC80000, 0x3FCE0000, "DRAM"], + [0x3C000000, 0x3C400000, "DROM"], + [0x3FCA0000, 0x3FCE0000, "DRAM"], [0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"], - [0x3FF00000, 0x3FF20000, "DROM_MASK"], - [0x40000000, 0x40060000, "IROM_MASK"], - [0x42000000, 0x42800000, "IROM"], - [0x4037C000, 0x403E0000, "IRAM"], - [0x50000000, 0x50002000, "RTC_IRAM"], - [0x50000000, 0x50002000, "RTC_DRAM"], - [0x600FE000, 0x60100000, "MEM_INTERNAL2"]] + [0x3FF00000, 0x3FF50000, "DROM_MASK"], + [0x40000000, 0x40090000, "IROM_MASK"], + [0x42000000, 0x42400000, "IROM"], + [0x4037C000, 0x403C0000, "IRAM"]] */ /* 272K of on soc RAM, 16K reserved for cache */ - ICACHE : ORIGIN = 0x4037C000, LENGTH = 0x4000 + ICACHE : ORIGIN = 0x4037C000, LENGTH = 16K /* Instruction RAM */ - IRAM : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 272K - 0x4000 + IRAM : ORIGIN = 0x4037C000 + 16K, LENGTH = 272K - 16K /* Data RAM */ DRAM : ORIGIN = 0x3FCA0000, LENGTH = 0x30000