115 lines
3.0 KiB
Rust
115 lines
3.0 KiB
Rust
//! Delay driver
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//!
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//! Implement the `DelayMs` and `DelayUs` traits from [embedded-hal].
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//!
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//! [embedded-hal]: https://docs.rs/embedded-hal/latest/embedded_hal/
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use embedded_hal::blocking::delay::{DelayMs, DelayUs};
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pub use self::delay::Delay;
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impl<T> DelayMs<T> for Delay
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where
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T: Into<u32>,
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{
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fn delay_ms(&mut self, ms: T) {
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for _ in 0..ms.into() {
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self.delay_us(1000u32);
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}
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}
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}
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impl<T> DelayUs<T> for Delay
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where
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T: Into<u32>,
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{
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fn delay_us(&mut self, us: T) {
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self.delay(us.into());
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}
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}
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#[cfg(feature = "esp32c3")]
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mod delay {
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use crate::pac::SYSTIMER;
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// The counters and comparators are driven using `XTAL_CLK`. The average clock
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// frequency is fXTAL_CLK/2.5, which is 16 MHz. The timer counting is
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// incremented by 1/16 μs on each `CNT_CLK` cycle.
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const CLK_FREQ_HZ: u64 = 16_000_000;
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/// Delay driver
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///
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/// Uses the `SYSTIMER` peripheral for counting clock cycles, as
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/// unfortunately the ESP32-C3 does NOT implement the `mcycle` CSR, which is
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/// how we would normally do this.
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pub struct Delay {
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systimer: SYSTIMER,
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}
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impl Delay {
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/// Create a new Delay instance
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pub fn new(systimer: SYSTIMER) -> Self {
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Self { systimer }
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}
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/// Return the raw interface to the underlying SYSTIMER instance
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pub fn free(self) -> SYSTIMER {
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self.systimer
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}
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/// Delay for the specified number of microseconds
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pub fn delay(&self, us: u32) {
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let t0 = self.unit0_value();
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let clocks = (us as u64 * CLK_FREQ_HZ) / 1_000_000;
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while self.unit0_value().wrapping_sub(t0) <= clocks {}
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}
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#[inline(always)]
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fn unit0_value(&self) -> u64 {
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self.systimer
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.unit0_op
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.write(|w| w.timer_unit0_update().set_bit());
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while !self
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.systimer
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.unit0_op
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.read()
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.timer_unit0_value_valid()
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.bit_is_set()
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{}
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let value_lo = self.systimer.unit0_value_lo.read().bits();
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let value_hi = self.systimer.unit0_value_hi.read().bits();
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((value_hi as u64) << 32) | value_lo as u64
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}
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}
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}
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#[cfg(not(feature = "esp32c3"))]
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mod delay {
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// FIXME: The ESP32-S2 and ESP32-S3 have fixed crystal frequencies of 40MHz.
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// This will not always be the case when using the ESP32.
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const CLK_FREQ_HZ: u64 = 40_000_000;
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/// Delay driver
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///
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/// Uses the built-in Xtensa timer from the `xtensa_lx` crate.
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#[derive(Default)]
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pub struct Delay;
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impl Delay {
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/// Instantiate the `Delay` driver
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pub fn new() -> Self {
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Self
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}
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/// Delay for the specified number of microseconds
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pub fn delay(&self, us: u32) {
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let clocks = (us as u64 * CLK_FREQ_HZ) / 1_000_000;
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xtensa_lx::timer::delay(clocks as u32);
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}
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}
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}
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