17daa464ba
* Enable ESP32 HIL * RMT fixed * SPI DMA partially works, _pcnt tests not working * bckup * finish * readme and cleanup * rebase + cleanup * RMT S2 pin typo + clean forgotten comments * review comments * update 10000 * indentation * replace cfg gate with cfg_if
134 lines
3.7 KiB
Rust
134 lines
3.7 KiB
Rust
//! UART Test
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//!
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//! Folowing pins are used:
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//! TX GPIO2 / GPIO9 (esp32s2 / esp32s3) / GPIO26 (esp32)
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//! RX GPIO3 / GPIO10 (esp32s2 / esp32s3) / GPIO27 (esp32)
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//!
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//! Connect TX and RX pins.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use embedded_hal_02::serial::{Read, Write};
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use esp_hal::{
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gpio::Io,
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peripherals::UART1,
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prelude::*,
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uart::{ClockSource, Uart},
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Blocking,
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};
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use hil_test as _;
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use nb::block;
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struct Context {
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uart: Uart<'static, UART1, Blocking>,
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let (tx, rx) = hil_test::common_test_pins!(io);
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let uart = Uart::new(peripherals.UART1, tx, rx).unwrap();
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Context { uart }
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}
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#[test]
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#[timeout(3)]
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fn test_send_receive(mut ctx: Context) {
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ctx.uart.write(0x42).ok();
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let read = block!(ctx.uart.read());
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assert_eq!(read, Ok(0x42));
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}
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#[test]
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#[timeout(3)]
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fn test_send_receive_buffer(mut ctx: Context) {
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const BUF_SIZE: usize = 128; // UART_FIFO_SIZE
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let data = [13; BUF_SIZE];
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let written = ctx.uart.write_bytes(&data).unwrap();
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assert_eq!(written, BUF_SIZE);
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let mut buffer = [0; BUF_SIZE];
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let mut i = 0;
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while i < BUF_SIZE {
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match ctx.uart.read() {
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Ok(byte) => {
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buffer[i] = byte;
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i += 1;
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}
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Err(nb::Error::WouldBlock) => continue,
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Err(nb::Error::Other(_)) => panic!(),
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}
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}
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assert_eq!(data, buffer);
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}
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#[test]
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#[timeout(3)]
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fn test_send_receive_different_baud_rates_and_clock_sources(mut ctx: Context) {
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// The default baud rate for the UART is 115,200, so we will try to
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// send/receive with some other common baud rates to ensure this is
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// working as expected. We will also using different clock sources
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// while we're at it.
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#[cfg(not(feature = "esp32s2"))]
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{
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#[cfg(not(any(feature = "esp32", feature = "esp32c3", feature = "esp32c2")))]
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{
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// 9600 baud, RC FAST clock source:
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ctx.uart.change_baud(9600, ClockSource::RcFast);
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ctx.uart.write(7).ok();
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let read = block!(ctx.uart.read());
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assert_eq!(read, Ok(7));
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}
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// 19,200 baud, XTAL clock source:
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#[cfg(not(feature = "esp32"))]
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{
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ctx.uart.change_baud(19_200, ClockSource::Xtal);
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ctx.uart.write(55).ok();
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let read = block!(ctx.uart.read());
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assert_eq!(read, Ok(55));
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}
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// 921,600 baud, APB clock source:
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ctx.uart.change_baud(921_600, ClockSource::Apb);
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ctx.uart.write(253).ok();
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let read = block!(ctx.uart.read());
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assert_eq!(read, Ok(253));
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}
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#[cfg(feature = "esp32s2")]
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{
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// 9600 baud, REF TICK clock source:
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ctx.uart.change_baud(9600, ClockSource::RefTick);
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ctx.uart.write(7).ok();
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let read = block!(ctx.uart.read());
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assert_eq!(read, Ok(7));
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// 921,600 baud, APB clock source:
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ctx.uart.change_baud(921_600, ClockSource::Apb);
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ctx.uart.write(253).ok();
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let read = block!(ctx.uart.read());
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assert_eq!(read, Ok(253));
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}
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}
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}
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