* make pins optional for Spi::new (master, full-duplex mode)
* add additional method to setup spi pins (master, full-duplex mode)
* add additional method to setup spi pins (master, half-duplex mode)
* remove generic type parameters for Spi::new
* update documentation
* make `with_pins` could be chained
* update CHANGELOG.md
* update CHANGELOG.md
* make the return value of a method like `with_{*}` owned
* fix (maybe?) all broken examples caused by the change (esp32-hal)
* fix (maybe?) all broken examples caused by the change (esp32c2-hal)
* fix (maybe?) all broken examples caused by the change (esp32c3-hal)
* fix (maybe?) all broken examples caused by the change (esp32c6-hal)
* fix (maybe?) all broken examples caused by the change (esp32h2-hal)
* fix (maybe?) all broken examples caused by the change (esp32s2-hal)
* fix (maybe?) all broken examples caused by the change (esp32s3-hal)
* rerun 'cargo fmt' for esp-hal-common
* rerun 'cargo fmt' for the rest of examples
* Temporarily disable async `SYSTIMER` implementation, remove mention from `CHANGELOG.md`
* Remove a couple files which are not required
* Fix warning for `sha` examples
* Fix warning for non-C3 devices
* s/interrupt_clear/clear_interrupt/
* Provide ADC values in mV instead of requiring the user to scale them
* Changelog
* Try converting poly calibration also
* Update changelog and comments
* Fix example
* Fix Async UART
The uart handler was `writing` to the enable register instead of
`modify`, which meant any wake would see the cleared enabled bit and
think the event had occurred. This wasn't seen before the split of uart
because it was only possible to listen to one thing at a time.
This PR also removes the ReadBufferFull error in favour of returning the
max bytes in the buffer.
The serial examples has been updated to actually have some cross task
communication.
* changelog
* fix dev deps
* Move SPI-related traits into their own preludes in the `spi` module
* Remove the `embedded-hal-async` trait re-exports and the `eh1` module from the prelude
* Update `CHANGELOG.md`
* Remove duplicated `analog` modules, which are not necessary
* Merge the `SarAdcExt` and `SensExt` traits into a single `AnalogExt` trait
* Clean up/simplify the analog module a bit
* Update `CHANGELOG.md`
* Refactor the `spi` and `spi_slave` modules into a single `spi` module
* Update import paths in examples as needed
* Extract some common types from `spi::master` into the root `spi` module
* Fix imports in examples (again)
* Documentation fixes/improvements
* Remove unnecessary re-exports
* Update `CHANGELOG.md`
* Duplicate spi to spi_slave
* Restore spi
* Add barebones SPI slave mode, DMA only.
This setup allows registering buffers for future transactions the master
does (lowering cs, toggling sclk, and raising cs again). The transfer
struct returned from the registration API will complete its wait() or
return true from is_done() after cs has been raised.
Copied from spi.rs, so most of the changes are deleting code that
handles e.g. segmented transfers or synchronous operations.
Fix non-c3 devices' builds
* Limit spi_slave to non-pdma devices
* SPI slave DMA example
Ensure the API "feels" right.
Since there's no way to route GPIOs to other peripherals, we choose four
other wires and bit-bang SPI for the master side, relying on the person
running the example to connect the bus. This way we ensure the slave
code works, since we created the master ourselves.
Also, it's not really possible to use a second ESP device as the master
anyway: all the digital lines have glitches on startup, and those
glitches cause the slave's DMA engine to skip descriptors (it thinks
they're intended CS indicators); this causes it to lose data.
Then, fix the bitbang master (recording the progression here)
- When bitbanging, iterate the bits by "for _ in 0..8", instead of the
broken "for _ in [0..8]". The latter only runs the iteration once,
since there's only one list given ... and because the code uses _
instead of a real loop variable, type checking didn't save us.
- When bitbanging, send the bits out (and read them in) MSB first, since
that's actually how we have the slave configured.
* Add changelog entry
* Split DMA prepare_transfer into two fns.
The first does everything but write to the start bit and check for an
error. The second does those. We need 2 fns because the SPI slave needs
to start the transfer only after resetting the various afifo hardware
components (if it starts the transfer before, the first 8 bytes will be
lost when that reset happens).
Use the split fns everywhere.
Also split flush(). It needs to be pollable, so split it into one fn that
polls and one that waits until the poll returns clear. Also call the poll
fn from the is_done() fn, so we don't trample in-progress transfers.
* Make example code fill rx buffer before transfer
This way we can tell if it's ever touching certain bytes - 0xff is never
added to the master transmit buffer.
While I'm changing this, make the slave tx buffer never contain 0xff
either (go from 254 to 0).
---------
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Make sure examples can build with defmt
* Remove duplicate example checks
* Fix examples
* Add changelog entry
* Actually build some examples with defmt feature enabled
* Add the defmt linker script in each package's build script
* Unify the system peripheral
Whilst the PCR, SYSTEM and DPORT peripherals are different, we currently
use them all in the same way. This PR unifies the peripheral name in the
hal to `SYSTEM`. The idea is that they all do the same sort of thing, so
we can collect them under the same name, and later down the line we can
being to expose differences under an extended API.
The benifits to this are imo quite big, the examples now are all identical,
which makes things easier for esp-wifi, and paves a path towards the
multichip hal.
Why not do this in the PAC? Imo the pac should be as close to the
hardware as possible, and the HAL is where we should abstractions such
as this.
* changelog
* Make the example work
* Make GPIO wakeups work
* Add example
* revert hello_rgb change
* Clean up the first hacky version
* Fix example warnings
* Add changelog entry
* Fix example comment
* Stop skipping rustfmt
* Unify the xtal frequency features for ESP32 and ESP32-C2
* Group and re-organize features for `esp-hal-common`
* Update `esp-hal-smartled` and fix its CI check
* Update `CHANGELOG.md`
* Update feature names in documentation
* Adding async support for RSA peripheral
* Add esp32 support (doesn't work properly yet)
* Xtensa chips are supported (except of esp32)
Add modular multiplication for esp32
Adding a CHANGELOG entry
Rebase issue fix
* Code cleanup
* Add `.await` on `RsaFuture::new()` calls
* Refactor and rebase
Made `read_results` functions to be `async`, got rid of `nb` usage
* Change API methods naming + refactor `start_step2` method
* Adjust example to the API change + documentation
* Code cleaning + refactoring
Update examples
* No longer publicly expose the `PeripheralClockControl` struct
* Update examples as needed to get things building again
* Update CHANGELOG.md
* Address review feedback, fix a warning
* Use a critical section for all devices other than the ESP32-C6/H2, as they modify multiple registers
* Rebase and update `etm` driver to fix build errors
* Make ADC reads return u16s, not generic types
* Changelog entry
* Add the PR number to the changelog
---------
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Ensure that uart is configured to account for clock changes, not just boot defaults
* fix examples
* changelog
---------
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Add support for splitting esp32 uart into TX and RX
* Keeps existing API for uart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to embassy-rs nRF/stm32/rp for getting indepdendent TX and RX
parts
* Implements e-h traits for TX and RX types
* Add esp32s3 example
* finish implementing
* rebase examples
* declare new examples
* fix fmt
* rebase on 0.12.0
* fix fmt
* fix fmt
* merge embassy_serial_split example with embassy_serial
* fix changelog
* fix changelog
* Add ECC driver for ESP32C2 and ESP32C6
* Add ECC example for ESP32C2 and ESP32C6
* Add and modify dependencies
* ESP32H2: Add ECC driver support
* ESP32H2: Add ECC example
* ESP32C2 and ESP32C6: clean examples
* changelog
* refactor: remove enable_interrupt() and clear_interrupt()
* refactor: remove ugly if/else logic for padding
* Bump MSRV to 1.67, check with `defmt` feature enabled in MSRV checks where applicable
* Add `esp32c6-lp-hal-procmacros` package to VS Code workspace
* Update `CHANGELOG.md`
* Macro to load LP core code
* Fix imports, add CHANGELOG.md entry
* Avoid code warning
* Omit path from function signature
* More error checking
* Clippy fix
* Include the ELF used by the lp_core_basic example
* Make object dependency optional
* Use 1.65 for RISCV MSRV check
* Use RUSTC_BOOTSTRAP for RISCV MSRV check
* Remove the pre-compiled LP core example
* Pin toml_edit in esp32c6-lp-hal-procmacro
* Executor related touchups
* Make log optional
* Add defmt feature and derive on Debug structs
* Test both log drivers
* Update esp-println
* Document defmt msrv
* Rework watchdog timer drivers to allow enabling/disabling and feeding without traits
* Disable all watchdogs prior to `main` using the `__post_init` hook
* Update all watchdog-related examples
* Update CHANGELOG
* Address review comment
* Update a bunch of dependencies
* Implement `embedded-io` and `embedded-io-async` traits for USB Serial JTAG
* Implement `embedded-io` and `embedded-io-async` traits for UART
* Fix `embassy_serial` examples
* Update CHANGELOG
* Address review comments
* Use all remaining memory for stack(s)
* Remove HEAP related code from RISCV linker scripts
* Fix direct-boot / mcu-boot linker scripts
* Use a statically allocated stack for core-1
