3 Commits

Author	SHA1	Message	Date
Sergio Gasquez Arcos	b5f0246129	Reordered RX-TX pairs to be consistent (#2074) ... * feat: Update rx-tx order in i2s * feat: Update rx-tx order in dma macros * feat: Update rx-tx order in spi * feat: Update rx-tx order in aes * feat: Update rx-tx order in mem2mem * feat: Update rx-tx order in twai and split methods * feat: Update rx-tx order in twai * feat: Update rx-tx order in twai and uart docs * docs: Add sentence about order * docs: Update changelog * feat: Update rx-tx order in embassy_interrupt_spi_dma tests * style: Rustfmt * docs: Migrating guide * fix: Typo Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Diff Co-authored-by: Dániel Buga <bugadani@gmail.com> * fix: Tests rx-tx order * fix: Update new_with_default_pins order * feat: Update rx/tx order in hil_test::common_test_pins! * feat: Update dma_extmem2mem example * fix: Revert deleted input arg * style: rustfmt * feat: Disable test_asymmetric_dma_transfer for S2 --------- Co-authored-by: Dániel Buga <bugadani@gmail.com>	2024-09-06 09:56:10 +00:00
Dániel Buga	ec130877b7	Disable RTT polling in HIL tests by default (#1960) ... * Disable defmt-rtt by default * Update i2s test based on changes done to async * fmt * Update readme * Update more tests	2024-08-19 13:47:22 +00:00
liebman	1631f22083	support dma chunk sizes other than 4092 (#1758) ... * support dma chunk sizes other than 4092 * fmt * update CHANGELOG * fix 0 size static assert * review changes: - `.div_ceil()` - return errors for bad chunk size and buffer sizes in Mem2Mem constructors - correct 0 chunk size check in descripter macros * dma: clear the mem2mem bit when channel is configured instead of in Drop	2024-07-15 12:00:33 +00:00