* esp32 & esp32s2 sharing scripts
* add wokwi files
* Add fixup section for esp32s2, fix ordering of sectino includes
* Remove debug asm file
* Use shared linker scripts for s3 with fixups
* Add external.x sections back
* Move ld scripts into esp-hal-common
* esp32c3 unified linker scripts
- rework original c3 script to use the xtensa named sections
(e.g, _SECTIONNAME_start)
- Add fixups in esp32c3 specific linker
- Remove useless text section start and end (not required when using any
form of bootloader)
* Add RTC alias'. Move some shared fixups to a file
* comment and cleanup
* unify c2 linker script
* unify c6 linker script
* remove debug configs
* use new esp-riscv-rt
* fmt
* align db symbol names
* fix s3 db
* Add additional `cfg` gates to re-exports in `esp-hal-common`
This leaves only `clock`, `delay`, `peripheral`, `prelude`, `rom`, and `soc` *not* behind `cfg`s
* Simplify the prelude, update its `cfg`s, and re-export some missing traits
* Update various dependencies
* Extract the `esp-hal-smartled` package
This (finally) eliminates the `esp_hal_common::utils` module!
* Remove all references to the old `smartled` feature from CI
* RISCV: Separate PLIC and non-PLIC
* De-duplicate code
* Write 0 to INTR_MAP again to disable peripheral interrupts
* Limit visibility of `get_assigned_cpu_interrupt`
* Move some linker scripts into `esp-hal-common` and update the build script
* Move `EspDefaultHandler` and `DefaultHandler` definitions into `esp-hal-common`
* Re-export everything from `esp-hal-common`
* Add a couple cfg symbols, cleanup/organize some exports/modules
* Create an `soc` module with a submodule for each chip, move `peripherals` in
* Move the `cpu_control` module into `soc`
* Move the `efuse` module into `soc`
* Refactor type definitions from `gpio` module into `soc`
* Put all embassy-related files in a common directory
* Change visibility of `GpioPin` constructor
* Create the `esp32c6-hal` package
* Teach `esp-hal-common` about the ESP32-C6
* Get a number of peripheral drivers building for the ESP32-C6
bckup
initial clocks_ii
* Create the `esp32c6-hal` package
C6: update
* Simplify and fix the linker script
update
* C6: add I2S
* Create the `esp32c6-hal` package
* Teach `esp-hal-common` about the ESP32-C6
* Get a number of peripheral drivers building for the ESP32-C6
bckup
initial clocks_ii
* Create the `esp32c6-hal` package
* C6: update
* Simplify and fix the linker script
* update
* C6: add I2S
* update
* C6 Interrupts
* C6: Update build.rs, linker scripts and initial examples
* C6: RMT
* Fix interrupt handling
* Fix `ClockControl::configure`
* C6: revert to I2S0 instead of just I2S
* C6: rebase and update
* RTC not buildable
* Implement RWDT and SWD disable
* C6: working LEDC
* C6: working RMT
* C6: add aes
* C6: add mcpwm
* C6: add rtc_cntln - not finished
* C6: update and formatting
* C6: add pcnt
* C6: add examples and format
* Remove inline assembly, fix interrupts and linker scripts
* Remove unused features, update cargo config for atomic emu, misc cleanup
* Get ADC building and example "working" (as much as it ever does)
* Remove a bunch of unused constants which were copied from ESP-IDF
* The `mcpwm` example now works correctly
* Get `TWAI` peripheral driver building for C6
* Clean up the `rtc_cntl` module and get all the other HALs building again
* Add the C6 to our CI workflow
* Fix various things that have been missed when rebasing
Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`)
* C6: Small updates in wdt (#1)
* C6: Update WDT
* C6: Update examples with WDT update
* Update `esp-println` dependency to fix build errors
* Fix formatting issues causing pre-commit hook to fail
* Get some more examples working
* Working `ram` example
* Sync with changes in `main` after rebasing
* Working `embassy_spi` example
* Use a git dependency for the PAC until we publish a release
* Fix I2S for ESP32-C6
* Fix esp32c6 direct boot (#4)
* Add direct boot support for C6
* Fix direct boot for c6
- Actually copy into rtc ram
- remove dummy section that is no longer needed (was just a waste of
flash space)
- Move RTC stuff before the no load sections
* Update RWDT and refactor RTC (#3)
* C6: Update RWDT and add example, refactor RTC and add not-really-good example
* Update based on review comments, resolve bunch of warnings and run cargo fmt
* Update C6 esp-pacs rev commit
* Fix clocks_ll/esp32c6.rs
* Fix riscv interrupts
* Remove clock_monitor example for now
* RAM example works in direct-boot mode
* Add a TODO for &mut TIMG0 and cargo fmt
* Fix linker script after a bad rebase
* Update CI and Cargo.toml embassy required features
* use riscv32imac-unknown-none-elf target for C6 in CI
* change default target to riscv32imac-unknown-none-elf
* add riscv32imac-unknown-none-elf target to MSRV job
* another cleanup
---------
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Jesse Braham <jesse@beta7.io>
* Make required changes to include new `RADIO` peripheral
* Use published versions of PAC and `esp-println`
* Use the correct target extensions (`imac`)
* Fix the super watchdog timer, plus a few more examples
* Fix UART clock configuration
* Make sure to sync UART registers when configuring AT cmd detection
* Disable APM in direct-boot mode
* Address a number of review comments
* Fix `SPI` clocks and `rtc_watchdog` example (#6)
* fix SPI clocks
* run cargo fmt
* Add comment about used default clk src
* Fix rtc_watchdog example in BL mode
* run cargo fmt
* Update rtc_watchdog example that it works in DB mode
* README and example fixes/cleanup
* Add I2C peripheral enable and reset
* Fix `ApbSarAdc` configuration in `system.rs`
---------
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Allow the creation of peripherals _not_ from the pac in the peripherals macro
* Add RADIO peripheral
- Remove DerefMut hack, replace with proper Sealed impls
- Add RADIO peripheral for all chips
* Add RADIO peripheral with split method into each radio feature
* ground work for async dma (gdma only atm)
* Add async DMA (GDMA) - esp32c3/esp32c2
* Add Async SPI impl for esp32c3/c2
* Remove private modules from DMA
* add async spi example for esp32c3
* Switch to assoc wakers instead of a static array
* add support for esp32/esp32s2
* add support for esp32s3
* run fmt
* add c2 example, fix CI
* Remove redundant comments
* Update PACs and modify `esp-hal-common` to use new `esp-riscv-rt` package
* Update `esp32c2-hal` and `esp32c3-hal` to use `esp-riscv-rt` as well
* Update all RISC-V examples to use `esp-riscv-rt`
* Update RISC-V trap frame handling according to review feedback
* Add `is_listening` to `Pin` trait
* Add `Wait` impl for Gpio Input
* Add GPIO wait example for C3
* Ensure correct bank is accessed in interrupt
* Add esp32c2 wait example
* Add esp32s3 wait example
* Add esp32s2 wait example
* Add esp32 wait example
* Run fmt
* Add example to cargo tomls
* Add top level docs for embassy examples
* Mention the higher MSRV for async in the README
---------
Co-authored-by: Jesse Braham <jesse@beta7.io>
* Refactor `clock` and `clocks_ll` into a common module
* Add a ROM function linker script to each HAL and provide some functions
* Use the provided ROM functions instead of transmuting addresses
* Fix CI workflow for ESP32-S2
* Refactor the `rtc` and `rtc_cntl` modules into a common `rtc_cntl` module
* Implement the `get_reset_reason` and add `SocResetReason` enum for each chip
* Update `riscv`, `riscv-rt` dependencies, plus PACs for RISC-V chips
* Update `riscv-atomic-emulation-trap` package
* Update the `embassy-executor` dev dependency to a newer version
* start of pulse counter implementation
* implement interrupts
implement pcnt for esp32, esp32s2, and esp32s3
* implement pcnt for esp32s2
* fix esp32 PCNT signal names
* update PCNT register/fields for cleaned up PAC
* implement events/get_events (choosing what events interrupt)
* added pcnt example: simple encoder configuration
* restrict pcnt::channel::Channel::new() to super
* PcntPin -> PcntSignal
added range checks for thresholds and limits
* PcntSource is a better name I think
* handle error for PCNT Unit configure() in example
* update pac versions for status register change
* cargo fmt
* cargo fmt (examples)
* PcntSource now only stores the source id.
add a critical section to protect the ctrl & isr_en registers
* cargo fmt
* wip: initial implementation of transmission only.
* Moved TWAI to its own directory and added initial reception of packets.
* Added extended id transmit and receive.
* Added maybe better code for making packet filters.
* Fixed bug with ids and improved methods of copying data to the peripheral.
* Added some guards against Bus Off
* Added reception of remote frames.
* Clean up of comments, etc
* Updated TWAI naming and cleaned up example a bit.
* Updated bitselector to include better unpacking methods.
* Add embedded-can and limit initial TWAI implementation to esp32c3.
* Added embedded-can to esp32c3 twai example.
* Switched twai filter to using bytestrings.
Co-authored-by: dimi <dimi.polonski@gmail.com>
* Implemented new() for twai filters.
* Clean up TWAI docs and example.
* Fix filter constructors and add examples.
* pre driver PeripheralRef update.
* PeripheralRef/twai
* Format comments with nightly rustfmt.
* Add gpio PeripheralRef and use volatile for direct register access.
Co-authored-by: dimi <dimi.polonski@gmail.com>
* Peripheral ref/sha (#312)
* Add SHA to list of peripherals to be created
* Refactor SHA peripheral to use PeripheralRef
* Update SHA examples to get them building again
* Fix async time drivers
* Fix usb otg
* Fix s3
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Add RNG to list of peripherals to be created
* Refactor RNG driver to use PeripheralRef
Co-authored-by: Jesse Braham <jessebraham@users.noreply.github.com>
* Add the peripheral module plus some helper macros in preparation
* peripheral macro
* Add peripheral generation macro
* Fixes after rebase
* Update the signature of Peripherals::take
* syncronise hello world example
* fmt the entire repo
Co-authored-by: Jesse Braham <jesse@beta7.io>
- Rename timg feature to timg0 to better refect which TG is being used
- Use the time_driver::TimerType in the signature of init to fix#268
- Update examples
- Fix CI features
- Add timg0 cfg to build.rs
* Add untested basic SHA for esp-sX/cX chips
* Fix ptr type inconsistency for S2
* Add ESP32 impl & fix process_buffer latch issue
* Add debug example for SHA accelerator
* Clean up no-op buffer prints
* Test vector parity (on esp32s3)
* Checkpoint for converting to alignment helper
* Finish refactoring & additional parity tests on esp32s3
* Remove core_intrinsics requirement for now
* Fix case where (src.len() % 4) == 3
* Finish sha2 example with performance comparison (12-61x speedup)
* Refactor ESP32 to alignment helper & Clean up example
* Prevent out-of-bounds reads in ESP32 version
* Revert Cargo debug changes
* Remove cargo config.toml
* Clean up example
* Remove common/rust-toolchain & ignore in future
* Might as well use actual size_of const
* Remove SHA512/SHA384 for C2/C3
* Directly import nb::block! to remove unused import warning & fix c2 feature detect
* Remove stray newlines
* Fix esp32c2 having SHA256
* ESP32 also has SHA384
* Remove comments that don't have a purpose
* Clean up example & finish() handling
* Add examples & add ESP32 free()
* Update C2/C3 examples to show accurate algorithm used
* Fix busy check for ESP32
* Remove outdated TODO comment
* Update PAC for ESP3 and (actually) fix busy check
* Refactor ESP32 version to reduce search space
* Add debug printlns to sha example & clean up comments
* Fix ESP32 version, finally
Co-authored-by: ferris <ferris@devdroplets.com>
Co-authored-by: Jesse Braham <jesse@beta7.io>
* wip: timg embassy driver
- read_raw on timg renamed to now()
- timg initialized and stored in static for use in the embassy driver
- timg sets alarm value
- untested whether alarms actually trigger
* TIMG timer driver for esp32, esp32s3
- Adds the timg timer block as a time driver for embassy
- Not enabled on the C3 as it only has one timer block, better to use
systimer
- s2 example added but can't build due to atomic requirements in
futures-core
* Add S2 atomic support with emulation, fixup embassy support for the S2
* Move executor & static-cell to dev deps. Make eha optional
* Add c2 support, run fmt
* Update to crates.io embassy releases
* Update eha
* update timg time driver to new trait
* Remove exception feature of esp-backtrace and use the user handler for backtracing
* Add async testing workflow
* Update systick example
* Fix S2 examples
* Update xtensa-toolchain
* set rustflags for s2 target
* Disable systick for esp32s2 until we can fix the noted issues
* review improvements
- Fix intr prio array being off by one
- emabssy time prio interrupt set to max prio
- use cfg instead of feature for systick detection
* Update example time delays
to create a new `SpiBusDevice` instead of directly instantiating the
struct. `SpiBusDevice::new` takes care of setting up the CS line to be a
default-high output, too, which the raw struct doesn't.
Add a feature for the ESP32-C2 to`esp-hal-common` and update some `cfg`s
Organize the `esp-hal-common` imports and exports and update to include the ESP32-C2
Removes a lot of generic arguments and hard-codes the `SpiBusController`
and `SpiBusDevice` to work with the `Spi<T>` defined in the HAL instead.
This allows us to access the `cs_signal()` trait function from `T:
Instance`, which we need to connect/disconnect the CS I/O as
appropriate.
