* Small refactor to extract functions for setting up reads/writes
* Implement async capabilities for `I2C` driver
* Add async I2C examples for each supported chip
* Update CHANGELOG
* Initial async_{write|flush} implementations
- ESP32C3 + UART0 example
* Support UART1 & UART2
* Add examples for all chips
* reduce number of wakers depending on uart count
* Software interrupt support added, not sure if the code is good
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for remaining SW interrupts
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* Added support for esp32c2, esp32s2, esp32s3
* Software interrupt example for esp32c3
* prio based preemption only, vector table reverted
* prio based preemption only, vector table reverted
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* fixed rare bug causing misaligned memory access when emulating atomics
* fixed a rare bug causing misaligned memory accesses
* fixed a rare bug causing misaligned memory accesses
* broke something
* broke something
* fixed alignment bug
* Tentative: added support for interrupt preemption without involving the rt
* Added feature enabling priority based interrupt preemption
* Fixed failed merge
* Tagged preemption helpers with inline always
* Disable interrupts before restoring context to avoid ruining it
* Fix max priority edge case
* Fix broken merge
* Added examples for the remaining RISC-V ESPs
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp32c2-hal/examples/interrupt_preemption.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: sethp <seth.pellegrino@gmail.com>
* Example comments courtesy of @sethp
* Reverted irrelevant changes, raised high prio interrupt to max prio
* Rolling back an irrelevant change
* Rolling back an irrelevant change
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update esp-hal-common/src/interrupt/riscv.rs
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Moved imports to avoid warnings, moved functions to ram, moved interrupt disable to before prio threshold is restored
* Added preemption for the ESP32C6
* Moved helper functions into the relevant modules, changed threshold for ESP32C6 to machine mode one
* ESP32C6 Threshold register changed to machine mode one, corrected threshold set.
---------
Co-authored-by: sethp <seth.pellegrino@gmail.com>
Co-authored-by: Scott Mabin <scott@mabez.dev>
* Update `embedded-hal-1` and `embedded-hal-nb` dependencies to latest versions
* Update the `Delay` and `I2c` trait implementations
* Update the `SpiDevice` trait, implement `SpiDeviceRead` and `SpiDeviceWrite`
* Add additional `cfg` gates to re-exports in `esp-hal-common`
This leaves only `clock`, `delay`, `peripheral`, `prelude`, `rom`, and `soc` *not* behind `cfg`s
* Simplify the prelude, update its `cfg`s, and re-export some missing traits
* Update various dependencies
* ground work for async dma (gdma only atm)
* Add async DMA (GDMA) - esp32c3/esp32c2
* Add Async SPI impl for esp32c3/c2
* Remove private modules from DMA
* add async spi example for esp32c3
* Switch to assoc wakers instead of a static array
* add support for esp32/esp32s2
* add support for esp32s3
* run fmt
* add c2 example, fix CI
* Remove redundant comments
* Update PACs and modify `esp-hal-common` to use new `esp-riscv-rt` package
* Update `esp32c2-hal` and `esp32c3-hal` to use `esp-riscv-rt` as well
* Update all RISC-V examples to use `esp-riscv-rt`
* Update RISC-V trap frame handling according to review feedback
* Add `is_listening` to `Pin` trait
* Add `Wait` impl for Gpio Input
* Add GPIO wait example for C3
* Ensure correct bank is accessed in interrupt
* Add esp32c2 wait example
* Add esp32s3 wait example
* Add esp32s2 wait example
* Add esp32 wait example
* Run fmt
* Add example to cargo tomls
* Add top level docs for embassy examples
* Mention the higher MSRV for async in the README
---------
Co-authored-by: Jesse Braham <jesse@beta7.io>
* Update `riscv`, `riscv-rt` dependencies, plus PACs for RISC-V chips
* Update `riscv-atomic-emulation-trap` package
* Update the `embassy-executor` dev dependency to a newer version
- Rename timg feature to timg0 to better refect which TG is being used
- Use the time_driver::TimerType in the signature of init to fix#268
- Update examples
- Fix CI features
- Add timg0 cfg to build.rs
* Add untested basic SHA for esp-sX/cX chips
* Fix ptr type inconsistency for S2
* Add ESP32 impl & fix process_buffer latch issue
* Add debug example for SHA accelerator
* Clean up no-op buffer prints
* Test vector parity (on esp32s3)
* Checkpoint for converting to alignment helper
* Finish refactoring & additional parity tests on esp32s3
* Remove core_intrinsics requirement for now
* Fix case where (src.len() % 4) == 3
* Finish sha2 example with performance comparison (12-61x speedup)
* Refactor ESP32 to alignment helper & Clean up example
* Prevent out-of-bounds reads in ESP32 version
* Revert Cargo debug changes
* Remove cargo config.toml
* Clean up example
* Remove common/rust-toolchain & ignore in future
* Might as well use actual size_of const
* Remove SHA512/SHA384 for C2/C3
* Directly import nb::block! to remove unused import warning & fix c2 feature detect
* Remove stray newlines
* Fix esp32c2 having SHA256
* ESP32 also has SHA384
* Remove comments that don't have a purpose
* Clean up example & finish() handling
* Add examples & add ESP32 free()
* Update C2/C3 examples to show accurate algorithm used
* Fix busy check for ESP32
* Remove outdated TODO comment
* Update PAC for ESP3 and (actually) fix busy check
* Refactor ESP32 version to reduce search space
* Add debug printlns to sha example & clean up comments
* Fix ESP32 version, finally
Co-authored-by: ferris <ferris@devdroplets.com>
Co-authored-by: Jesse Braham <jesse@beta7.io>
* wip: timg embassy driver
- read_raw on timg renamed to now()
- timg initialized and stored in static for use in the embassy driver
- timg sets alarm value
- untested whether alarms actually trigger
* TIMG timer driver for esp32, esp32s3
- Adds the timg timer block as a time driver for embassy
- Not enabled on the C3 as it only has one timer block, better to use
systimer
- s2 example added but can't build due to atomic requirements in
futures-core
* Add S2 atomic support with emulation, fixup embassy support for the S2
* Move executor & static-cell to dev deps. Make eha optional
* Add c2 support, run fmt
* Update to crates.io embassy releases
* Update eha
* update timg time driver to new trait
* Remove exception feature of esp-backtrace and use the user handler for backtracing
* Add async testing workflow
* Update systick example
* Fix S2 examples
* Update xtensa-toolchain
* set rustflags for s2 target
* Disable systick for esp32s2 until we can fix the noted issues
* review improvements
- Fix intr prio array being off by one
- emabssy time prio interrupt set to max prio
- use cfg instead of feature for systick detection
* Update example time delays
Add a feature for the ESP32-C2 to`esp-hal-common` and update some `cfg`s
Organize the `esp-hal-common` imports and exports and update to include the ESP32-C2
