* wip: timg embassy driver
- read_raw on timg renamed to now()
- timg initialized and stored in static for use in the embassy driver
- timg sets alarm value
- untested whether alarms actually trigger
* TIMG timer driver for esp32, esp32s3
- Adds the timg timer block as a time driver for embassy
- Not enabled on the C3 as it only has one timer block, better to use
systimer
- s2 example added but can't build due to atomic requirements in
futures-core
* Add S2 atomic support with emulation, fixup embassy support for the S2
* Move executor & static-cell to dev deps. Make eha optional
* Add c2 support, run fmt
* Update to crates.io embassy releases
* Update eha
* update timg time driver to new trait
* Remove exception feature of esp-backtrace and use the user handler for backtracing
* Add async testing workflow
* Update systick example
* Fix S2 examples
* Update xtensa-toolchain
* set rustflags for s2 target
* Disable systick for esp32s2 until we can fix the noted issues
* review improvements
- Fix intr prio array being off by one
- emabssy time prio interrupt set to max prio
- use cfg instead of feature for systick detection
* Update example time delays
* Update the build script to inject a configuration value for the enabled chip
* Update all cfg gates to use the new symbols instead of the chip features
* Inject architecture and core count symbols as well, update as needed
* Organize the imports and exports of `esp-hal-common`
Instead of building a table of _all_ configured interrupts,
we now only check the currently _pending_ interrupts configuration
status. This means in the best case scenario we only ever do _one_
lookup instead of the 60~ we did before.
Tested on esp32c3, gpio_interrupt:
Before: 850cycles from `handler_interrupts` to the actual handler
After: 125cycles
* RISCV interrupt vectoring
- Adds support for vectoring peripheral interrupts to PAC handlers
- Currently supports level interrupts with priorities from 1-15
- Updated the gpio interrupt example to reflect the new changes
* remove .vscode files
* Support vectored edge interrupts
This is as simple as making sure we clear the CPU interrupt whenever we
receive one. This also documents further what APIs are safe to call when
the `vectored` feature is enabled.
* fix all examples to use vectoring
* doc & cleanup
* run handlers from ram
* make xtensa::interrupt::vectored private, we rexport public items
* fix default handlers
* pass interrupt into EspDefaultHandler
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
