Optionally pass interrupt context to handlers for Xtensa

esp-hal-common/Cargo.toml

@@ -25,6 +25,9 @@ riscv-atomic-emulation-trap = { version = "0.1", optional = true }
 # Xtensa
 xtensa-lx = { version = "0.6", optional = true }
 
+# Xtensa Runtime
+xtensa-lx-rt = { version = "0.10.0", optional = true }
+
 # Part of `ufmt` containing only `uWrite` trait
 ufmt-write = { version = "0.1", optional = true }
 
@@ -38,10 +41,10 @@ esp32s2_pac = { package = "esp32s2", git = "https://github.com/esp-rs/esp-pacs.g
 esp32s3_pac = { package = "esp32s3", git = "https://github.com/esp-rs/esp-pacs.git", branch = "with_source", optional = true }
 
 [features]
-esp32   = [  "esp32_pac/rt", "xtensa",   "dual_core"]
+esp32   = [  "esp32_pac/rt", "xtensa",   "dual_core", "xtensa-lx-rt/esp32"]
 esp32c3 = ["esp32c3_pac/rt", "risc_v", "single_core"]
-esp32s2 = ["esp32s2_pac/rt", "xtensa", "single_core"]
-esp32s3 = ["esp32s3_pac/rt", "xtensa",   "dual_core"]
+esp32s2 = ["esp32s2_pac/rt", "xtensa", "single_core", "xtensa-lx-rt/esp32s2"]
+esp32s3 = ["esp32s3_pac/rt", "xtensa",   "dual_core", "xtensa-lx-rt/esp32s3"]
 
 # Architecture (should not be enabled directly, but instead by a PAC's feature)
 risc_v = ["riscv", "riscv-atomic-emulation-trap"]

esp-hal-common/src/interrupt/xtensa.rs

@@ -1,13 +1,14 @@
 use crate::{pac::Interrupt, Cpu};
+use xtensa_lx_rt::exception::Context;
 
 extern "C" {
-    fn level1_interrupt();
-    fn level2_interrupt();
-    fn level3_interrupt();
-    fn level4_interrupt();
-    fn level5_interrupt();
-    fn level6_interrupt();
-    fn level7_interrupt();
+    fn level1_interrupt(save_frame: &mut Context);
+    fn level2_interrupt(save_frame: &mut Context);
+    fn level3_interrupt(save_frame: &mut Context);
+    fn level4_interrupt(save_frame: &mut Context);
+    fn level5_interrupt(save_frame: &mut Context);
+    fn level6_interrupt(save_frame: &mut Context);
+    fn level7_interrupt(save_frame: &mut Context);
 }
 
 /// Enumeration of available CPU interrupts
@@ -174,42 +175,42 @@ unsafe fn core1_interrupt_peripheral() -> *const crate::pac::interrupt_core1::Re
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_1_interrupt() {
-    unsafe { level1_interrupt() };
+fn __level_1_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level1_interrupt(save_frame) };
 }
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_2_interrupt() {
-    unsafe { level2_interrupt() };
+fn __level_2_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level2_interrupt(save_frame) };
 }
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_3_interrupt() {
-    unsafe { level3_interrupt() };
+fn __level_3_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level3_interrupt(save_frame) };
 }
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_4_interrupt() {
-    unsafe { level4_interrupt() };
+fn __level_4_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level4_interrupt(save_frame) };
 }
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_5_interrupt() {
-    unsafe { level5_interrupt() };
+fn __level_5_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level5_interrupt(save_frame) };
 }
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_6_interrupt() {
-    unsafe { level6_interrupt() };
+fn __level_6_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level6_interrupt(save_frame) };
 }
 
 #[no_mangle]
 #[link_section = ".rwtext"]
-fn __level_7_interrupt() {
-    unsafe { level7_interrupt() };
+fn __level_7_interrupt(_level: u32, save_frame: &mut Context) {
+    unsafe { level7_interrupt(save_frame) };
 }

esp32-hal/Cargo.toml

@@ -29,7 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
 nb           = "1.0"
 void         = { version = "1.0", default-features = false }
 xtensa-lx    = { version = "0.6.0", features = ["esp32"] }
-xtensa-lx-rt = { version = "0.9.0", features = ["esp32"], optional = true }
+xtensa-lx-rt = { version = "0.10.0", features = ["esp32"], optional = true }
 
 [dependencies.esp-hal-common]
 path     = "../esp-hal-common"

esp32s2-hal/Cargo.toml

@@ -29,7 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
 nb           = "1.0"
 void         = { version = "1.0", default-features = false }
 xtensa-lx    = { version = "0.6.0", features = ["esp32"] } # FIXME
-xtensa-lx-rt = { version = "0.9.0", features = ["esp32s2"], optional = true }
+xtensa-lx-rt = { version = "0.10.0", features = ["esp32s2"], optional = true }
 
 [dependencies.esp-hal-common]
 path     = "../esp-hal-common"

esp32s3-hal/Cargo.toml

@@ -29,7 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
 nb           = "1.0"
 void         = { version = "1.0", default-features = false }
 xtensa-lx    = { version = "0.6.0", features = ["esp32"] } # FIXME
-xtensa-lx-rt = { version = "0.9.0", features = ["esp32s3"], optional = true }
+xtensa-lx-rt = { version = "0.10.0", features = ["esp32s3"], optional = true }
 
 [dependencies.esp-hal-common]
 path     = "../esp-hal-common"