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Fix half-duplex SPI read (#552)

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* Fix half-duplex SPI read

* Update CHANGELOG.md
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Björn Quentin 2023-05-22 14:02:33 +02:00 committed by GitHub
parent 02c7e38cf5
commit 7b3e19c4c6
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2 changed files with 8 additions and 2 deletions
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CHANGELOG.md
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@ -35,6 +35,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Set `vecbase` on core 1 (ESP32, ESP32-S3) (#536) - Set `vecbase` on core 1 (ESP32, ESP32-S3) (#536)
- ESP32-S3: Move PSRAM related function to RAM (#546) - ESP32-S3: Move PSRAM related function to RAM (#546)
- ADC driver will now apply attenuation values to the correct ADC's channels. (#554) - ADC driver will now apply attenuation values to the correct ADC's channels. (#554)
- Sometimes half-duplex non-DMA SPI reads were reading garbage in non-release mode (#552)
### Changed ### Changed

9
esp-hal-common/src/spi.rs
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@ -2881,8 +2881,13 @@ pub trait Instance {
.modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1));
} }
// re-using the full-duplex read which does dummy writes which is okay self.configure_datalen(buffer.len() as u32 * 8);
self.read_bytes(buffer) self.update();
reg_block.cmd.modify(|_, w| w.usr().set_bit());
while reg_block.cmd.read().usr().bit_is_set() {
// wait for completion
}
self.read_bytes_from_fifo(buffer)
} }
#[cfg(not(any(esp32, esp32s2)))] #[cfg(not(any(esp32, esp32s2)))]