From 7b3e19c4c6bbca778f3ac77c036635bb1a919e75 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Mon, 22 May 2023 14:02:33 +0200 Subject: [PATCH] Fix half-duplex SPI read (#552) * Fix half-duplex SPI read * Update CHANGELOG.md --- CHANGELOG.md | 1 + esp-hal-common/src/spi.rs | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8e795d255..e7c67e419 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -35,6 +35,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Set `vecbase` on core 1 (ESP32, ESP32-S3) (#536) - ESP32-S3: Move PSRAM related function to RAM (#546) - ADC driver will now apply attenuation values to the correct ADC's channels. (#554) +- Sometimes half-duplex non-DMA SPI reads were reading garbage in non-release mode (#552) ### Changed diff --git a/esp-hal-common/src/spi.rs b/esp-hal-common/src/spi.rs index 853e5b208..4593fde6e 100644 --- a/esp-hal-common/src/spi.rs +++ b/esp-hal-common/src/spi.rs @@ -2881,8 +2881,13 @@ pub trait Instance { .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); } - // re-using the full-duplex read which does dummy writes which is okay - self.read_bytes(buffer) + self.configure_datalen(buffer.len() as u32 * 8); + self.update(); + reg_block.cmd.modify(|_, w| w.usr().set_bit()); + while reg_block.cmd.read().usr().bit_is_set() { + // wait for completion + } + self.read_bytes_from_fifo(buffer) } #[cfg(not(any(esp32, esp32s2)))]