Clock monitor HIL test (#1425)
* tests: Add clock_monitor HIL test * feat: Adjust accepted freq ranges * fix: Get the estimate a second time if its very off * test: Update ranges and check
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@ -1821,6 +1821,10 @@ impl RtcClock {
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.rtc_cali_start()
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.set_bit()
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});
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timg0
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.rtccalicfg()
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.modify(|_, w| w.rtc_cali_start().set_bit());
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while timg0.rtccalicfg().read().rtc_cali_rdy().bit_is_clear() {}
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(timg0.rtccalicfg1().read().rtc_cali_value().bits()
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@ -628,6 +628,11 @@ impl RtcClock {
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.rtc_cali_start()
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.set_bit()
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});
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timg0
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.rtccalicfg()
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.modify(|_, w| w.rtc_cali_start().set_bit());
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while timg0.rtccalicfg().read().rtc_cali_rdy().bit_is_clear() {}
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(timg0.rtccalicfg1().read().rtc_cali_value().bits()
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@ -12,6 +12,10 @@ harness = false
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name = "aes_dma"
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harness = false
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[[test]]
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name = "clock_monitor"
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harness = false
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[[test]]
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name = "crc"
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harness = false
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47
hil-test/tests/clock_monitor.rs
Normal file
47
hil-test/tests/clock_monitor.rs
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@ -0,0 +1,47 @@
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//! Clock Monitor Test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use defmt_rtt as _;
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use esp_backtrace as _;
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use esp_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, rtc_cntl::Rtc};
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struct Context<'a> {
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rtc: Rtc<'a>,
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}
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impl Context<'_> {
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pub fn init() -> Self {
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let peripherals = Peripherals::take();
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let system = peripherals.SYSTEM.split();
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ClockControl::boot_defaults(system.clock_control).freeze();
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let rtc = Rtc::new(peripherals.LPWR, None);
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Context { rtc }
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}
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context<'static> {
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Context::init()
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}
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#[test]
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fn test_estimated_clock(mut ctx: Context<'static>) {
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#[cfg(feature = "esp32c2")] // 26 MHz
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defmt::assert!((23..=29).contains(&ctx.rtc.estimate_xtal_frequency()));
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#[cfg(feature = "esp32h2")] // 32 MHz
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defmt::assert!((29..=35).contains(&ctx.rtc.estimate_xtal_frequency()));
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#[cfg(not(any(feature = "esp32h2", feature = "esp32c2")))] // 40 MHz
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defmt::assert!((35..=45).contains(&ctx.rtc.estimate_xtal_frequency()));
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}
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}
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