From 381ce9530cc2429753b091d43b4abacb384768a4 Mon Sep 17 00:00:00 2001
From: Sergio Gasquez Arcos <sergio.gasquez@gmail.com>
Date: Mon, 15 Apr 2024 11:54:55 +0200
Subject: [PATCH] Clock monitor HIL test (#1425)

* tests: Add clock_monitor HIL test

* feat: Adjust accepted freq ranges

* fix: Get the estimate a second time if its very off

* test: Update ranges and check
---
 esp-hal/src/rtc_cntl/rtc/esp32c6.rs |  4 +++
 esp-hal/src/rtc_cntl/rtc/esp32h2.rs |  5 +++
 hil-test/Cargo.toml                 |  4 +++
 hil-test/tests/clock_monitor.rs     | 47 +++++++++++++++++++++++++++++
 4 files changed, 60 insertions(+)
 create mode 100644 hil-test/tests/clock_monitor.rs

diff --git a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs
index 6dc3891fb..c749d7673 100644
--- a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs
+++ b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs
@@ -1821,6 +1821,10 @@ impl RtcClock {
                 .rtc_cali_start()
                 .set_bit()
         });
+        timg0
+            .rtccalicfg()
+            .modify(|_, w| w.rtc_cali_start().set_bit());
+
         while timg0.rtccalicfg().read().rtc_cali_rdy().bit_is_clear() {}
 
         (timg0.rtccalicfg1().read().rtc_cali_value().bits()
diff --git a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs
index 028b495e1..6b86c4de8 100644
--- a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs
+++ b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs
@@ -628,6 +628,11 @@ impl RtcClock {
                 .rtc_cali_start()
                 .set_bit()
         });
+
+        timg0
+            .rtccalicfg()
+            .modify(|_, w| w.rtc_cali_start().set_bit());
+
         while timg0.rtccalicfg().read().rtc_cali_rdy().bit_is_clear() {}
 
         (timg0.rtccalicfg1().read().rtc_cali_value().bits()
diff --git a/hil-test/Cargo.toml b/hil-test/Cargo.toml
index 8d802040f..f582c13da 100644
--- a/hil-test/Cargo.toml
+++ b/hil-test/Cargo.toml
@@ -12,6 +12,10 @@ harness = false
 name    = "aes_dma"
 harness = false
 
+[[test]]
+name    = "clock_monitor"
+harness = false
+
 [[test]]
 name    = "crc"
 harness = false
diff --git a/hil-test/tests/clock_monitor.rs b/hil-test/tests/clock_monitor.rs
new file mode 100644
index 000000000..f300d129b
--- /dev/null
+++ b/hil-test/tests/clock_monitor.rs
@@ -0,0 +1,47 @@
+//! Clock Monitor Test
+
+//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
+
+#![no_std]
+#![no_main]
+
+use defmt_rtt as _;
+use esp_backtrace as _;
+use esp_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, rtc_cntl::Rtc};
+
+struct Context<'a> {
+    rtc: Rtc<'a>,
+}
+
+impl Context<'_> {
+    pub fn init() -> Self {
+        let peripherals = Peripherals::take();
+        let system = peripherals.SYSTEM.split();
+        ClockControl::boot_defaults(system.clock_control).freeze();
+
+        let rtc = Rtc::new(peripherals.LPWR, None);
+
+        Context { rtc }
+    }
+}
+
+#[cfg(test)]
+#[embedded_test::tests]
+mod tests {
+    use super::*;
+
+    #[init]
+    fn init() -> Context<'static> {
+        Context::init()
+    }
+
+    #[test]
+    fn test_estimated_clock(mut ctx: Context<'static>) {
+        #[cfg(feature = "esp32c2")] // 26 MHz
+        defmt::assert!((23..=29).contains(&ctx.rtc.estimate_xtal_frequency()));
+        #[cfg(feature = "esp32h2")] // 32 MHz
+        defmt::assert!((29..=35).contains(&ctx.rtc.estimate_xtal_frequency()));
+        #[cfg(not(any(feature = "esp32h2", feature = "esp32c2")))] // 40 MHz
+        defmt::assert!((35..=45).contains(&ctx.rtc.estimate_xtal_frequency()));
+    }
+}