138 lines
4.3 KiB
Rust
138 lines
4.3 KiB
Rust
//! This test needs a connection between GPIO 4 and GPIO 7 (pins 6 and 10 an a Pico)
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#![no_std]
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#![no_main]
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#![cfg(test)]
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use crate::hal::dma::Channels;
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use defmt_rtt as _; // defmt transport
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use defmt_test as _;
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use panic_probe as _;
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use rp2040_hal as hal; // memory layout // panic handler
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use rp2040_hal::gpio::{self, Pin};
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use rp2040_hal::pac::SPI0;
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use rp2040_hal::spi;
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/// The linker will place this boot block at the start of our program image. We
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/// need this to help the ROM bootloader get our code up and running.
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/// Note: This boot block is not necessary when using a rp-hal based BSP
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/// as the BSPs already perform this step.
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#[link_section = ".boot2"]
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#[used]
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pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_GENERIC_03H;
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/// External high-speed crystal on the Raspberry Pi Pico board is 12 MHz. Adjust
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/// if your board has a different frequency
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const XTAL_FREQ_HZ: u32 = 12_000_000u32;
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type MISO = Pin<gpio::bank0::Gpio4, gpio::FunctionSpi, gpio::PullNone>;
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type MOSI = Pin<gpio::bank0::Gpio7, gpio::FunctionSpi, gpio::PullNone>;
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type SCLK = Pin<gpio::bank0::Gpio6, gpio::FunctionSpi, gpio::PullNone>;
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struct State {
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channels: Option<Channels>,
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spi: Option<spi::Spi<spi::Enabled, SPI0, (MOSI, MISO, SCLK), 8>>,
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}
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mod testdata {
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#[allow(dead_code)]
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pub const ARRAY_U8: [u8; 10] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10];
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#[allow(dead_code)]
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pub const ARRAY_U16: [u16; 10] = [270, 271, 272, 273, 274, 275, 276, 277, 278, 279];
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#[allow(dead_code)]
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pub const ARRAY_U32: [u32; 10] = [
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65571, 65572, 65573, 65574, 65575, 65576, 65577, 65578, 65579, 65580,
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];
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#[allow(dead_code)]
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pub const ARRAY_U64: [u64; 10] = [
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65571, 65572, 65573, 65574, 65575, 65576, 65577, 65578, 65579, 65580,
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];
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}
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#[defmt_test::tests]
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mod tests {
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use crate::testdata;
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use crate::State;
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use crate::XTAL_FREQ_HZ;
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use defmt::assert_eq;
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use defmt_rtt as _;
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use fugit::RateExtU32;
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use hal::{clocks::init_clocks_and_plls, pac, watchdog::Watchdog};
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use panic_probe as _;
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use rp2040_hal as hal;
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use rp2040_hal::dma::bidirectional;
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use rp2040_hal::dma::DMAExt;
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use rp2040_hal::Clock;
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#[init]
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fn setup() -> State {
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unsafe {
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hal::sio::spinlock_reset();
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}
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let mut pac = pac::Peripherals::take().unwrap();
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let _core = pac::CorePeripherals::take().unwrap();
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let mut watchdog = Watchdog::new(pac.WATCHDOG);
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let clocks = init_clocks_and_plls(
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XTAL_FREQ_HZ,
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pac.XOSC,
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pac.CLOCKS,
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pac.PLL_SYS,
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pac.PLL_USB,
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&mut pac.RESETS,
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&mut watchdog,
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)
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.ok()
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.unwrap();
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let dma = pac.DMA.split(&mut pac.RESETS);
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// Setup the pins.
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let sio = hal::sio::Sio::new(pac.SIO);
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let pins = hal::gpio::Pins::new(
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pac.IO_BANK0,
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pac.PADS_BANK0,
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sio.gpio_bank0,
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&mut pac.RESETS,
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);
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// Set up our SPI pins into the correct mode
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let spi_sclk = pins.gpio6.reconfigure();
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let spi_mosi = pins.gpio7.reconfigure();
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let spi_miso = pins.gpio4.reconfigure();
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let spi = hal::spi::Spi::new(pac.SPI0, (spi_mosi, spi_miso, spi_sclk));
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// Exchange the uninitialised SPI driver for an initialised one
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let spi = spi.init(
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&mut pac.RESETS,
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clocks.peripheral_clock.freq(),
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16_000_000u32.Hz(),
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&embedded_hal::spi::MODE_0,
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);
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State {
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channels: Some(dma),
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spi: Some(spi),
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}
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}
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#[test]
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fn dma_spi_loopback_u8(state: &mut State) {
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if let Some(dma) = state.channels.take() {
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if let Some(spi) = state.spi.take() {
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let rx_buf = cortex_m::singleton!(: [u8; 10] = [0; 10]).unwrap();
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let tx_buf = cortex_m::singleton!(: [u8; 10] = testdata::ARRAY_U8).unwrap();
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let transfer =
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bidirectional::Config::new((dma.ch0, dma.ch1), tx_buf, spi, rx_buf).start();
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let ((_ch0, _ch1), tx_buf, _spi, rx_buf) = transfer.wait();
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let first = tx_buf.iter();
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let second = rx_buf.iter();
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for (x, y) in first.zip(second) {
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assert_eq!(x, y);
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}
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}
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}
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}
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}
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