f7830e2750
* Move some linker scripts into `esp-hal-common` and update the build script * Move `EspDefaultHandler` and `DefaultHandler` definitions into `esp-hal-common` * Re-export everything from `esp-hal-common` * Add a couple cfg symbols, cleanup/organize some exports/modules
273 lines
7.6 KiB
Rust
273 lines
7.6 KiB
Rust
//! `no_std` HAL implementations for the peripherals which are common among
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//! Espressif devices. Implements a number of the traits defined by
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//! [embedded-hal].
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//!
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//! This crate should not be used directly; you should use one of the
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//! device-specific HAL crates instead:
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//!
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//! - [esp32-hal]
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//! - [esp32c2-hal]
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//! - [esp32c3-hal]
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//! - [esp32c6-hal]
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//! - [esp32s2-hal]
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//! - [esp32s3-hal]
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//!
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//! [embedded-hal]: https://docs.rs/embedded-hal/latest/embedded_hal/
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//! [esp32-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32-hal
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//! [esp32c2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c2-hal
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//! [esp32c3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c3-hal
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//! [esp32c6-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32c6-hal
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//! [esp32s2-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s2-hal
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//! [esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal
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#![no_std]
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#![cfg_attr(xtensa, feature(asm_experimental_arch))]
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#![cfg_attr(
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feature = "async",
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allow(incomplete_features),
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feature(async_fn_in_trait),
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feature(impl_trait_projections)
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)]
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#[cfg(riscv)]
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pub use esp_riscv_rt::{self, entry, riscv};
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pub use procmacros as macros;
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#[cfg(xtensa)]
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pub use xtensa_lx;
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#[cfg(xtensa)]
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pub use xtensa_lx_rt::{self, entry};
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#[cfg(dac)]
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pub use self::analog::dac::implementation as dac;
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#[cfg(gdma)]
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pub use self::dma::gdma;
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#[cfg(pdma)]
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pub use self::dma::pdma;
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#[cfg(rmt)]
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pub use self::pulse_control::PulseControl;
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#[cfg(any(esp32, esp32s3))]
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pub use self::soc::cpu_control;
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#[cfg(usb_serial_jtag)]
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pub use self::usb_serial_jtag::UsbSerialJtag;
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pub use self::{
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analog::adc::implementation as adc,
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delay::Delay,
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interrupt::*,
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rng::Rng,
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rtc_cntl::{Rtc, Rwdt},
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soc::{efuse, peripherals},
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spi::Spi,
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timer::Timer,
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uart::Uart,
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};
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#[cfg(aes)]
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pub mod aes;
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pub mod analog;
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pub mod clock;
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pub mod delay;
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pub mod dma;
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#[cfg(feature = "embassy")]
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pub mod embassy;
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pub mod gpio;
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pub mod i2c;
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#[cfg(i2s)]
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pub mod i2s;
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pub mod interrupt;
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pub mod ledc;
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#[cfg(mcpwm)]
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pub mod mcpwm;
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#[cfg(usb_otg)]
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pub mod otg_fs;
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#[cfg(pcnt)]
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pub mod pcnt;
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pub mod peripheral;
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pub mod prelude;
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#[cfg(rmt)]
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pub mod pulse_control;
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#[cfg(radio)]
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pub mod radio;
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pub mod rng;
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pub mod rom;
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pub mod rtc_cntl;
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pub mod sha;
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pub mod soc;
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pub mod spi;
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pub mod system;
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#[cfg(systimer)]
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pub mod systimer;
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pub mod timer;
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#[cfg(any(twai))]
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pub mod twai;
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pub mod uart;
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#[cfg(usb_serial_jtag)]
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pub mod usb_serial_jtag;
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#[cfg(rmt)]
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pub mod utils;
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/// State of the CPU saved when entering exception or interrupt
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pub mod trapframe {
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#[cfg(riscv)]
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pub use esp_riscv_rt::TrapFrame;
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#[cfg(xtensa)]
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pub use xtensa_lx_rt::exception::Context as TrapFrame;
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}
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#[no_mangle]
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extern "C" fn EspDefaultHandler(_level: u32, _interrupt: peripherals::Interrupt) {}
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#[cfg(xtensa)]
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#[no_mangle]
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extern "C" fn DefaultHandler() {}
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#[cfg(esp32c6)]
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pub fn disable_apm_filter() {
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unsafe {
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(&*esp32c6::LP_APM::PTR).func_ctrl.write(|w| w.bits(0));
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(&*esp32c6::LP_APM0::PTR).func_ctrl.write(|w| w.bits(0));
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(&*esp32c6::HP_APM::PTR).func_ctrl.write(|w| w.bits(0));
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}
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}
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/// Enumeration of CPU cores
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/// The actual number of available cores depends on the target.
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pub enum Cpu {
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/// The first core
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ProCpu = 0,
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/// The second core
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AppCpu,
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}
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pub fn get_core() -> Cpu {
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#[cfg(all(xtensa, multi_core))]
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match ((xtensa_lx::get_processor_id() >> 13) & 1) != 0 {
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false => Cpu::ProCpu,
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true => Cpu::AppCpu,
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}
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// #[cfg(all(riscv, multi_core))]
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// TODO get hart_id
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// single core always has ProCpu only
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#[cfg(single_core)]
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Cpu::ProCpu
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}
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mod critical_section_impl {
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struct CriticalSection;
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critical_section::set_impl!(CriticalSection);
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#[cfg(xtensa)]
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mod xtensa {
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unsafe impl critical_section::Impl for super::CriticalSection {
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unsafe fn acquire() -> critical_section::RawRestoreState {
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let tkn: critical_section::RawRestoreState;
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core::arch::asm!("rsil {0}, 5", out(reg) tkn);
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#[cfg(multi_core)]
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{
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let guard = super::multicore::MULTICORE_LOCK.lock();
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core::mem::forget(guard); // forget it so drop doesn't run
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}
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tkn
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}
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unsafe fn release(token: critical_section::RawRestoreState) {
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if token != 0 {
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#[cfg(multi_core)]
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{
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debug_assert!(super::multicore::MULTICORE_LOCK.is_owned_by_current_thread());
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// safety: we logically own the mutex from acquire()
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super::multicore::MULTICORE_LOCK.force_unlock();
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}
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core::arch::asm!(
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"wsr.ps {0}",
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"rsync", in(reg) token)
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}
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}
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}
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}
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#[cfg(riscv)]
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mod riscv {
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use esp_riscv_rt::riscv;
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unsafe impl critical_section::Impl for super::CriticalSection {
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unsafe fn acquire() -> critical_section::RawRestoreState {
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let mut mstatus = 0u32;
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core::arch::asm!("csrrci {0}, mstatus, 8", inout(reg) mstatus);
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let interrupts_active = (mstatus & 0b1000) != 0;
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#[cfg(multi_core)]
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{
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let guard = multicore::MULTICORE_LOCK.lock();
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core::mem::forget(guard); // forget it so drop doesn't run
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}
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interrupts_active as _
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}
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unsafe fn release(token: critical_section::RawRestoreState) {
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if token != 0 {
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#[cfg(multi_core)]
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{
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debug_assert!(multicore::MULTICORE_LOCK.is_owned_by_current_thread());
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// safety: we logically own the mutex from acquire()
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multicore::MULTICORE_LOCK.force_unlock();
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}
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riscv::interrupt::enable();
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}
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}
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}
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}
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#[cfg(multi_core)]
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mod multicore {
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use core::sync::atomic::{AtomicBool, Ordering};
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use lock_api::{GetThreadId, GuardSend, RawMutex};
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use crate::get_core;
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/// Reentrant Mutex
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///
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/// Currently implemented using an atomic spin lock.
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/// In the future we can optimize this raw mutex to use some hardware
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/// features.
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pub(crate) static MULTICORE_LOCK: lock_api::ReentrantMutex<RawSpinlock, RawThreadId, ()> =
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lock_api::ReentrantMutex::const_new(RawSpinlock::INIT, RawThreadId::INIT, ());
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pub(crate) struct RawThreadId;
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unsafe impl lock_api::GetThreadId for RawThreadId {
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const INIT: Self = RawThreadId;
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fn nonzero_thread_id(&self) -> core::num::NonZeroUsize {
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core::num::NonZeroUsize::new((get_core() as usize) + 1).unwrap()
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}
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}
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pub(crate) struct RawSpinlock(AtomicBool);
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unsafe impl lock_api::RawMutex for RawSpinlock {
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const INIT: RawSpinlock = RawSpinlock(AtomicBool::new(false));
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// A spinlock guard can be sent to another thread and unlocked there
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type GuardMarker = GuardSend;
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fn lock(&self) {
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while !self.try_lock() {}
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}
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fn try_lock(&self) -> bool {
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self.0
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.compare_exchange(false, true, Ordering::Acquire, Ordering::Relaxed)
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.is_ok()
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}
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unsafe fn unlock(&self) {
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self.0.store(false, Ordering::Release);
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}
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}
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}
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}
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