c7a2368845
* Print panic messages using semihosting * Don't use defmt's asserts * Make RA_OFFSET available without panic-handler * Re-add defmt imports where missing * Revert unintended test change * Initialise hal in critical-section test * Disable defmt in tests by default
425 lines
15 KiB
Rust
425 lines
15 KiB
Rust
use core::{arch::asm, fmt::Display};
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use crate::MAX_BACKTRACE_ADDRESSES;
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// subtract 3 from the return address
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// the return address is the address following the callxN
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// we get better results (especially if the caller was the last function in the
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// calling function) if we report the address of callxN itself
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#[allow(unused)]
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pub(super) const RA_OFFSET: usize = 3;
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/// Exception Cause
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#[doc(hidden)]
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#[derive(Debug, Clone, Copy, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[repr(C)]
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pub enum ExceptionCause {
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/// Illegal Instruction
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IllegalInstruction = 0,
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/// System Call (Syscall Instruction)
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Syscall = 1,
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/// Instruction Fetch Error
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InstrFetchError = 2,
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/// Load Store Error
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LoadStoreError = 3,
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/// Level 1 Interrupt
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LevelOneInterrupt = 4,
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/// Stack Extension Assist (movsp Instruction) For Alloca
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Alloca = 5,
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/// Integer Divide By Zero
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DivideByZero = 6,
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/// Use Of Failed Speculative Access (Not Implemented)
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NextPCValueIllegal = 7,
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/// Privileged Instruction
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PrivilegedInstruction = 8,
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/// Unaligned Load Or Store
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UnalignedLoadOrStore = 9,
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/// Reserved
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ExternalRegisterPrivilegeError = 10,
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/// Reserved
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ExclusiveError = 11,
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/// Pif Data Error On Instruction Fetch (Rb-200x And Later)
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InstrDataError = 12,
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/// Pif Data Error On Load Or Store (Rb-200x And Later)
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LoadStoreDataError = 13,
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/// Pif Address Error On Instruction Fetch (Rb-200x And Later)
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InstrAddrError = 14,
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/// Pif Address Error On Load Or Store (Rb-200x And Later)
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LoadStoreAddrError = 15,
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/// Itlb Miss (No Itlb Entry Matches, Hw Refill Also Missed)
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ItlbMiss = 16,
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/// Itlb Multihit (Multiple Itlb Entries Match)
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ItlbMultiHit = 17,
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/// Ring Privilege Violation On Instruction Fetch
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InstrRing = 18,
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/// Size Restriction On Ifetch (Not Implemented)
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Reserved19 = 19,
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/// Cache Attribute Does Not Allow Instruction Fetch
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InstrProhibited = 20,
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/// Reserved
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Reserved21 = 21,
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/// Reserved
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Reserved22 = 22,
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/// Reserved
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Reserved23 = 23,
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/// Dtlb Miss (No Dtlb Entry Matches, Hw Refill Also Missed)
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DtlbMiss = 24,
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/// Dtlb Multihit (Multiple Dtlb Entries Match)
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DtlbMultiHit = 25,
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/// Ring Privilege Violation On Load Or Store
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LoadStoreRing = 26,
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/// Size Restriction On Load/Store (Not Implemented)
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Reserved27 = 27,
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/// Cache Attribute Does Not Allow Load
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LoadProhibited = 28,
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/// Cache Attribute Does Not Allow Store
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StoreProhibited = 29,
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/// Reserved
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Reserved30 = 30,
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/// Reserved
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Reserved31 = 31,
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/// Access To Coprocessor 0 When Disabled
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Cp0Disabled = 32,
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/// Access To Coprocessor 1 When Disabled
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Cp1Disabled = 33,
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/// Access To Coprocessor 2 When Disabled
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Cp2Disabled = 34,
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/// Access To Coprocessor 3 When Disabled
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Cp3Disabled = 35,
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/// Access To Coprocessor 4 When Disabled
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Cp4Disabled = 36,
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/// Access To Coprocessor 5 When Disabled
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Cp5Disabled = 37,
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/// Access To Coprocessor 6 When Disabled
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Cp6Disabled = 38,
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/// Access To Coprocessor 7 When Disabled
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Cp7Disabled = 39,
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/// None
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None = 255,
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}
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impl Display for ExceptionCause {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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if *self == Self::Cp0Disabled {
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write!(f, "Cp0Disabled (Access to the floating point coprocessor is not allowed. You may want to enable the `float-save-restore` feature of the `xtensa-lx-rt` crate.)")
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} else {
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write!(f, "{:?}", self)
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}
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}
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}
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#[doc(hidden)]
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#[allow(non_snake_case)]
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#[derive(Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[repr(C)]
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pub struct Context {
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/// Program counter, stores the address of the next instruction to be
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/// executed.
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pub PC: u32,
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/// Processor status, holds various status flags for the CPU.
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pub PS: u32,
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/// General-purpose register A0 used for data storage and manipulation.
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pub A0: u32,
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/// General-purpose register A1 used for data storage and manipulation.
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pub A1: u32,
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/// General-purpose register A2 used for data storage and manipulation.
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pub A2: u32,
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/// General-purpose register A3 used for data storage and manipulation.
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pub A3: u32,
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/// General-purpose register A4 used for data storage and manipulation.
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pub A4: u32,
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/// General-purpose register A5 used for data storage and manipulation.
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pub A5: u32,
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/// General-purpose register A6 used for data storage and manipulation.
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pub A6: u32,
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/// General-purpose register A7 used for data storage and manipulation.
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pub A7: u32,
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/// General-purpose register A8 used for data storage and manipulation.
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pub A8: u32,
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/// General-purpose register A9 used for data storage and manipulation.
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pub A9: u32,
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/// General-purpose register A10 used for data storage and manipulation.
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pub A10: u32,
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/// General-purpose register A11 used for data storage and manipulation.
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pub A11: u32,
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/// General-purpose register A12 used for data storage and manipulation.
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pub A12: u32,
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/// General-purpose register A13 used for data storage and manipulation.
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pub A13: u32,
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/// General-purpose register A14 used for data storage and manipulation.
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pub A14: u32,
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/// General-purpose register A15 used for data storage and manipulation.
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pub A15: u32,
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/// Shift amount register, used for shift and rotate instructions.
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pub SAR: u32,
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/// Exception cause, indicates the reason for the last exception.
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pub EXCCAUSE: u32,
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/// Exception address, holds the address related to the exception.
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pub EXCVADDR: u32,
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/// Loop start address, used in loop instructions.
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pub LBEG: u32,
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/// Loop end address, used in loop instructions.
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pub LEND: u32,
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/// Loop counter, used to count iterations in loop instructions.
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pub LCOUNT: u32,
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/// Thread pointer, used for thread-local storage.
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pub THREADPTR: u32,
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/// Compare register, used for certain compare instructions.
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pub SCOMPARE1: u32,
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/// Break register, used for breakpoint-related operations.
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pub BR: u32,
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/// Accumulator low register, used for extended arithmetic operations.
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pub ACCLO: u32,
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/// Accumulator high register, used for extended arithmetic operations.
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pub ACCHI: u32,
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/// Additional register M0 used for special operations.
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pub M0: u32,
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/// Additional register M1 used for special operations.
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pub M1: u32,
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/// Additional register M2 used for special operations.
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pub M2: u32,
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/// Additional register M3 used for special operations.
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pub M3: u32,
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/// 64-bit floating-point register (low part), available if the
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/// `print-float-registers` feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F64R_LO: u32,
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/// 64-bit floating-point register (high part), available if the
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/// `print-float-registers` feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F64R_HI: u32,
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/// Floating-point status register, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F64S: u32,
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/// Floating-point control register, available if the
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/// `print-float-registers` feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub FCR: u32,
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/// Floating-point status register, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub FSR: u32,
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/// Floating-point register F0, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F0: u32,
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/// Floating-point register F1, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F1: u32,
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/// Floating-point register F2, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F2: u32,
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/// Floating-point register F3, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F3: u32,
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/// Floating-point register F4, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F4: u32,
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/// Floating-point register F5, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F5: u32,
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/// Floating-point register F6, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F6: u32,
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/// Floating-point register F7, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F7: u32,
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/// Floating-point register F8, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F8: u32,
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/// Floating-point register F9, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F9: u32,
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/// Floating-point register F10, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F10: u32,
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/// Floating-point register F11, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F11: u32,
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/// Floating-point register F12, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F12: u32,
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/// Floating-point register F13, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F13: u32,
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/// Floating-point register F14, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F14: u32,
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/// Floating-point register F15, available if the `print-float-registers`
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/// feature is enabled.
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#[cfg(feature = "print-float-registers")]
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pub F15: u32,
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}
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impl core::fmt::Debug for Context {
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fn fmt(&self, fmt: &mut core::fmt::Formatter<'_>) -> Result<(), core::fmt::Error> {
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write!(
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fmt,
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"Context
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PC=0x{:08x} PS=0x{:08x}
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A0=0x{:08x} A1=0x{:08x} A2=0x{:08x} A3=0x{:08x} A4=0x{:08x}
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A5=0x{:08x} A6=0x{:08x} A7=0x{:08x} A8=0x{:08x} A9=0x{:08x}
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A10=0x{:08x} A11=0x{:08x} A12=0x{:08x} A13=0x{:08x} A14=0x{:08x}
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A15=0x{:08x}
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SAR={:08x}
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EXCCAUSE=0x{:08x} EXCVADDR=0x{:08x}
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LBEG=0x{:08x} LEND=0x{:08x} LCOUNT=0x{:08x}
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THREADPTR=0x{:08x}
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SCOMPARE1=0x{:08x}
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BR=0x{:08x}
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ACCLO=0x{:08x} ACCHI=0x{:08x}
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M0=0x{:08x} M1=0x{:08x} M2=0x{:08x} M3=0x{:08x}
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",
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self.PC,
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self.PS,
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self.A0,
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self.A1,
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self.A2,
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self.A3,
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self.A4,
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self.A5,
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self.A6,
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self.A7,
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self.A8,
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self.A9,
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self.A10,
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self.A11,
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self.A12,
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self.A13,
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self.A14,
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self.A15,
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self.SAR,
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self.EXCCAUSE,
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self.EXCVADDR,
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self.LBEG,
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self.LEND,
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self.LCOUNT,
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self.THREADPTR,
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self.SCOMPARE1,
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self.BR,
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self.ACCLO,
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self.ACCHI,
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self.M0,
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self.M1,
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self.M2,
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self.M3,
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)?;
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#[cfg(feature = "print-float-registers")]
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write!(
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fmt,
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"F64R_LO=0x{:08x} F64R_HI=0x{:08x} F64S=0x{:08x}
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FCR=0x{:08x} FSR=0x{:08x}
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F0=0x{:08x} F1=0x{:08x} F2=0x{:08x} F3=0x{:08x} F4=0x{:08x}
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F5=0x{:08x} F6=0x{:08x} F7=0x{:08x} F8=0x{:08x} F9=0x{:08x}
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F10=0x{:08x} F11=0x{:08x} F12=0x{:08x} F13=0x{:08x} F14=0x{:08x}
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F15=0x{:08x}",
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self.F64R_LO,
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self.F64R_HI,
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self.F64S,
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self.FCR,
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self.FSR,
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self.F0,
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self.F1,
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self.F2,
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self.F3,
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self.F4,
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self.F5,
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self.F6,
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self.F7,
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self.F8,
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self.F9,
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self.F10,
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self.F11,
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self.F12,
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self.F13,
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self.F14,
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self.F15,
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)?;
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Ok(())
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}
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}
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/// Get an array of backtrace addresses.
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pub fn backtrace() -> [Option<usize>; MAX_BACKTRACE_ADDRESSES] {
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let sp = unsafe {
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let mut _tmp: u32;
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asm!("mov {0}, a1", out(reg) _tmp);
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_tmp
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};
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backtrace_internal(sp, 1)
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}
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pub(crate) fn sanitize_address(address: u32) -> u32 {
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(address & 0x3fff_ffff) | 0x4000_0000
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}
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pub(crate) fn backtrace_internal(
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sp: u32,
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suppress: i32,
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) -> [Option<usize>; MAX_BACKTRACE_ADDRESSES] {
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let mut result = [None; 10];
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let mut index = 0;
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let mut fp = sp;
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let mut suppress = suppress;
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let mut old_address = 0;
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loop {
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unsafe {
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let address = sanitize_address((fp as *const u32).offset(-4).read_volatile()); // RA/PC
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fp = (fp as *const u32).offset(-3).read_volatile(); // next FP
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if old_address == address {
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break;
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}
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old_address = address;
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// the address is 0 but we sanitized the address - then 0 becomes 0x40000000
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if address == 0x40000000 {
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break;
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}
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if !crate::is_valid_ram_address(fp) {
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break;
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}
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if fp == 0 {
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break;
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}
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if suppress == 0 {
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result[index] = Some(address as usize);
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index += 1;
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if index >= MAX_BACKTRACE_ADDRESSES {
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break;
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}
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} else {
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suppress -= 1;
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}
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}
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}
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result
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}
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