3f7181fece
* ground work for async dma (gdma only atm) * Add async DMA (GDMA) - esp32c3/esp32c2 * Add Async SPI impl for esp32c3/c2 * Remove private modules from DMA * add async spi example for esp32c3 * Switch to assoc wakers instead of a static array * add support for esp32/esp32s2 * add support for esp32s3 * run fmt * add c2 example, fix CI * Remove redundant comments
576 lines
22 KiB
Rust
576 lines
22 KiB
Rust
//! Direct Memory Access
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use crate::{
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dma::*,
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peripheral::PeripheralRef,
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system::{Peripheral, PeripheralClockControl},
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};
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macro_rules! ImplSpiChannel {
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($num: literal) => {
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paste::paste! {
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pub struct [<Spi $num DmaChannel>] {}
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impl RegisterAccess for [<Spi $num DmaChannel>] {
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fn init_channel() {
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// (only) on ESP32 we need to configure DPORT for the SPI DMA channels
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#[cfg(esp32)]
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{
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let dport = unsafe { &*crate::peripherals::DPORT::PTR };
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match $num {
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2 => {
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dport
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.spi_dma_chan_sel
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.modify(|_, w| w.spi2_dma_chan_sel().variant(1));
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},
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3 => {
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dport
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.spi_dma_chan_sel
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.modify(|_, w| w.spi3_dma_chan_sel().variant(2));
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},
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_ => panic!("Only SPI2 and SPI3 supported"),
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}
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}
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}
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fn set_out_burstmode(burst_mode: bool) {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_conf
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.modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
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}
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fn set_out_priority(_priority: DmaPriority) {}
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fn clear_out_interrupts() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_clr.write(|w| {
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w.out_done_int_clr()
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.set_bit()
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.out_eof_int_clr()
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.set_bit()
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.out_total_eof_int_clr()
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.set_bit()
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.outlink_dscr_error_int_clr()
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.set_bit()
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});
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}
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fn reset_out() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_conf.modify(|_, w| w.out_rst().set_bit());
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spi.dma_conf.modify(|_, w| w.out_rst().clear_bit());
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}
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fn set_out_descriptors(address: u32) {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_out_link
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.modify(|_, w| unsafe { w.outlink_addr().bits(address) });
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}
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fn has_out_descriptor_error() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_raw.read().outlink_dscr_error_int_raw().bit()
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}
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fn set_out_peripheral(_peripheral: u8) {
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// no-op
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}
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fn start_out() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_out_link.modify(|_, w| w.outlink_start().set_bit());
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}
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fn is_out_done() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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// FIXME this should be out_total_eof_int_raw? but on esp32 this interrupt doesn't seem to fire
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spi.dma_int_raw.read().out_eof_int_raw().bit()
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}
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fn last_out_dscr_address() -> usize {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.out_eof_des_addr.read().dma_out_eof_des_addr().bits() as usize
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}
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fn is_out_eof_interrupt_set() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_raw.read().out_eof_int_raw().bit()
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}
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fn reset_out_eof_interrupt() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_clr.write(|w| {
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w.out_eof_int_clr()
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.set_bit()
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});
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}
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fn set_in_burstmode(burst_mode: bool) {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_conf
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.modify(|_, w| w.indscr_burst_en().bit(burst_mode));
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}
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fn set_in_priority(_priority: DmaPriority) {}
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fn clear_in_interrupts() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_clr.write(|w| {
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w.in_done_int_clr()
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.set_bit()
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.in_err_eof_int_clr()
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.set_bit()
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.in_suc_eof_int_clr()
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.set_bit()
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.inlink_dscr_error_int_clr()
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.set_bit()
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});
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}
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fn reset_in() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_conf.modify(|_, w| w.in_rst().set_bit());
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spi.dma_conf.modify(|_, w| w.in_rst().clear_bit());
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}
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fn set_in_descriptors(address: u32) {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_in_link
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.modify(|_, w| unsafe { w.inlink_addr().bits(address) });
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}
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fn has_in_descriptor_error() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_raw.read().inlink_dscr_error_int_raw().bit()
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}
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fn set_in_peripheral(_peripheral: u8) {
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// no-op
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}
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fn start_in() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_in_link.modify(|_, w| w.inlink_start().set_bit());
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}
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fn is_in_done() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_raw.read().in_done_int_raw().bit()
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}
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fn last_in_dscr_address() -> usize {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.inlink_dscr_bf0.read().dma_inlink_dscr_bf0().bits() as usize
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}
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fn is_listening_in_eof() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_ena.read().in_suc_eof_int_ena().bit_is_set()
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}
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fn is_listening_out_eof() -> bool {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_ena.read().out_total_eof_int_ena().bit_is_set()
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}
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fn listen_in_eof() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_ena.modify(|_, w| w.in_suc_eof_int_ena().set_bit());
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}
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fn listen_out_eof() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_ena.modify(|_, w| w.out_total_eof_int_ena().set_bit());
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}
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fn unlisten_in_eof() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_ena.modify(|_, w| w.in_suc_eof_int_ena().clear_bit());
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}
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fn unlisten_out_eof() {
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let spi = unsafe { &*crate::peripherals::[<SPI $num>]::PTR };
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spi.dma_int_ena.modify(|_, w| w.out_total_eof_int_ena().clear_bit());
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}
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}
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pub struct [<Spi $num DmaChannelTxImpl>] {}
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impl<'a> TxChannel<[<Spi $num DmaChannel>]> for [<Spi $num DmaChannelTxImpl>] {
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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pub struct [<Spi $num DmaChannelRxImpl>] {}
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impl<'a> RxChannel<[<Spi $num DmaChannel>]> for [<Spi $num DmaChannelRxImpl>] {
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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pub struct [<Spi $num DmaChannelCreator>] {}
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impl [<Spi $num DmaChannelCreator>] {
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/// Configure the channel for use
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///
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/// Descriptors should be sized as (BUFFERSIZE / 4092) * 3
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pub fn configure<'a>(
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self,
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burst_mode: bool,
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tx_descriptors: &'a mut [u32],
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rx_descriptors: &'a mut [u32],
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priority: DmaPriority,
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) -> Channel<
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ChannelTx<'a,[<Spi $num DmaChannelTxImpl>], [<Spi $num DmaChannel>]>,
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ChannelRx<'a,[<Spi $num DmaChannelRxImpl>], [<Spi $num DmaChannel>]>,
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[<Spi $num DmaSuitablePeripheral>],
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> {
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let mut tx_impl = [<Spi $num DmaChannelTxImpl>] {};
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tx_impl.init(burst_mode, priority);
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let tx_channel = ChannelTx {
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descriptors: tx_descriptors,
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burst_mode,
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tx_impl: tx_impl,
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write_offset: 0,
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write_descr_ptr: core::ptr::null(),
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available: 0,
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last_seen_handled_descriptor_ptr: core::ptr::null(),
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buffer_start: core::ptr::null(),
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buffer_len: 0,
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_phantom: PhantomData::default(),
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};
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let mut rx_impl = [<Spi $num DmaChannelRxImpl>] {};
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rx_impl.init(burst_mode, priority);
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let rx_channel = ChannelRx {
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descriptors: rx_descriptors,
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burst_mode,
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rx_impl: rx_impl,
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read_descr_ptr: core::ptr::null(),
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available: 0,
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last_seen_handled_descriptor_ptr: core::ptr::null(),
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read_buffer_start: core::ptr::null(),
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_phantom: PhantomData::default(),
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};
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Channel {
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tx: tx_channel,
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rx: rx_channel,
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_phantom: PhantomData::default(),
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}
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}
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}
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}
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};
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}
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macro_rules! ImplI2sChannel {
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($num: literal, $peripheral: literal) => {
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paste::paste! {
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pub struct [<I2s $num DmaChannel>] {}
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impl RegisterAccess for [<I2s $num DmaChannel>] {
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fn init_channel() {
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// nothing to do
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}
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fn set_out_burstmode(burst_mode: bool) {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.lc_conf
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.modify(|_, w| w.outdscr_burst_en().bit(burst_mode));
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}
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fn set_out_priority(_priority: DmaPriority) {}
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fn clear_out_interrupts() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_clr.write(|w| {
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w.out_done_int_clr()
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.set_bit()
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.out_eof_int_clr()
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.set_bit()
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.out_total_eof_int_clr()
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.set_bit()
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.out_dscr_err_int_clr()
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.set_bit()
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});
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}
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fn reset_out() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.lc_conf.modify(|_, w| w.out_rst().set_bit());
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reg_block.lc_conf.modify(|_, w| w.out_rst().clear_bit());
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}
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fn set_out_descriptors(address: u32) {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.out_link
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.modify(|_, w| unsafe { w.outlink_addr().bits(address) });
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}
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fn has_out_descriptor_error() -> bool {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_raw.read().out_dscr_err_int_raw().bit()
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}
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fn set_out_peripheral(_peripheral: u8) {
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// no-op
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}
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fn start_out() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.out_link.modify(|_, w| w.outlink_start().set_bit());
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}
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fn is_out_done() -> bool {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_raw.read().out_done_int_raw().bit()
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}
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fn last_out_dscr_address() -> usize {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.out_eof_des_addr.read().out_eof_des_addr().bits() as usize
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}
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fn is_out_eof_interrupt_set() -> bool {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_raw.read().out_eof_int_raw().bit()
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}
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fn reset_out_eof_interrupt() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_clr.write(|w| {
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w.out_eof_int_clr()
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.set_bit()
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});
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}
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fn set_in_burstmode(burst_mode: bool) {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.lc_conf
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.modify(|_, w| w.indscr_burst_en().bit(burst_mode));
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}
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fn set_in_priority(_priority: DmaPriority) {}
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fn clear_in_interrupts() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_clr.write(|w| {
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w.in_done_int_clr()
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.set_bit()
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.in_err_eof_int_clr()
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.set_bit()
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.in_suc_eof_int_clr()
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.set_bit()
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.in_dscr_err_int_clr()
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.set_bit()
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});
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}
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fn reset_in() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.lc_conf.modify(|_, w| w.in_rst().set_bit());
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reg_block.lc_conf.modify(|_, w| w.in_rst().clear_bit());
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}
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fn set_in_descriptors(address: u32) {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.in_link
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.modify(|_, w| unsafe { w.inlink_addr().bits(address) });
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}
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fn has_in_descriptor_error() -> bool {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_raw.read().in_dscr_err_int_raw().bit()
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}
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fn set_in_peripheral(_peripheral: u8) {
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// no-op
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}
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fn start_in() {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.in_link.modify(|_, w| w.inlink_start().set_bit());
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}
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fn is_in_done() -> bool {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.int_raw.read().in_done_int_raw().bit()
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}
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fn last_in_dscr_address() -> usize {
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let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR };
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reg_block.inlink_dscr_bf0.read().inlink_dscr_bf0().bits() as usize
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}
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fn is_listening_in_eof() -> bool {
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todo!()
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}
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fn is_listening_out_eof() -> bool {
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todo!()
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}
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fn listen_in_eof() {
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todo!()
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}
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fn listen_out_eof() {
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todo!()
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}
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fn unlisten_in_eof() {
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todo!()
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}
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fn unlisten_out_eof() {
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todo!()
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}
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}
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pub struct [<I2s $num DmaChannelTxImpl>] {}
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impl<'a> TxChannel<[<I2s $num DmaChannel>]> for [<I2s $num DmaChannelTxImpl>] {
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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pub struct [<I2s $num DmaChannelRxImpl>] {}
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impl<'a> RxChannel<[<I2s $num DmaChannel>]> for [<I2s $num DmaChannelRxImpl>] {
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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pub struct [<I2s $num DmaChannelCreator>] {}
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impl [<I2s $num DmaChannelCreator>] {
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/// Configure the channel for use
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///
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/// Descriptors should be sized as (BUFFERSIZE / 4092) * 3
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pub fn configure<'a>(
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self,
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burst_mode: bool,
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tx_descriptors: &'a mut [u32],
|
|
rx_descriptors: &'a mut [u32],
|
|
priority: DmaPriority,
|
|
) -> Channel<
|
|
ChannelTx<'a,[<I2s $num DmaChannelTxImpl>], [<I2s $num DmaChannel>]>,
|
|
ChannelRx<'a,[<I2s $num DmaChannelRxImpl>], [<I2s $num DmaChannel>]>,
|
|
[<I2s $num DmaSuitablePeripheral>],
|
|
> {
|
|
let mut tx_impl = [<I2s $num DmaChannelTxImpl>] {};
|
|
tx_impl.init(burst_mode, priority);
|
|
|
|
let tx_channel = ChannelTx {
|
|
descriptors: tx_descriptors,
|
|
burst_mode,
|
|
tx_impl: tx_impl,
|
|
write_offset: 0,
|
|
write_descr_ptr: core::ptr::null(),
|
|
available: 0,
|
|
last_seen_handled_descriptor_ptr: core::ptr::null(),
|
|
buffer_start: core::ptr::null(),
|
|
buffer_len: 0,
|
|
_phantom: PhantomData::default(),
|
|
};
|
|
|
|
let mut rx_impl = [<I2s $num DmaChannelRxImpl>] {};
|
|
rx_impl.init(burst_mode, priority);
|
|
|
|
let rx_channel = ChannelRx {
|
|
descriptors: rx_descriptors,
|
|
burst_mode,
|
|
rx_impl: rx_impl,
|
|
read_descr_ptr: core::ptr::null(),
|
|
available: 0,
|
|
last_seen_handled_descriptor_ptr: core::ptr::null(),
|
|
read_buffer_start: core::ptr::null(),
|
|
_phantom: PhantomData::default(),
|
|
};
|
|
|
|
Channel {
|
|
tx: tx_channel,
|
|
rx: rx_channel,
|
|
_phantom: PhantomData::default(),
|
|
}
|
|
}
|
|
}
|
|
}
|
|
};
|
|
}
|
|
|
|
pub struct Spi2DmaSuitablePeripheral {}
|
|
impl PeripheralMarker for Spi2DmaSuitablePeripheral {}
|
|
impl SpiPeripheral for Spi2DmaSuitablePeripheral {}
|
|
impl Spi2Peripheral for Spi2DmaSuitablePeripheral {}
|
|
|
|
pub struct Spi3DmaSuitablePeripheral {}
|
|
impl PeripheralMarker for Spi3DmaSuitablePeripheral {}
|
|
impl SpiPeripheral for Spi3DmaSuitablePeripheral {}
|
|
impl Spi3Peripheral for Spi3DmaSuitablePeripheral {}
|
|
|
|
ImplSpiChannel!(2);
|
|
ImplSpiChannel!(3);
|
|
|
|
pub struct I2s0DmaSuitablePeripheral {}
|
|
impl PeripheralMarker for I2s0DmaSuitablePeripheral {}
|
|
impl I2sPeripheral for I2s0DmaSuitablePeripheral {}
|
|
impl I2s0Peripheral for I2s0DmaSuitablePeripheral {}
|
|
|
|
#[cfg(esp32)]
|
|
ImplI2sChannel!(0, "I2S0");
|
|
|
|
#[cfg(esp32s2)]
|
|
ImplI2sChannel!(0, "I2S");
|
|
|
|
pub struct I2s1DmaSuitablePeripheral {}
|
|
impl PeripheralMarker for I2s1DmaSuitablePeripheral {}
|
|
impl I2sPeripheral for I2s1DmaSuitablePeripheral {}
|
|
impl I2s1Peripheral for I2s1DmaSuitablePeripheral {}
|
|
|
|
#[cfg(esp32)]
|
|
ImplI2sChannel!(1, "I2S1");
|
|
|
|
/// DMA Peripheral
|
|
///
|
|
/// This offers the available DMA channels.
|
|
pub struct Dma<'d> {
|
|
_inner: PeripheralRef<'d, crate::system::Dma>,
|
|
pub spi2channel: Spi2DmaChannelCreator,
|
|
pub spi3channel: Spi3DmaChannelCreator,
|
|
pub i2s0channel: I2s0DmaChannelCreator,
|
|
#[cfg(esp32)]
|
|
pub i2s1channel: I2s1DmaChannelCreator,
|
|
}
|
|
|
|
impl<'d> Dma<'d> {
|
|
/// Create a DMA instance.
|
|
pub fn new(
|
|
dma: impl crate::peripheral::Peripheral<P = crate::system::Dma> + 'd,
|
|
peripheral_clock_control: &mut PeripheralClockControl,
|
|
) -> Dma<'d> {
|
|
peripheral_clock_control.enable(Peripheral::Dma);
|
|
|
|
Dma {
|
|
_inner: dma.into_ref(),
|
|
spi2channel: Spi2DmaChannelCreator {},
|
|
spi3channel: Spi3DmaChannelCreator {},
|
|
i2s0channel: I2s0DmaChannelCreator {},
|
|
#[cfg(esp32)]
|
|
i2s1channel: I2s1DmaChannelCreator {},
|
|
}
|
|
}
|
|
}
|