db409ffe7b
* Unify the system peripheral Whilst the PCR, SYSTEM and DPORT peripherals are different, we currently use them all in the same way. This PR unifies the peripheral name in the hal to `SYSTEM`. The idea is that they all do the same sort of thing, so we can collect them under the same name, and later down the line we can being to expose differences under an extended API. The benifits to this are imo quite big, the examples now are all identical, which makes things easier for esp-wifi, and paves a path towards the multichip hal. Why not do this in the PAC? Imo the pac should be as close to the hardware as possible, and the HAL is where we should abstractions such as this. * changelog
109 lines
3.1 KiB
Rust
109 lines
3.1 KiB
Rust
//! SPI loopback test
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//!
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//! Folowing pins are used:
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//! SCLK GPIO19
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//! MISO GPIO25
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//! MOSI GPIO23
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//! CS GPIO22
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//!
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//! Depending on your target and the board you are using you have to change the
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//! pins.
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//!
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//! This example transfers data via SPI.
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//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
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//! data.
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#![no_std]
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#![no_main]
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use embedded_hal_1::spi::SpiBus;
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use esp32_hal::{
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clock::ClockControl,
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gpio::IO,
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peripherals::Peripherals,
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prelude::*,
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spi::{Spi, SpiMode},
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Delay,
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};
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use esp_backtrace as _;
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use esp_println::{print, println};
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio19;
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let miso = io.pins.gpio25;
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let mosi = io.pins.gpio23;
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let cs = io.pins.gpio22;
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let mut spi = Spi::new(
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peripherals.SPI2,
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sclk,
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mosi,
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miso,
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cs,
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1000u32.kHz(),
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SpiMode::Mode0,
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&clocks,
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);
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let mut delay = Delay::new(&clocks);
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println!("=== SPI example with embedded-hal-1 traits ===");
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loop {
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// --- Symmetric transfer (Read as much as we write) ---
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print!("Starting symmetric transfer...");
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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SpiBus::transfer(&mut spi, &mut read[..], &write[..]).expect("Symmetric transfer failed");
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assert_eq!(write, read);
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Asymmetric transfer (Read more than we write) ---
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print!("Starting asymetric transfer (read > write)...");
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let mut read: [u8; 4] = [0x00; 4];
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SpiBus::transfer(&mut spi, &mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer ---
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// Only your RAM is the limit!
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print!("Starting huge transfer...");
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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SpiBus::transfer(&mut spi, &mut read[..], &write[..]).expect("Huge transfer failed");
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assert_eq!(write, read);
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer in-place (No additional allocation
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// needed) ---
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print!("Starting huge transfer (in-place)...");
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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SpiBus::transfer_in_place(&mut spi, &mut write[..]).expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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}
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}
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