984b7fc042
* Create an `soc` module with a submodule for each chip, move `peripherals` in * Move the `cpu_control` module into `soc` * Move the `efuse` module into `soc` * Refactor type definitions from `gpio` module into `soc` * Put all embassy-related files in a common directory * Change visibility of `GpioPin` constructor
126 lines
3.4 KiB
Rust
126 lines
3.4 KiB
Rust
//! USB OTG full-speed peripheral
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pub use esp_synopsys_usb_otg::UsbBus;
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use esp_synopsys_usb_otg::UsbPeripheral;
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use crate::{
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gpio::InputSignal,
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peripheral::{Peripheral, PeripheralRef},
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peripherals,
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system::{Peripheral as PeripheralEnable, PeripheralClockControl},
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};
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#[doc(hidden)]
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pub trait UsbSel {}
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#[doc(hidden)]
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pub trait UsbDp {}
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#[doc(hidden)]
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pub trait UsbDm {}
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pub struct USB<'d, S, P, M>
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where
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S: UsbSel + Send + Sync,
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P: UsbDp + Send + Sync,
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M: UsbDm + Send + Sync,
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{
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_usb0: PeripheralRef<'d, peripherals::USB0>,
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_usb_sel: PeripheralRef<'d, S>,
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_usb_dp: PeripheralRef<'d, P>,
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_usb_dm: PeripheralRef<'d, M>,
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}
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impl<'d, S, P, M> USB<'d, S, P, M>
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where
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S: UsbSel + Send + Sync,
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P: UsbDp + Send + Sync,
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M: UsbDm + Send + Sync,
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{
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pub fn new(
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usb0: impl Peripheral<P = peripherals::USB0> + 'd,
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usb_sel: impl Peripheral<P = S> + 'd,
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usb_dp: impl Peripheral<P = P> + 'd,
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usb_dm: impl Peripheral<P = M> + 'd,
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peripheral_clock_control: &mut PeripheralClockControl,
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) -> Self {
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crate::into_ref!(usb_sel, usb_dp, usb_dm);
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peripheral_clock_control.enable(PeripheralEnable::Usb);
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Self {
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_usb0: usb0.into_ref(),
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_usb_sel: usb_sel,
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_usb_dp: usb_dp,
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_usb_dm: usb_dm,
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}
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}
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}
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unsafe impl<'d, S, P, M> Sync for USB<'d, S, P, M>
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where
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S: UsbSel + Send + Sync,
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P: UsbDp + Send + Sync,
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M: UsbDm + Send + Sync,
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{
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}
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unsafe impl<'d, S, P, M> UsbPeripheral for USB<'d, S, P, M>
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where
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S: UsbSel + Send + Sync,
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P: UsbDp + Send + Sync,
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M: UsbDm + Send + Sync,
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{
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const REGISTERS: *const () = peripherals::USB0::ptr() as *const ();
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const HIGH_SPEED: bool = false;
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const FIFO_DEPTH_WORDS: usize = 256;
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const ENDPOINT_COUNT: usize = 5;
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fn enable() {
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unsafe {
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let usb_wrap = &*peripherals::USB_WRAP::PTR;
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usb_wrap.otg_conf.modify(|_, w| {
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w.usb_pad_enable()
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.set_bit()
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.phy_sel()
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.clear_bit()
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.clk_en()
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.set_bit()
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.ahb_clk_force_on()
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.set_bit()
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.phy_clk_force_on()
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.set_bit()
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});
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#[cfg(esp32s3)]
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{
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let rtc = &*peripherals::RTC_CNTL::PTR;
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rtc.usb_conf
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.modify(|_, w| w.sw_hw_usb_phy_sel().set_bit().sw_usb_phy_sel().set_bit());
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}
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crate::gpio::connect_high_to_peripheral(InputSignal::USB_OTG_IDDIG); // connected connector is mini-B side
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crate::gpio::connect_high_to_peripheral(InputSignal::USB_SRP_BVALID); // HIGH to force USB device mode
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crate::gpio::connect_high_to_peripheral(InputSignal::USB_OTG_VBUSVALID); // receiving a valid Vbus from device
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crate::gpio::connect_low_to_peripheral(InputSignal::USB_OTG_AVALID);
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usb_wrap.otg_conf.modify(|_, w| {
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w.pad_pull_override()
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.set_bit()
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.dp_pullup()
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.set_bit()
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.dp_pulldown()
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.clear_bit()
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.dm_pullup()
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.clear_bit()
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.dm_pulldown()
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.clear_bit()
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});
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}
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}
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fn ahb_frequency_hz(&self) -> u32 {
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// unused
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80_000_000
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}
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}
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