67e9c60a23
* Simplify the `Delay` driver, derive `Clone` and `Copy` The RISC-V and Xtensa implementations of the delay functionality are both safe to access from multiple contexts, and the `Delay` struct does not take ownership of any peripheral struct, so `Delay` is safe to clone/copy * Update the CHANGELOG
96 lines
2.6 KiB
Rust
96 lines
2.6 KiB
Rust
//! Delay driver implement the blocking [DelayMs] and [DelayUs] traits from
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//! [embedded-hal].
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//!
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//! The delays are implemented in a "best-effort" way, meaning that the CPU will
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//! block for at least the amount of time specified, but accuracy can be
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//! affected by many factors, including interrupt usage.
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//!
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//! [DelayMs]: embedded_hal::blocking::delay::DelayMs
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//! [DelayUs]: embedded_hal::blocking::delay::DelayUs
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//! [embedded-hal]: https://docs.rs/embedded-hal/latest/embedded_hal/
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use fugit::HertzU64;
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/// Delay driver
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///
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/// Uses the `SYSTIMER` peripheral internally for RISC-V devices, and the
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/// built-in Xtensa timer for Xtensa devices.
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#[derive(Clone, Copy)]
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pub struct Delay {
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freq: HertzU64,
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}
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impl<T> embedded_hal::blocking::delay::DelayMs<T> for Delay
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where
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T: Into<u32>,
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{
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fn delay_ms(&mut self, ms: T) {
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for _ in 0..ms.into() {
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self.delay(1000u32);
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}
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}
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}
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impl<T> embedded_hal::blocking::delay::DelayUs<T> for Delay
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where
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T: Into<u32>,
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{
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fn delay_us(&mut self, us: T) {
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self.delay(us.into());
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}
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}
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#[cfg(feature = "eh1")]
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impl embedded_hal_1::delay::DelayUs for Delay {
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fn delay_us(&mut self, us: u32) {
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self.delay(us);
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}
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}
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#[cfg(riscv)]
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mod delay {
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use super::*;
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use crate::{clock::Clocks, systimer::SystemTimer};
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impl Delay {
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/// Create a new `Delay` instance
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pub fn new(clocks: &Clocks) -> Self {
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// The counters and comparators are driven using `XTAL_CLK`.
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// The average clock frequency is fXTAL_CLK/2.5, which is 16 MHz.
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// The timer counting is incremented by 1/16 μs on each `CNT_CLK` cycle.
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Self {
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freq: HertzU64::MHz(clocks.xtal_clock.to_MHz() as u64 * 10 / 25),
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}
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}
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/// Delay for the specified number of microseconds
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pub fn delay(&self, us: u32) {
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let t0 = SystemTimer::now();
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let clocks = us as u64 * (self.freq / HertzU64::MHz(1));
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while SystemTimer::now().wrapping_sub(t0) & SystemTimer::BIT_MASK <= clocks {}
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}
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}
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}
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#[cfg(xtensa)]
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mod delay {
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use super::*;
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use crate::clock::Clocks;
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impl Delay {
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/// Create a new `Delay` instance
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pub fn new(clocks: &Clocks) -> Self {
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Self {
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freq: clocks.cpu_clock.into(),
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}
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}
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/// Delay for the specified number of microseconds
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pub fn delay(&self, us: u32) {
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let clocks = us as u64 * (self.freq / HertzU64::MHz(1));
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xtensa_lx::timer::delay(clocks as u32);
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}
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}
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}
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