c1fa400e7c
* RISCV: Separate PLIC and non-PLIC * De-duplicate code * Write 0 to INTR_MAP again to disable peripheral interrupts * Limit visibility of `get_assigned_cpu_interrupt`
187 lines
4.7 KiB
Rust
187 lines
4.7 KiB
Rust
use std::{env, fs, path::PathBuf};
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fn main() {
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let esp32 = cfg!(feature = "esp32");
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let esp32c2 = cfg!(feature = "esp32c2");
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let esp32c3 = cfg!(feature = "esp32c3");
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let esp32c6 = cfg!(feature = "esp32c6");
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let esp32s2 = cfg!(feature = "esp32s2");
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let esp32s3 = cfg!(feature = "esp32s3");
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// Ensure that exactly one chip has been specified
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let chip_features = [esp32, esp32c2, esp32c3, esp32c6, esp32s2, esp32s3];
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match chip_features.iter().filter(|&&f| f).count() {
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1 => {}
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n => panic!("Exactly 1 chip must be enabled via its Cargo feature, {n} provided"),
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}
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if cfg!(feature = "esp32") && cfg!(feature = "esp32_40mhz") && cfg!(feature = "esp32_26mhz") {
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panic!("Only one xtal speed feature can be selected");
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}
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if cfg!(feature = "esp32c2")
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&& cfg!(feature = "esp32c2_40mhz")
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&& cfg!(feature = "esp32c2_26mhz")
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{
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panic!("Only one xtal speed feature can be selected");
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}
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// Define all required configuration symbols for the enabled chip.
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//
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// When adding a new device, at the bare minimum the following symbols MUST be
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// defined:
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// - the name of the device
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// - the architecture ('riscv' or 'xtensa')
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// - the core count ('single_core' or 'multi_core')
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//
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// Additionally, the following symbols MAY be defined if present:
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// - 'aes'
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// - 'dac'
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// - 'gdma'
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// - 'i2c1'
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// - 'i2s'
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// - 'large_intr_status'
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// - 'mcpwm'
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// - 'pcnt'
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// - 'pdma'
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// - 'plic'
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// - 'radio'
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// - 'rmt'
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// - 'spi3'
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// - 'systimer'
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// - 'timg0'
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// - 'timg1'
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// - 'twai'
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// - 'uart2'
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// - 'usb_otg'
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// - 'usb_serial_jtag'
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//
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// New symbols can be added as needed, but please be sure to update both this
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// comment and the required vectors below.
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let symbols = if esp32 {
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vec![
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"esp32",
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"xtensa",
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"multi_core",
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"aes",
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"dac",
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"i2c1",
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"i2s",
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"mcpwm",
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"pcnt",
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"pdma",
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"radio",
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"rmt",
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"spi3",
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"timg0",
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"timg1",
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"uart2",
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]
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} else if esp32c2 {
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vec![
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"esp32c2",
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"riscv",
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"single_core",
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"gdma",
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"radio",
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"systimer",
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"timg0",
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]
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} else if esp32c3 {
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vec![
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"esp32c3",
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"riscv",
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"single_core",
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"aes",
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"gdma",
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"i2s",
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"radio",
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"rmt",
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"spi3",
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"systimer",
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"timg0",
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"timg1",
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"twai",
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"usb_serial_jtag",
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]
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} else if esp32c6 {
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vec![
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"esp32c6",
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"riscv",
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"single_core",
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"aes",
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"gdma",
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"i2s",
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"large_intr_status",
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"mcpwm",
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"pcnt",
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"plic",
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"radio",
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"rmt",
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"systimer",
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"timg0",
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"timg1",
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"twai",
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"usb_serial_jtag",
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]
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} else if esp32s2 {
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vec![
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"esp32s2",
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"xtensa",
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"single_core",
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"aes",
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"dac",
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"i2c1",
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"i2s",
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"pcnt",
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"pdma",
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"radio",
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"rmt",
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"spi3",
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"systimer",
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"timg0",
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"timg1",
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"usb_otg",
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]
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} else if esp32s3 {
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vec![
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"esp32s3",
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"xtensa",
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"multi_core",
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"aes",
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"gdma",
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"i2c1",
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"i2s",
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"mcpwm",
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"pcnt",
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"radio",
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"rmt",
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"spi3",
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"systimer",
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"timg0",
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"timg1",
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"twai",
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"uart2",
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"usb_otg",
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"usb_serial_jtag",
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]
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} else {
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unreachable!(); // We've already confirmed exactly one chip was selected
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};
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for symbol in symbols {
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println!("cargo:rustc-cfg={symbol}");
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}
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// Place all linker scripts in `OUT_DIR`, and instruct Cargo how to find these
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// files:
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let out = PathBuf::from(env::var_os("OUT_DIR").unwrap());
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println!("cargo:rustc-link-search={}", out.display());
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if esp32 || esp32s2 || esp32s3 {
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fs::copy("ld/xtensa/hal-defaults.x", out.join("hal-defaults.x")).unwrap();
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fs::copy("ld/xtensa/rom.x", out.join("alias.x")).unwrap();
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} else {
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fs::copy("ld/riscv/hal-defaults.x", out.join("hal-defaults.x")).unwrap();
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}
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}
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