3444476eb2
The ROM code _data_ section is loaded into the middle of the DRAM address space, unlike the other chips where it is loaded at the end. Therefore subtracting the previously "reserved" section from heap end could actually corrupt the ROM data section. For the ESP32, the DRAM block has been split into two individual segments, with some reserved segments in the middle (addresses taken from esp-idf). At the moment we don't use the second segment at all in esp-hal, but we could utilize it in esp-wifi for placing the internal allocator for example.
58 lines
2.8 KiB
Plaintext
58 lines
2.8 KiB
Plaintext
/* This memory map assumes the flash cache is on;
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the blocks used are excluded from the various memory ranges
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see: https://github.com/espressif/esp-idf/blob/5b1189570025ba027f2ff6c2d91f6ffff3809cc2/components/heap/port/esp32/memory_layout.c
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for details
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*/
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/* override entry point */
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ENTRY(ESP32Reset)
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INCLUDE "memory_extras.x"
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/* Specify main memory areas */
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MEMORY
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{
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reserved_cache_seg : ORIGIN = 0x40070000, len = 64k /* SRAM0; reserved for usage as flash cache*/
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vectors_seg ( RX ) : ORIGIN = 0x40080000, len = 1k /* SRAM0 */
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iram_seg ( RX ) : ORIGIN = 0x40080400, len = 128k-0x400 /* SRAM0 */
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reserved_for_rom_seg : ORIGIN = 0x3FFAE000, len = 8k /* SRAM2; reserved for usage by the ROM */
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dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM, len = 176k - RESERVE_DRAM /* SRAM2+1; first 64kB used by BT if enable */
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/*
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* The following values come from the heap allocator in esp-idf: https://github.com/espressif/esp-idf/blob/ab63aaa4a24a05904da2862d627f3987ecbeafd0/components/heap/port/esp32/memory_layout.c#L137-L157
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* The segment dram2_seg after the rom data space is not mentioned in the esp32 linker scripts in esp-idf, instead the space after is used as heap space.
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* It seems not all rom data space is reserved, but only "core"/"important" ROM functions that may be called after booting from ROM.
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*/
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reserved_rom_data_pro : ORIGIN = 0X3FFE0000, len = 1088
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reserved_rom_data_app : ORIGIN = 0X3FFE3F20, len = 1072
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dram2_seg : ORIGIN = 0x3FFE4350, len = 111k /* the rest of DRAM after the rom data segments in the middle */
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/* external flash
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The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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irom_seg ( RX ) : ORIGIN = 0x400D0020, len = 3M - 0x20
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drom_seg ( R ) : ORIGIN = 0x3F400020, len = 4M - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
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rtc_fast_iram_seg(RWX) : ORIGIN = 0x400C0000, len = 8k
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/* RTC fast memory (same block as above), viewed from data bus. Only for core 0 (PRO_CPU) */
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rtc_fast_dram_seg(RW) : ORIGIN = 0x3FF80000 + RESERVE_RTC_FAST, len = 8k - RESERVE_RTC_FAST
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : ORIGIN = 0x50000000 + RESERVE_RTC_SLOW, len = 8k - RESERVE_RTC_SLOW
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/* external memory, including data and text,
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4MB is the maximum, if external psram is bigger, paging is required */
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psram_seg(RWX) : ORIGIN = 0x3F800000, len = 4M
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}
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