esp-hal/hil-test/tests/spi_full_duplex.rs
Sergio Gasquez Arcos baea915935
Add HIL testing (#1297)
* Create the `hil-test` package

* Add a simple integration test to verify basic GPIO functionality

* WIP

* feat: Update with esp-hal unification

* build: Update dependencies

* feat: Add a simple CI workflow test

* ci: Avoid using a gh-hosted-runner to build

* ci: Remove building bins in gh-hosted-runner

* ci: Remove HIL Gpio CI test

* ci: Test all the available tests

* test: Add spi_full_duplex test

* docs: Add documentation

* test: Add uart test

* style: Remove unused imports

* docs: Update wiring, document H2 VM

* ci: Enable H2 tests

* ci: Add rust-cache action

* docs: Document H2 vm

* test: Add timeout

* ci: Enable ESP32-C3 tests

* feat: Add timeouts

* feat: Add aes test

* ci: Avoid running CI workflow when we change hil-test stuff

* test: Remove warnings

* feat: Address feedback

* feat: Update features names and spi methods

* ci: Remove rust-cache action

* Update HIL to probe-rs#2292 (#1307)

* feat: Update probe-rs/embedded-test to probe-rs#2292

* feat: Remove lib

* ci: Use a matrix

* ci: Enable ESP32C3

* feat: Add a way to cfg away test for unsuported peripherals

* ci: Update trigger conditions

* feat: Update pins to make it work on s3

* feat: Changes enabling S3

* feat: Remove log feature

* feat: Adapt for rebase

* feat: Remove env

* feat: enable S3

* chore: Remove todo

* build: Pin dependencies

* feat: Add target alias

* docs: Update readme

* fix: Fix traits imports after rebase. Use debug

* build: Remove lto

* feat: Build tests on release mode

---------

Co-authored-by: Jesse Braham <jesse@beta7.io>
2024-03-21 14:28:27 +00:00

116 lines
2.7 KiB
Rust

//! SPI Full Duplex Test
//!
//! Folowing pins are used:
//! SCLK GPIO0
//! MISO GPIO2
//! MOSI GPIO4
//! CS GPIO5
//!
//! Connect MISO (GPIO2) and MOSI (GPIO4) pins.
#![no_std]
#![no_main]
use defmt_rtt as _;
use embedded_hal::spi::SpiBus;
use esp_hal::{
clock::ClockControl,
gpio::IO,
peripherals::Peripherals,
prelude::*,
spi::{master::Spi, FullDuplexMode, SpiMode},
};
struct Context {
spi: Spi<'static, esp_hal::peripherals::SPI2, FullDuplexMode>,
}
impl Context {
pub fn init() -> Self {
let peripherals = Peripherals::take();
let system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio0;
let miso = io.pins.gpio2;
let mosi = io.pins.gpio4;
let cs = io.pins.gpio5;
let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0, &clocks).with_pins(
Some(sclk),
Some(mosi),
Some(miso),
Some(cs),
);
Context { spi }
}
}
#[cfg(test)]
#[embedded_test::tests]
mod tests {
use defmt::assert_eq;
use super::*;
#[init]
fn init() -> Context {
Context::init()
}
#[test]
fn test_symestric_transfer(mut ctx: Context) {
let write = [0xde, 0xad, 0xbe, 0xef];
let mut read: [u8; 4] = [0x00u8; 4];
ctx.spi
.transfer(&mut read[..], &write[..])
.expect("Symmetric transfer failed");
assert_eq!(write, read);
}
#[test]
fn test_asymestric_transfer(mut ctx: Context) {
let write = [0xde, 0xad, 0xbe, 0xef];
let mut read: [u8; 4] = [0x00; 4];
ctx.spi
.transfer(&mut read[0..2], &write[..])
.expect("Asymmetric transfer failed");
assert_eq!(write[0], read[0]);
assert_eq!(read[2], 0x00u8);
}
#[test]
fn test_symestric_transfer_huge_buffer(mut ctx: Context) {
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
let mut read = [0x00u8; 4096];
ctx.spi
.transfer(&mut read[..], &write[..])
.expect("Huge transfer failed");
assert_eq!(write, read);
}
#[test]
#[timeout(3)]
fn test_symestric_transfer_huge_buffer_no_alloc(mut ctx: Context) {
let mut write = [0x55u8; 4096];
for byte in 0..write.len() {
write[byte] = byte as u8;
}
ctx.spi
.transfer_in_place(&mut write[..])
.expect("Huge transfer failed");
for byte in 0..write.len() {
assert_eq!(write[byte], byte as u8);
}
}
}