* Create the `hil-test` package * Add a simple integration test to verify basic GPIO functionality * WIP * feat: Update with esp-hal unification * build: Update dependencies * feat: Add a simple CI workflow test * ci: Avoid using a gh-hosted-runner to build * ci: Remove building bins in gh-hosted-runner * ci: Remove HIL Gpio CI test * ci: Test all the available tests * test: Add spi_full_duplex test * docs: Add documentation * test: Add uart test * style: Remove unused imports * docs: Update wiring, document H2 VM * ci: Enable H2 tests * ci: Add rust-cache action * docs: Document H2 vm * test: Add timeout * ci: Enable ESP32-C3 tests * feat: Add timeouts * feat: Add aes test * ci: Avoid running CI workflow when we change hil-test stuff * test: Remove warnings * feat: Address feedback * feat: Update features names and spi methods * ci: Remove rust-cache action * Update HIL to probe-rs#2292 (#1307) * feat: Update probe-rs/embedded-test to probe-rs#2292 * feat: Remove lib * ci: Use a matrix * ci: Enable ESP32C3 * feat: Add a way to cfg away test for unsuported peripherals * ci: Update trigger conditions * feat: Update pins to make it work on s3 * feat: Changes enabling S3 * feat: Remove log feature * feat: Adapt for rebase * feat: Remove env * feat: enable S3 * chore: Remove todo * build: Pin dependencies * feat: Add target alias * docs: Update readme * fix: Fix traits imports after rebase. Use debug * build: Remove lto * feat: Build tests on release mode --------- Co-authored-by: Jesse Braham <jesse@beta7.io>
116 lines
2.7 KiB
Rust
116 lines
2.7 KiB
Rust
//! SPI Full Duplex Test
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//!
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//! Folowing pins are used:
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//! SCLK GPIO0
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//! MISO GPIO2
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//! MOSI GPIO4
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//! CS GPIO5
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//!
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//! Connect MISO (GPIO2) and MOSI (GPIO4) pins.
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#![no_std]
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#![no_main]
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use defmt_rtt as _;
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use embedded_hal::spi::SpiBus;
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use esp_hal::{
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clock::ClockControl,
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gpio::IO,
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peripherals::Peripherals,
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prelude::*,
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spi::{master::Spi, FullDuplexMode, SpiMode},
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};
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struct Context {
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spi: Spi<'static, esp_hal::peripherals::SPI2, FullDuplexMode>,
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}
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impl Context {
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pub fn init() -> Self {
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let peripherals = Peripherals::take();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio0;
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let miso = io.pins.gpio2;
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let mosi = io.pins.gpio4;
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let cs = io.pins.gpio5;
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let spi = Spi::new(peripherals.SPI2, 1000u32.kHz(), SpiMode::Mode0, &clocks).with_pins(
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Some(sclk),
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Some(mosi),
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Some(miso),
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Some(cs),
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);
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Context { spi }
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}
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}
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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Context::init()
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}
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#[test]
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fn test_symestric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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ctx.spi
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.transfer(&mut read[..], &write[..])
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.expect("Symmetric transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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fn test_asymestric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00; 4];
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ctx.spi
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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}
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#[test]
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fn test_symestric_transfer_huge_buffer(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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ctx.spi
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_symestric_transfer_huge_buffer_no_alloc(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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ctx.spi
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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}
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}
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