2a4e58a230
* Remove `read_bytes` function, rename `drain_fifo` to `read_bytes` * Update migration guide * Update `CHANGELOG.md` * Use `crate::interrupt::free` in `read_byte` * Fix HIL test * Only use `crate::interrupt:free` for ESP32
68 lines
1.5 KiB
Rust
68 lines
1.5 KiB
Rust
//! UART TX/RX Test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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#![no_std]
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#![no_main]
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use esp_hal::{
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uart::{self, UartRx, UartTx},
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Blocking,
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};
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use hil_test as _;
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use nb::block;
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struct Context {
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rx: UartRx<'static, Blocking>,
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tx: UartTx<'static, Blocking>,
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}
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3)]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (rx, tx) = hil_test::common_test_pins!(peripherals);
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let tx = UartTx::new(peripherals.UART0, uart::Config::default(), tx).unwrap();
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let rx = UartRx::new(peripherals.UART1, uart::Config::default(), rx).unwrap();
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Context { rx, tx }
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}
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#[test]
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fn test_send_receive(mut ctx: Context) {
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let byte = [0x42];
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ctx.tx.flush().unwrap();
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ctx.tx.write_bytes(&byte).unwrap();
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let read = block!(ctx.rx.read_byte());
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assert_eq!(read, Ok(0x42));
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}
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#[test]
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fn test_send_receive_bytes(mut ctx: Context) {
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let bytes = [0x42, 0x43, 0x44];
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let mut buf = [0u8; 3];
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ctx.tx.flush().unwrap();
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ctx.tx.write_bytes(&bytes).unwrap();
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let mut bytes_read = 0;
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loop {
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bytes_read += ctx.rx.read_bytes(&mut buf[bytes_read..]);
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if bytes_read == 3 {
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break;
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}
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}
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assert_eq!(bytes_read, 3);
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assert_eq!(buf, bytes);
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}
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}
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