9a894879a7
* PARL_IO RX for ESP32-C6 / H2 * Add PARL_IO RX to README.md * Remove logger-init from PARL_IO_RX examples
563 lines
22 KiB
Rust
563 lines
22 KiB
Rust
//! # Direct Memory Access
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//!
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//! ## Overview
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//! The GDMA (General DMA) module is a part of the DMA (Direct Memory Access)
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//! driver for ESP chips. Of the Espressif chip range, every chip except of
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//! `ESP32` and `ESP32-S2` uses the `GDMA` type of direct memory access.
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//!
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//! DMA is a hardware feature that allows data transfer between memory and
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//! peripherals without involving the CPU, resulting in efficient data movement
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//! and reduced CPU overhead. The `GDMA` module provides multiple DMA channels,
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//! each capable of managing data transfer for various peripherals.
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//!
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//! This module implements DMA channels, such as `channel0`, `channel1` and so
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//! on. Each channel struct implements the `ChannelTypes` trait, which provides
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//! associated types for peripheral configuration.
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//!
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//! GDMA peripheral can be initializes using the `new` function, which requires
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//! a DMA peripheral instance and a clock control reference. ```no_run
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//! let dma = Gdma::new(peripherals.DMA, &mut system.peripheral_clock_control);
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//! ```
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//!
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//! <em>PS: Note that the number of DMA channels is chip-specific.</em>
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use crate::{
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dma::*,
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peripheral::PeripheralRef,
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system::{Peripheral, PeripheralClockControl},
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};
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macro_rules! impl_channel {
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($num: literal) => {
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paste::paste! {
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#[non_exhaustive]
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pub struct [<Channel $num>] {}
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impl ChannelTypes for [<Channel $num>] {
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type P = [<SuitablePeripheral $num>];
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type Tx<'a> = ChannelTx<'a, [<Channel $num TxImpl>], [<Channel $num>]>;
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type Rx<'a> = ChannelRx<'a, [<Channel $num RxImpl>], [<Channel $num>]>;
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}
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impl RegisterAccess for [<Channel $num>] {
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fn init_channel() {
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// nothing special to be done here
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}
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fn set_out_burstmode(burst_mode: bool) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_conf0_ch $num>].modify(|_,w| {
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w.out_data_burst_en().bit(burst_mode)
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.outdscr_burst_en().bit(burst_mode)
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});
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}
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fn set_out_priority(priority: DmaPriority) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_pri_ch $num>].write(|w| {
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w.tx_pri().variant(priority as u8)
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});
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}
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fn clear_out_interrupts() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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dma.[<int_clr_ch $num>].write(|w| {
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w.out_eof()
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.set_bit()
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.out_dscr_err()
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.set_bit()
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.out_done()
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.set_bit()
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.out_total_eof()
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.set_bit()
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.outfifo_ovf()
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.set_bit()
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.outfifo_udf()
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.set_bit()
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});
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#[cfg(any(esp32c6, esp32h2))]
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dma.[<out_int_clr_ch $num>].write(|w| {
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w.out_eof()
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.set_bit()
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.out_dscr_err()
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.set_bit()
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.out_done()
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.set_bit()
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.out_total_eof()
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.set_bit()
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.outfifo_ovf()
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.set_bit()
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.outfifo_udf()
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.set_bit()
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});
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#[cfg(esp32s3)]
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dma.[<out_int_clr_ch $num>].write(|w| {
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w.out_eof()
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.set_bit()
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.out_dscr_err()
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.set_bit()
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.out_done()
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.set_bit()
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.out_total_eof()
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.set_bit()
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.outfifo_ovf_l1()
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.set_bit()
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.outfifo_ovf_l3()
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.set_bit()
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.outfifo_udf_l1()
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.set_bit()
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.outfifo_udf_l3()
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.set_bit()
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});
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}
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fn reset_out() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_conf0_ch $num>].modify(|_, w| w.out_rst().set_bit());
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dma.[<out_conf0_ch $num>].modify(|_, w| w.out_rst().clear_bit());
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}
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fn set_out_descriptors(address: u32) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_link_ch $num>].modify(|_, w| unsafe { w.outlink_addr().bits(address) });
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}
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fn has_out_descriptor_error() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().out_dscr_err().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<out_int_raw_ch $num>].read().out_dscr_err().bit();
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ret
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}
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fn set_out_peripheral(peripheral: u8) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_peri_sel_ch $num>].modify(|_, w| w.peri_out_sel().variant(peripheral));
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}
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fn start_out() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_link_ch $num>].modify(|_, w| w.outlink_start().set_bit());
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}
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fn is_out_done() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().out_total_eof().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<out_int_raw_ch $num>].read().out_total_eof().bit();
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ret
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}
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fn last_out_dscr_address() -> usize {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<out_eof_des_addr_ch $num>].read().out_eof_des_addr().bits() as usize
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}
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fn is_out_eof_interrupt_set() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().out_eof().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<out_int_raw_ch $num>].read().out_eof().bit();
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ret
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}
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fn reset_out_eof_interrupt() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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dma.[<int_clr_ch $num>].write(|w| {
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w.out_eof()
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.set_bit()
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});
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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dma.[<out_int_clr_ch $num>].write(|w| {
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w.out_eof()
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.set_bit()
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});
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}
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fn set_in_burstmode(burst_mode: bool) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_conf0_ch $num>].modify(|_,w| {
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w.in_data_burst_en().bit(burst_mode).indscr_burst_en().bit(burst_mode)
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});
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}
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fn set_in_priority(priority: DmaPriority) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_pri_ch $num>].write(|w| {
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w.rx_pri().variant(priority as u8)
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});
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}
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fn clear_in_interrupts() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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dma.[<int_clr_ch $num>].write(|w| {
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w.in_suc_eof()
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.set_bit()
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.in_err_eof()
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.set_bit()
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.in_dscr_err()
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.set_bit()
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.in_dscr_empty()
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.set_bit()
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.in_done()
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.set_bit()
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.infifo_ovf()
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.set_bit()
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.infifo_udf()
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.set_bit()
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});
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#[cfg(any(esp32c6, esp32h2))]
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dma.[<in_int_clr_ch $num>].write(|w| {
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w.in_suc_eof()
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.set_bit()
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.in_err_eof()
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.set_bit()
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.in_dscr_err()
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.set_bit()
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.in_dscr_empty()
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.set_bit()
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.in_done()
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.set_bit()
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.infifo_ovf()
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.set_bit()
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.infifo_udf()
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.set_bit()
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});
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#[cfg(esp32s3)]
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dma.[<in_int_clr_ch $num>].write(|w| {
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w.in_suc_eof()
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.set_bit()
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.in_err_eof()
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.set_bit()
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.in_dscr_err()
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.set_bit()
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.in_dscr_empty()
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.set_bit()
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.in_done()
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.set_bit()
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.infifo_ovf_l1()
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.set_bit()
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.infifo_ovf_l3()
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.set_bit()
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.infifo_udf_l1()
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.set_bit()
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.infifo_udf_l3()
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.set_bit()
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});
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}
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fn reset_in() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_conf0_ch $num>].modify(|_, w| w.in_rst().set_bit());
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dma.[<in_conf0_ch $num>].modify(|_, w| w.in_rst().clear_bit());
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}
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fn set_in_descriptors(address: u32) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_link_ch $num>].modify(|_, w| unsafe { w.inlink_addr().bits(address) });
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}
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fn has_in_descriptor_error() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().in_dscr_err().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<in_int_raw_ch $num>].read().in_dscr_err().bit();
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ret
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}
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fn has_in_descriptor_error_dscr_empty() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().in_dscr_empty().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<in_int_raw_ch $num>].read().in_dscr_empty().bit();
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ret
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}
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fn has_in_descriptor_error_err_eof() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().in_err_eof().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<in_int_raw_ch $num>].read().in_err_eof().bit();
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ret
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}
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fn set_in_peripheral(peripheral: u8) {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_peri_sel_ch $num>].modify(|_, w| w.peri_in_sel().variant(peripheral));
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}
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fn start_in() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_link_ch $num>].modify(|_, w| w.inlink_start().set_bit());
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}
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fn is_in_done() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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#[cfg(not(any(esp32c6, esp32h2, esp32s3)))]
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let ret = dma.[<int_raw_ch $num>].read().in_suc_eof().bit();
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#[cfg(any(esp32c6, esp32h2, esp32s3))]
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let ret = dma.[<in_int_raw_ch $num>].read().in_suc_eof().bit();
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ret
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}
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fn last_in_dscr_address() -> usize {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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dma.[<in_dscr_bf0_ch $num>].read().inlink_dscr_bf0().bits() as usize
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}
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fn is_listening_in_eof() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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cfg_if::cfg_if! {
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if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
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dma.[<in_int_ena_ch $num>].read().in_suc_eof().bit_is_set()
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} else {
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dma.[<int_ena_ch $num>].read().in_suc_eof().bit_is_set()
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}
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}
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}
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fn is_listening_out_eof() -> bool {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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cfg_if::cfg_if! {
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if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
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dma.[<out_int_ena_ch $num>].read().out_total_eof().bit_is_set()
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} else {
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dma.[<int_ena_ch $num>].read().out_total_eof().bit_is_set()
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}
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}
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}
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fn listen_in_eof() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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cfg_if::cfg_if! {
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if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
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dma.[<in_int_ena_ch $num>].modify(|_, w| w.in_suc_eof().set_bit())
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} else {
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dma.[<int_ena_ch $num>].modify(|_, w| w.in_suc_eof().set_bit())
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}
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}
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}
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fn listen_out_eof() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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cfg_if::cfg_if! {
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if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
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dma.[<out_int_ena_ch $num>].modify(|_, w| w.out_total_eof().set_bit())
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} else {
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dma.[<int_ena_ch $num>].modify(|_, w| w.out_total_eof().set_bit())
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}
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}
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}
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fn unlisten_in_eof() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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cfg_if::cfg_if! {
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if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
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dma.[<in_int_ena_ch $num>].modify(|_, w| w.in_suc_eof().clear_bit())
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} else {
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dma.[<int_ena_ch $num>].modify(|_, w| w.in_suc_eof().clear_bit())
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}
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}
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}
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fn unlisten_out_eof() {
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let dma = unsafe { &*crate::peripherals::DMA::PTR };
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cfg_if::cfg_if! {
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if #[cfg(any(esp32c6, esp32h2, esp32s3))] {
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dma.[<out_int_ena_ch $num>].modify(|_, w| w.out_total_eof().clear_bit())
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} else {
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dma.[<int_ena_ch $num>].modify(|_, w| w.out_total_eof().clear_bit())
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}
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}
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}
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}
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#[non_exhaustive]
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pub struct [<Channel $num TxImpl>] {}
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impl<'a> TxChannel<[<Channel $num>]> for [<Channel $num TxImpl>] {
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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#[non_exhaustive]
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pub struct [<Channel $num RxImpl>] {}
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impl<'a> RxChannel<[<Channel $num>]> for [<Channel $num RxImpl>] {
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#[cfg(feature = "async")]
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker {
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static WAKER: embassy_sync::waitqueue::AtomicWaker = embassy_sync::waitqueue::AtomicWaker::new();
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&WAKER
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}
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}
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#[non_exhaustive]
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pub struct [<ChannelCreator $num>] {}
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impl [<ChannelCreator $num>] {
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/// Configure the channel for use
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///
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/// Descriptors should be sized as `((BUFFERSIZE + 4091) / 4092) * 3`. I.e., to
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/// transfer buffers of size `1..=4092`, you need 3 descriptors.
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pub fn configure<'a>(
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self,
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burst_mode: bool,
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tx_descriptors: &'a mut [u32],
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rx_descriptors: &'a mut [u32],
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priority: DmaPriority,
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) -> Channel<'a, [<Channel $num>]> {
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let mut tx_impl = [<Channel $num TxImpl>] {};
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tx_impl.init(burst_mode, priority);
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let tx_channel = ChannelTx {
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descriptors: tx_descriptors,
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burst_mode,
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tx_impl: tx_impl,
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write_offset: 0,
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write_descr_ptr: core::ptr::null(),
|
|
available: 0,
|
|
last_seen_handled_descriptor_ptr: core::ptr::null(),
|
|
buffer_start: core::ptr::null(),
|
|
buffer_len: 0,
|
|
_phantom: PhantomData::default(),
|
|
};
|
|
|
|
let mut rx_impl = [<Channel $num RxImpl>] {};
|
|
rx_impl.init(burst_mode, priority);
|
|
|
|
let rx_channel = ChannelRx {
|
|
descriptors: rx_descriptors,
|
|
burst_mode,
|
|
rx_impl: rx_impl,
|
|
read_descr_ptr: core::ptr::null(),
|
|
available: 0,
|
|
last_seen_handled_descriptor_ptr: core::ptr::null(),
|
|
read_buffer_start: core::ptr::null(),
|
|
_phantom: PhantomData::default(),
|
|
};
|
|
|
|
Channel {
|
|
tx: tx_channel,
|
|
rx: rx_channel,
|
|
}
|
|
}
|
|
}
|
|
|
|
#[non_exhaustive]
|
|
pub struct [<SuitablePeripheral $num>] {}
|
|
impl PeripheralMarker for [<SuitablePeripheral $num>] {}
|
|
|
|
// with GDMA every channel can be used for any peripheral
|
|
impl SpiPeripheral for [<SuitablePeripheral $num>] {}
|
|
impl Spi2Peripheral for [<SuitablePeripheral $num>] {}
|
|
#[cfg(esp32s3)]
|
|
impl Spi3Peripheral for [<SuitablePeripheral $num>] {}
|
|
impl I2sPeripheral for [<SuitablePeripheral $num>] {}
|
|
impl I2s0Peripheral for [<SuitablePeripheral $num>] {}
|
|
impl I2s1Peripheral for [<SuitablePeripheral $num>] {}
|
|
#[cfg(parl_io)]
|
|
impl ParlIoPeripheral for [<SuitablePeripheral $num>] {}
|
|
}
|
|
};
|
|
}
|
|
|
|
impl_channel!(0);
|
|
#[cfg(not(esp32c2))]
|
|
impl_channel!(1);
|
|
#[cfg(not(esp32c2))]
|
|
impl_channel!(2);
|
|
#[cfg(esp32s3)]
|
|
impl_channel!(3);
|
|
#[cfg(esp32s3)]
|
|
impl_channel!(4);
|
|
|
|
/// GDMA Peripheral
|
|
///
|
|
/// This offers the available DMA channels.
|
|
pub struct Gdma<'d> {
|
|
_inner: PeripheralRef<'d, crate::peripherals::DMA>,
|
|
pub channel0: ChannelCreator0,
|
|
#[cfg(not(esp32c2))]
|
|
pub channel1: ChannelCreator1,
|
|
#[cfg(not(esp32c2))]
|
|
pub channel2: ChannelCreator2,
|
|
#[cfg(esp32s3)]
|
|
pub channel3: ChannelCreator3,
|
|
#[cfg(esp32s3)]
|
|
pub channel4: ChannelCreator4,
|
|
}
|
|
|
|
impl<'d> Gdma<'d> {
|
|
/// Create a DMA instance.
|
|
pub fn new(
|
|
dma: impl crate::peripheral::Peripheral<P = crate::peripherals::DMA> + 'd,
|
|
peripheral_clock_control: &mut PeripheralClockControl,
|
|
) -> Gdma<'d> {
|
|
crate::into_ref!(dma);
|
|
|
|
peripheral_clock_control.enable(Peripheral::Gdma);
|
|
dma.misc_conf.modify(|_, w| w.ahbm_rst_inter().set_bit());
|
|
dma.misc_conf.modify(|_, w| w.ahbm_rst_inter().clear_bit());
|
|
dma.misc_conf.modify(|_, w| w.clk_en().set_bit());
|
|
|
|
Gdma {
|
|
_inner: dma,
|
|
channel0: ChannelCreator0 {},
|
|
#[cfg(not(esp32c2))]
|
|
channel1: ChannelCreator1 {},
|
|
#[cfg(not(esp32c2))]
|
|
channel2: ChannelCreator2 {},
|
|
#[cfg(esp32s3)]
|
|
channel3: ChannelCreator3 {},
|
|
#[cfg(esp32s3)]
|
|
channel4: ChannelCreator4 {},
|
|
}
|
|
}
|
|
}
|