6eca968bb8
* Add LLD option for all Xtensa chips * changelog * Fix linkerscript for esp32s3 rtc fast ram region
32 lines
1.2 KiB
Plaintext
32 lines
1.2 KiB
Plaintext
/* override entry point */
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ENTRY(ESP32Reset)
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/* reserved at the start of DRAM */
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RESERVE_DRAM = 0x8000;
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/* Specify main memory areas */
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MEMORY
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{
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iram_seg ( RX ) : ORIGIN = 0x40370400 + RESERVE_DRAM, len = 328k - 0x400
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dram_seg ( RW ) : ORIGIN = 0x3FC80000 + RESERVE_DRAM, len = 328k - RESERVE_DRAM
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reserved_for_boot_seg : ORIGIN = 0x3FFDC200, len = 144k /* ???? SRAM1; reserved for static ROM usage; can be used for heap */
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/* external flash
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The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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irom_seg ( RX ) : ORIGIN = 0x42000000, len = 4M
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drom_seg ( R ) : ORIGIN = 0x3C000000, len = 4M
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/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
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rtc_fast_seg(RWX) : ORIGIN = 0x600fe000, len = 8k
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : ORIGIN = 0x50000000, len = 8k
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}
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